[deliverable/linux.git] / drivers / clk / at91 / clk-main.c

/*
 *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/at91_pmc.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/wait.h>

#include "pmc.h"

#define SLOW_CLOCK_FREQ		32768
#define MAINF_DIV		16
#define MAINFRDY_TIMEOUT	(((MAINF_DIV + 1) * USEC_PER_SEC) / \
				 SLOW_CLOCK_FREQ)
#define MAINF_LOOP_MIN_WAIT	(USEC_PER_SEC / SLOW_CLOCK_FREQ)
#define MAINF_LOOP_MAX_WAIT	MAINFRDY_TIMEOUT

#define MOR_KEY_MASK		(0xff << 16)

struct clk_main_osc {
	struct clk_hw hw;
	struct at91_pmc *pmc;
	unsigned int irq;
	wait_queue_head_t wait;
};

#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)

struct clk_main_rc_osc {
	struct clk_hw hw;
	struct at91_pmc *pmc;
	unsigned int irq;
	wait_queue_head_t wait;
	unsigned long frequency;
	unsigned long accuracy;
};

#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)

struct clk_rm9200_main {
	struct clk_hw hw;
	struct at91_pmc *pmc;
};

#define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)

struct clk_sam9x5_main {
	struct clk_hw hw;
	struct at91_pmc *pmc;
	unsigned int irq;
	wait_queue_head_t wait;
	u8 parent;
};

#define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)

static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id)
{
	struct clk_main_osc *osc = dev_id;

	wake_up(&osc->wait);
	disable_irq_nosync(osc->irq);

	return IRQ_HANDLED;
}

static int clk_main_osc_prepare(struct clk_hw *hw)
{
	struct clk_main_osc *osc = to_clk_main_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp;

	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
	if (tmp & AT91_PMC_OSCBYPASS)
		return 0;

	if (!(tmp & AT91_PMC_MOSCEN)) {
		tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
		pmc_write(pmc, AT91_CKGR_MOR, tmp);
	}

	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
		enable_irq(osc->irq);
		wait_event(osc->wait,
			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
	}

	return 0;
}

static void clk_main_osc_unprepare(struct clk_hw *hw)
{
	struct clk_main_osc *osc = to_clk_main_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);

	if (tmp & AT91_PMC_OSCBYPASS)
		return;

	if (!(tmp & AT91_PMC_MOSCEN))
		return;

	tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
	pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
}

static int clk_main_osc_is_prepared(struct clk_hw *hw)
{
	struct clk_main_osc *osc = to_clk_main_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);

	if (tmp & AT91_PMC_OSCBYPASS)
		return 1;

	return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) &&
		  (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN));
}

static const struct clk_ops main_osc_ops = {
	.prepare = clk_main_osc_prepare,
	.unprepare = clk_main_osc_unprepare,
	.is_prepared = clk_main_osc_is_prepared,
};

static struct clk * __init
at91_clk_register_main_osc(struct at91_pmc *pmc,
			   unsigned int irq,
			   const char *name,
			   const char *parent_name,
			   bool bypass)
{
	int ret;
	struct clk_main_osc *osc;
	struct clk *clk = NULL;
	struct clk_init_data init;

	if (!pmc || !irq || !name || !parent_name)
		return ERR_PTR(-EINVAL);

	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
	if (!osc)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &main_osc_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = CLK_IGNORE_UNUSED;

	osc->hw.init = &init;
	osc->pmc = pmc;
	osc->irq = irq;

	init_waitqueue_head(&osc->wait);
	irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
	ret = request_irq(osc->irq, clk_main_osc_irq_handler,
			  IRQF_TRIGGER_HIGH, name, osc);
	if (ret) {
		kfree(osc);
		return ERR_PTR(ret);
	}

	if (bypass)
		pmc_write(pmc, AT91_CKGR_MOR,
			  (pmc_read(pmc, AT91_CKGR_MOR) &
			   ~(MOR_KEY_MASK | AT91_PMC_MOSCEN)) |
			  AT91_PMC_OSCBYPASS | AT91_PMC_KEY);

	clk = clk_register(NULL, &osc->hw);
	if (IS_ERR(clk)) {
		free_irq(irq, osc);
		kfree(osc);
	}

	return clk;
}

void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np,
					     struct at91_pmc *pmc)
{
	struct clk *clk;
	unsigned int irq;
	const char *name = np->name;
	const char *parent_name;
	bool bypass;

	of_property_read_string(np, "clock-output-names", &name);
	bypass = of_property_read_bool(np, "atmel,osc-bypass");
	parent_name = of_clk_get_parent_name(np, 0);

	irq = irq_of_parse_and_map(np, 0);
	if (!irq)
		return;

	clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass);
	if (IS_ERR(clk))
		return;

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}

static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id)
{
	struct clk_main_rc_osc *osc = dev_id;

	wake_up(&osc->wait);
	disable_irq_nosync(osc->irq);

	return IRQ_HANDLED;
}

static int clk_main_rc_osc_prepare(struct clk_hw *hw)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp;

	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;

	if (!(tmp & AT91_PMC_MOSCRCEN)) {
		tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY;
		pmc_write(pmc, AT91_CKGR_MOR, tmp);
	}

	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) {
		enable_irq(osc->irq);
		wait_event(osc->wait,
			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS);
	}

	return 0;
}

static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
	struct at91_pmc *pmc = osc->pmc;
	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);

	if (!(tmp & AT91_PMC_MOSCRCEN))
		return;

	tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN);
	pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
}

static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
	struct at91_pmc *pmc = osc->pmc;

	return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) &&
		  (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN));
}

static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);

	return osc->frequency;
}

static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
						     unsigned long parent_acc)
{
	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);

	return osc->accuracy;
}

static const struct clk_ops main_rc_osc_ops = {
	.prepare = clk_main_rc_osc_prepare,
	.unprepare = clk_main_rc_osc_unprepare,
	.is_prepared = clk_main_rc_osc_is_prepared,
	.recalc_rate = clk_main_rc_osc_recalc_rate,
	.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
};

static struct clk * __init
at91_clk_register_main_rc_osc(struct at91_pmc *pmc,
			      unsigned int irq,
			      const char *name,
			      u32 frequency, u32 accuracy)
{
	int ret;
	struct clk_main_rc_osc *osc;
	struct clk *clk = NULL;
	struct clk_init_data init;

	if (!pmc || !irq || !name || !frequency)
		return ERR_PTR(-EINVAL);

	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
	if (!osc)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &main_rc_osc_ops;
	init.parent_names = NULL;
	init.num_parents = 0;
	init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;

	osc->hw.init = &init;
	osc->pmc = pmc;
	osc->irq = irq;
	osc->frequency = frequency;
	osc->accuracy = accuracy;

	init_waitqueue_head(&osc->wait);
	irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
	ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler,
			  IRQF_TRIGGER_HIGH, name, osc);
	if (ret)
		return ERR_PTR(ret);

	clk = clk_register(NULL, &osc->hw);
	if (IS_ERR(clk)) {
		free_irq(irq, osc);
		kfree(osc);
	}

	return clk;
}

void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np,
						struct at91_pmc *pmc)
{
	struct clk *clk;
	unsigned int irq;
	u32 frequency = 0;
	u32 accuracy = 0;
	const char *name = np->name;

	of_property_read_string(np, "clock-output-names", &name);
	of_property_read_u32(np, "clock-frequency", &frequency);
	of_property_read_u32(np, "clock-accuracy", &accuracy);

	irq = irq_of_parse_and_map(np, 0);
	if (!irq)
		return;

	clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency,
					    accuracy);
	if (IS_ERR(clk))
		return;

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}


static int clk_main_probe_frequency(struct at91_pmc *pmc)
{
	unsigned long prep_time, timeout;
	u32 tmp;

	timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
	do {
		prep_time = jiffies;
		tmp = pmc_read(pmc, AT91_CKGR_MCFR);
		if (tmp & AT91_PMC_MAINRDY)
			return 0;
		usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
	} while (time_before(prep_time, timeout));

	return -ETIMEDOUT;
}

static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc,
					  unsigned long parent_rate)
{
	u32 tmp;

	if (parent_rate)
		return parent_rate;

	pr_warn("Main crystal frequency not set, using approximate value\n");
	tmp = pmc_read(pmc, AT91_CKGR_MCFR);
	if (!(tmp & AT91_PMC_MAINRDY))
		return 0;

	return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
}

static int clk_rm9200_main_prepare(struct clk_hw *hw)
{
	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);

	return clk_main_probe_frequency(clkmain->pmc);
}

static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
{
	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);

	return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY);
}

static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);

	return clk_main_recalc_rate(clkmain->pmc, parent_rate);
}

static const struct clk_ops rm9200_main_ops = {
	.prepare = clk_rm9200_main_prepare,
	.is_prepared = clk_rm9200_main_is_prepared,
	.recalc_rate = clk_rm9200_main_recalc_rate,
};

static struct clk * __init
at91_clk_register_rm9200_main(struct at91_pmc *pmc,
			      const char *name,
			      const char *parent_name)
{
	struct clk_rm9200_main *clkmain;
	struct clk *clk = NULL;
	struct clk_init_data init;

	if (!pmc || !name)
		return ERR_PTR(-EINVAL);

	if (!parent_name)
		return ERR_PTR(-EINVAL);

	clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
	if (!clkmain)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &rm9200_main_ops;
	init.parent_names = &parent_name;
	init.num_parents = 1;
	init.flags = 0;

	clkmain->hw.init = &init;
	clkmain->pmc = pmc;

	clk = clk_register(NULL, &clkmain->hw);
	if (IS_ERR(clk))
		kfree(clkmain);

	return clk;
}

void __init of_at91rm9200_clk_main_setup(struct device_node *np,
					 struct at91_pmc *pmc)
{
	struct clk *clk;
	const char *parent_name;
	const char *name = np->name;

	parent_name = of_clk_get_parent_name(np, 0);
	of_property_read_string(np, "clock-output-names", &name);

	clk = at91_clk_register_rm9200_main(pmc, name, parent_name);
	if (IS_ERR(clk))
		return;

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}

static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id)
{
	struct clk_sam9x5_main *clkmain = dev_id;

	wake_up(&clkmain->wait);
	disable_irq_nosync(clkmain->irq);

	return IRQ_HANDLED;
}

static int clk_sam9x5_main_prepare(struct clk_hw *hw)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	struct at91_pmc *pmc = clkmain->pmc;

	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
		enable_irq(clkmain->irq);
		wait_event(clkmain->wait,
			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
	}

	return clk_main_probe_frequency(pmc);
}

static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);

	return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
}

static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
						 unsigned long parent_rate)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);

	return clk_main_recalc_rate(clkmain->pmc, parent_rate);
}

static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	struct at91_pmc *pmc = clkmain->pmc;
	u32 tmp;

	if (index > 1)
		return -EINVAL;

	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;

	if (index && !(tmp & AT91_PMC_MOSCSEL))
		pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
	else if (!index && (tmp & AT91_PMC_MOSCSEL))
		pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);

	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
		enable_irq(clkmain->irq);
		wait_event(clkmain->wait,
			   pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
	}

	return 0;
}

static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
{
	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);

	return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN);
}

static const struct clk_ops sam9x5_main_ops = {
	.prepare = clk_sam9x5_main_prepare,
	.is_prepared = clk_sam9x5_main_is_prepared,
	.recalc_rate = clk_sam9x5_main_recalc_rate,
	.set_parent = clk_sam9x5_main_set_parent,
	.get_parent = clk_sam9x5_main_get_parent,
};

static struct clk * __init
at91_clk_register_sam9x5_main(struct at91_pmc *pmc,
			      unsigned int irq,
			      const char *name,
			      const char **parent_names,
			      int num_parents)
{
	int ret;
	struct clk_sam9x5_main *clkmain;
	struct clk *clk = NULL;
	struct clk_init_data init;

	if (!pmc || !irq || !name)
		return ERR_PTR(-EINVAL);

	if (!parent_names || !num_parents)
		return ERR_PTR(-EINVAL);

	clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
	if (!clkmain)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &sam9x5_main_ops;
	init.parent_names = parent_names;
	init.num_parents = num_parents;
	init.flags = CLK_SET_PARENT_GATE;

	clkmain->hw.init = &init;
	clkmain->pmc = pmc;
	clkmain->irq = irq;
	clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) &
			     AT91_PMC_MOSCEN);
	init_waitqueue_head(&clkmain->wait);
	irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
	ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler,
			  IRQF_TRIGGER_HIGH, name, clkmain);
	if (ret)
		return ERR_PTR(ret);

	clk = clk_register(NULL, &clkmain->hw);
	if (IS_ERR(clk)) {
		free_irq(clkmain->irq, clkmain);
		kfree(clkmain);
	}

	return clk;
}

void __init of_at91sam9x5_clk_main_setup(struct device_node *np,
					 struct at91_pmc *pmc)
{
	struct clk *clk;
	const char *parent_names[2];
	unsigned int num_parents;
	unsigned int irq;
	const char *name = np->name;

	num_parents = of_clk_get_parent_count(np);
	if (num_parents == 0 || num_parents > 2)
		return;

	of_clk_parent_fill(np, parent_names, num_parents);

	of_property_read_string(np, "clock-output-names", &name);

	irq = irq_of_parse_and_map(np, 0);
	if (!irq)
		return;

	clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names,
					    num_parents);
	if (IS_ERR(clk))
		return;

	of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
Commit	Line	Data
38d34c31 BB	1	/*
	2	* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	*/
	10
	11	#include <linux/clk-provider.h>
	12	#include <linux/clkdev.h>
	13	#include <linux/clk/at91_pmc.h>
	14	#include <linux/delay.h>
	15	#include <linux/of.h>
	16	#include <linux/of_address.h>
	17	#include <linux/of_irq.h>
	18	#include <linux/io.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/sched.h>
	22	#include <linux/wait.h>
	23
	24	#include "pmc.h"
	25
	26	#define SLOW_CLOCK_FREQ 32768
	27	#define MAINF_DIV 16
	28	#define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
	29	SLOW_CLOCK_FREQ)
	30	#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
	31	#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
	32
27cb1c20 BB	33	#define MOR_KEY_MASK (0xff << 16)
	34
	35	struct clk_main_osc {
38d34c31 BB	36	struct clk_hw hw;
38d34c31 BB	37	struct at91_pmc *pmc;
38d34c31 BB	38	unsigned int irq;
	39	wait_queue_head_t wait;
	40	};
	41
27cb1c20 BB	42	#define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
	43
	44	struct clk_main_rc_osc {
	45	struct clk_hw hw;
	46	struct at91_pmc *pmc;
	47	unsigned int irq;
	48	wait_queue_head_t wait;
	49	unsigned long frequency;
	50	unsigned long accuracy;
	51	};
	52
	53	#define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
	54
	55	struct clk_rm9200_main {
	56	struct clk_hw hw;
	57	struct at91_pmc *pmc;
	58	};
	59
	60	#define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
38d34c31	61
27cb1c20 BB	62	struct clk_sam9x5_main {
	63	struct clk_hw hw;
	64	struct at91_pmc *pmc;
	65	unsigned int irq;
	66	wait_queue_head_t wait;
	67	u8 parent;
	68	};
	69
	70	#define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
	71
	72	static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id)
38d34c31	73	{
27cb1c20	74	struct clk_main_osc *osc = dev_id;
38d34c31	75
27cb1c20 BB	76	wake_up(&osc->wait);
27cb1c20 BB	77	disable_irq_nosync(osc->irq);
38d34c31 BB	78
	79	return IRQ_HANDLED;
	80	}
	81
27cb1c20	82	static int clk_main_osc_prepare(struct clk_hw *hw)
38d34c31	83	{
27cb1c20 BB	84	struct clk_main_osc *osc = to_clk_main_osc(hw);
27cb1c20 BB	85	struct at91_pmc *pmc = osc->pmc;
38d34c31 BB	86	u32 tmp;
38d34c31 BB	87
27cb1c20 BB	88	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
	89	if (tmp & AT91_PMC_OSCBYPASS)
	90	return 0;
	91
	92	if (!(tmp & AT91_PMC_MOSCEN)) {
	93	tmp \|= AT91_PMC_MOSCEN \| AT91_PMC_KEY;
	94	pmc_write(pmc, AT91_CKGR_MOR, tmp);
	95	}
	96
38d34c31	97	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
27cb1c20 BB	98	enable_irq(osc->irq);
27cb1c20 BB	99	wait_event(osc->wait,
38d34c31 BB	100	pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
	101	}
	102
27cb1c20 BB	103	return 0;
	104	}
	105
	106	static void clk_main_osc_unprepare(struct clk_hw *hw)
	107	{
	108	struct clk_main_osc *osc = to_clk_main_osc(hw);
	109	struct at91_pmc *pmc = osc->pmc;
	110	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
	111
	112	if (tmp & AT91_PMC_OSCBYPASS)
	113	return;
	114
	115	if (!(tmp & AT91_PMC_MOSCEN))
	116	return;
	117
	118	tmp &= ~(AT91_PMC_KEY \| AT91_PMC_MOSCEN);
	119	pmc_write(pmc, AT91_CKGR_MOR, tmp \| AT91_PMC_KEY);
	120	}
	121
	122	static int clk_main_osc_is_prepared(struct clk_hw *hw)
	123	{
	124	struct clk_main_osc *osc = to_clk_main_osc(hw);
	125	struct at91_pmc *pmc = osc->pmc;
	126	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
	127
	128	if (tmp & AT91_PMC_OSCBYPASS)
	129	return 1;
	130
	131	return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) &&
	132	(pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN));
	133	}
	134
	135	static const struct clk_ops main_osc_ops = {
	136	.prepare = clk_main_osc_prepare,
	137	.unprepare = clk_main_osc_unprepare,
	138	.is_prepared = clk_main_osc_is_prepared,
	139	};
	140
	141	static struct clk * __init
	142	at91_clk_register_main_osc(struct at91_pmc *pmc,
	143	unsigned int irq,
	144	const char *name,
	145	const char *parent_name,
	146	bool bypass)
	147	{
	148	int ret;
	149	struct clk_main_osc *osc;
	150	struct clk *clk = NULL;
	151	struct clk_init_data init;
	152
	153	if (!pmc \|\| !irq \|\| !name \|\| !parent_name)
	154	return ERR_PTR(-EINVAL);
	155
	156	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
	157	if (!osc)
	158	return ERR_PTR(-ENOMEM);
	159
	160	init.name = name;
	161	init.ops = &main_osc_ops;
	162	init.parent_names = &parent_name;
	163	init.num_parents = 1;
	164	init.flags = CLK_IGNORE_UNUSED;
	165
	166	osc->hw.init = &init;
167	osc->pmc = pmc;
168	osc->irq = irq;
169
170	init_waitqueue_head(&osc->wait);
171	irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
172	ret = request_irq(osc->irq, clk_main_osc_irq_handler,
173	IRQF_TRIGGER_HIGH, name, osc);
c76a024e DD	174	if (ret) {
c76a024e DD	175	kfree(osc);
27cb1c20	176	return ERR_PTR(ret);
c76a024e	177	}
27cb1c20 BB	178
	179	if (bypass)
	180	pmc_write(pmc, AT91_CKGR_MOR,
	181	(pmc_read(pmc, AT91_CKGR_MOR) &
	182	~(MOR_KEY_MASK \| AT91_PMC_MOSCEN)) \|
	183	AT91_PMC_OSCBYPASS \| AT91_PMC_KEY);
	184
	185	clk = clk_register(NULL, &osc->hw);
	186	if (IS_ERR(clk)) {
	187	free_irq(irq, osc);
	188	kfree(osc);
	189	}
	190
	191	return clk;
	192	}
	193
	194	void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np,
	195	struct at91_pmc *pmc)
	196	{
	197	struct clk *clk;
	198	unsigned int irq;
	199	const char *name = np->name;
	200	const char *parent_name;
	201	bool bypass;
	202
	203	of_property_read_string(np, "clock-output-names", &name);
	204	bypass = of_property_read_bool(np, "atmel,osc-bypass");
	205	parent_name = of_clk_get_parent_name(np, 0);
	206
	207	irq = irq_of_parse_and_map(np, 0);
	208	if (!irq)
	209	return;
	210
	211	clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass);
	212	if (IS_ERR(clk))
	213	return;
	214
	215	of_clk_add_provider(np, of_clk_src_simple_get, clk);
	216	}
	217
	218	static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id)
	219	{
	220	struct clk_main_rc_osc *osc = dev_id;
	221
	222	wake_up(&osc->wait);
	223	disable_irq_nosync(osc->irq);
	224
	225	return IRQ_HANDLED;
	226	}
	227
	228	static int clk_main_rc_osc_prepare(struct clk_hw *hw)
	229	{
	230	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
	231	struct at91_pmc *pmc = osc->pmc;
	232	u32 tmp;
	233
	234	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
	235
	236	if (!(tmp & AT91_PMC_MOSCRCEN)) {
	237	tmp \|= AT91_PMC_MOSCRCEN \| AT91_PMC_KEY;
	238	pmc_write(pmc, AT91_CKGR_MOR, tmp);
	239	}
	240
	241	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) {
242	enable_irq(osc->irq);
243	wait_event(osc->wait,
244	pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS);
245	}
246
247	return 0;
248	}
249
250	static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
251	{
252	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
253	struct at91_pmc *pmc = osc->pmc;
254	u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
255
256	if (!(tmp & AT91_PMC_MOSCRCEN))
257	return;
258
259	tmp &= ~(MOR_KEY_MASK \| AT91_PMC_MOSCRCEN);
260	pmc_write(pmc, AT91_CKGR_MOR, tmp \| AT91_PMC_KEY);
261	}
262
263	static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
264	{
265	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
266	struct at91_pmc *pmc = osc->pmc;
267
268	return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) &&
269	(pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN));
270	}
271
272	static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
273	unsigned long parent_rate)
274	{
275	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
276
277	return osc->frequency;
278	}
279
280	static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
281	unsigned long parent_acc)
282	{
283	struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
284
285	return osc->accuracy;
286	}
287
288	static const struct clk_ops main_rc_osc_ops = {
289	.prepare = clk_main_rc_osc_prepare,
290	.unprepare = clk_main_rc_osc_unprepare,
291	.is_prepared = clk_main_rc_osc_is_prepared,
292	.recalc_rate = clk_main_rc_osc_recalc_rate,
293	.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
294	};
295
296	static struct clk * __init
297	at91_clk_register_main_rc_osc(struct at91_pmc *pmc,
298	unsigned int irq,
299	const char *name,
300	u32 frequency, u32 accuracy)
301	{
302	int ret;
303	struct clk_main_rc_osc *osc;
304	struct clk *clk = NULL;
305	struct clk_init_data init;
306
307	if (!pmc \|\| !irq \|\| !name \|\| !frequency)
308	return ERR_PTR(-EINVAL);
309
310	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
311	if (!osc)
312	return ERR_PTR(-ENOMEM);
313
314	init.name = name;
315	init.ops = &main_rc_osc_ops;
316	init.parent_names = NULL;
317	init.num_parents = 0;
318	init.flags = CLK_IS_ROOT \| CLK_IGNORE_UNUSED;
319
320	osc->hw.init = &init;
321	osc->pmc = pmc;
322	osc->irq = irq;
323	osc->frequency = frequency;
324	osc->accuracy = accuracy;
325
326	init_waitqueue_head(&osc->wait);
327	irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
328	ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler,
329	IRQF_TRIGGER_HIGH, name, osc);
330	if (ret)
331	return ERR_PTR(ret);
332
333	clk = clk_register(NULL, &osc->hw);
334	if (IS_ERR(clk)) {
335	free_irq(irq, osc);
336	kfree(osc);
337	}
338
339	return clk;
340	}
341
342	void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np,
343	struct at91_pmc *pmc)
344	{
345	struct clk *clk;
346	unsigned int irq;
347	u32 frequency = 0;
348	u32 accuracy = 0;
349	const char *name = np->name;
350
351	of_property_read_string(np, "clock-output-names", &name);
352	of_property_read_u32(np, "clock-frequency", &frequency);
353	of_property_read_u32(np, "clock-accuracy", &accuracy);
354
355	irq = irq_of_parse_and_map(np, 0);
356	if (!irq)
357	return;
358
359	clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency,
360	accuracy);
361	if (IS_ERR(clk))
362	return;
363
364	of_clk_add_provider(np, of_clk_src_simple_get, clk);
365	}
366
367
368	static int clk_main_probe_frequency(struct at91_pmc *pmc)
369	{
370	unsigned long prep_time, timeout;
371	u32 tmp;
38d34c31 BB	372
	373	timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
	374	do {
27cb1c20	375	prep_time = jiffies;
38d34c31 BB	376	tmp = pmc_read(pmc, AT91_CKGR_MCFR);
	377	if (tmp & AT91_PMC_MAINRDY)
	378	return 0;
	379	usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
27cb1c20	380	} while (time_before(prep_time, timeout));
38d34c31	381
27cb1c20	382	return -ETIMEDOUT;
38d34c31 BB	383	}
38d34c31 BB	384
27cb1c20 BB	385	static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc,
27cb1c20 BB	386	unsigned long parent_rate)
38d34c31	387	{
27cb1c20 BB	388	u32 tmp;
	389
	390	if (parent_rate)
	391	return parent_rate;
	392
4da66b63	393	pr_warn("Main crystal frequency not set, using approximate value\n");
27cb1c20 BB	394	tmp = pmc_read(pmc, AT91_CKGR_MCFR);
	395	if (!(tmp & AT91_PMC_MAINRDY))
	396	return 0;
38d34c31	397
27cb1c20	398	return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
38d34c31 BB	399	}
38d34c31 BB	400
27cb1c20	401	static int clk_rm9200_main_prepare(struct clk_hw *hw)
38d34c31	402	{
27cb1c20 BB	403	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
	404
	405	return clk_main_probe_frequency(clkmain->pmc);
	406	}
	407
	408	static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
	409	{
	410	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
	411
	412	return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY);
	413	}
	414
	415	static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
	416	unsigned long parent_rate)
	417	{
	418	struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
	419
	420	return clk_main_recalc_rate(clkmain->pmc, parent_rate);
	421	}
	422
	423	static const struct clk_ops rm9200_main_ops = {
	424	.prepare = clk_rm9200_main_prepare,
	425	.is_prepared = clk_rm9200_main_is_prepared,
	426	.recalc_rate = clk_rm9200_main_recalc_rate,
	427	};
	428
	429	static struct clk * __init
	430	at91_clk_register_rm9200_main(struct at91_pmc *pmc,
	431	const char *name,
	432	const char *parent_name)
	433	{
	434	struct clk_rm9200_main *clkmain;
	435	struct clk *clk = NULL;
	436	struct clk_init_data init;
	437
	438	if (!pmc \|\| !name)
	439	return ERR_PTR(-EINVAL);
	440
	441	if (!parent_name)
	442	return ERR_PTR(-EINVAL);
	443
	444	clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
	445	if (!clkmain)
	446	return ERR_PTR(-ENOMEM);
	447
	448	init.name = name;
	449	init.ops = &rm9200_main_ops;
	450	init.parent_names = &parent_name;
	451	init.num_parents = 1;
	452	init.flags = 0;
	453
	454	clkmain->hw.init = &init;
	455	clkmain->pmc = pmc;
	456
	457	clk = clk_register(NULL, &clkmain->hw);
	458	if (IS_ERR(clk))
	459	kfree(clkmain);
	460
	461	return clk;
	462	}
	463
	464	void __init of_at91rm9200_clk_main_setup(struct device_node *np,
	465	struct at91_pmc *pmc)
	466	{
467	struct clk *clk;
468	const char *parent_name;
469	const char *name = np->name;
470
471	parent_name = of_clk_get_parent_name(np, 0);
472	of_property_read_string(np, "clock-output-names", &name);
473
474	clk = at91_clk_register_rm9200_main(pmc, name, parent_name);
475	if (IS_ERR(clk))
476	return;
477
478	of_clk_add_provider(np, of_clk_src_simple_get, clk);
479	}
480
481	static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id)
482	{
483	struct clk_sam9x5_main *clkmain = dev_id;
484
485	wake_up(&clkmain->wait);
486	disable_irq_nosync(clkmain->irq);
487
488	return IRQ_HANDLED;
489	}
490
491	static int clk_sam9x5_main_prepare(struct clk_hw *hw)
492	{
493	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
38d34c31 BB	494	struct at91_pmc *pmc = clkmain->pmc;
38d34c31 BB	495
27cb1c20 BB	496	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
	497	enable_irq(clkmain->irq);
	498	wait_event(clkmain->wait,
	499	pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
	500	}
	501
	502	return clk_main_probe_frequency(pmc);
	503	}
38d34c31	504
27cb1c20 BB	505	static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
	506	{
	507	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
38d34c31	508
27cb1c20	509	return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
38d34c31 BB	510	}
38d34c31 BB	511
27cb1c20 BB	512	static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
	513	unsigned long parent_rate)
	514	{
	515	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	516
	517	return clk_main_recalc_rate(clkmain->pmc, parent_rate);
	518	}
	519
	520	static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
	521	{
	522	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	523	struct at91_pmc *pmc = clkmain->pmc;
	524	u32 tmp;
	525
	526	if (index > 1)
	527	return -EINVAL;
	528
	529	tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
	530
	531	if (index && !(tmp & AT91_PMC_MOSCSEL))
	532	pmc_write(pmc, AT91_CKGR_MOR, tmp \| AT91_PMC_MOSCSEL);
	533	else if (!index && (tmp & AT91_PMC_MOSCSEL))
	534	pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
	535
	536	while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
	537	enable_irq(clkmain->irq);
	538	wait_event(clkmain->wait,
	539	pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
	540	}
	541
	542	return 0;
	543	}
	544
	545	static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
	546	{
	547	struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
	548
	549	return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN);
	550	}
	551
	552	static const struct clk_ops sam9x5_main_ops = {
	553	.prepare = clk_sam9x5_main_prepare,
	554	.is_prepared = clk_sam9x5_main_is_prepared,
	555	.recalc_rate = clk_sam9x5_main_recalc_rate,
	556	.set_parent = clk_sam9x5_main_set_parent,
	557	.get_parent = clk_sam9x5_main_get_parent,
38d34c31 BB	558	};
	559
	560	static struct clk * __init
27cb1c20 BB	561	at91_clk_register_sam9x5_main(struct at91_pmc *pmc,
	562	unsigned int irq,
	563	const char *name,
	564	const char **parent_names,
	565	int num_parents)
38d34c31 BB	566	{
38d34c31 BB	567	int ret;
27cb1c20	568	struct clk_sam9x5_main *clkmain;
38d34c31 BB	569	struct clk *clk = NULL;
	570	struct clk_init_data init;
	571
	572	if (!pmc \|\| !irq \|\| !name)
	573	return ERR_PTR(-EINVAL);
	574
27cb1c20	575	if (!parent_names \|\| !num_parents)
38d34c31 BB	576	return ERR_PTR(-EINVAL);
	577
	578	clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
	579	if (!clkmain)
	580	return ERR_PTR(-ENOMEM);
	581
	582	init.name = name;
27cb1c20 BB	583	init.ops = &sam9x5_main_ops;
	584	init.parent_names = parent_names;
	585	init.num_parents = num_parents;
	586	init.flags = CLK_SET_PARENT_GATE;
38d34c31 BB	587
38d34c31 BB	588	clkmain->hw.init = &init;
38d34c31 BB	589	clkmain->pmc = pmc;
38d34c31 BB	590	clkmain->irq = irq;
27cb1c20 BB	591	clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) &
27cb1c20 BB	592	AT91_PMC_MOSCEN);
38d34c31 BB	593	init_waitqueue_head(&clkmain->wait);
38d34c31 BB	594	irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
27cb1c20 BB	595	ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler,
27cb1c20 BB	596	IRQF_TRIGGER_HIGH, name, clkmain);
38d34c31 BB	597	if (ret)
	598	return ERR_PTR(ret);
	599
	600	clk = clk_register(NULL, &clkmain->hw);
	601	if (IS_ERR(clk)) {
	602	free_irq(clkmain->irq, clkmain);
	603	kfree(clkmain);
	604	}
	605
	606	return clk;
	607	}
	608
27cb1c20 BB	609	void __init of_at91sam9x5_clk_main_setup(struct device_node *np,
27cb1c20 BB	610	struct at91_pmc *pmc)
38d34c31 BB	611	{
38d34c31 BB	612	struct clk *clk;
27cb1c20	613	const char *parent_names[2];
8c1b1e54	614	unsigned int num_parents;
38d34c31	615	unsigned int irq;
38d34c31	616	const char *name = np->name;
27cb1c20	617
51a43be9	618	num_parents = of_clk_get_parent_count(np);
8c1b1e54	619	if (num_parents == 0 \|\| num_parents > 2)
27cb1c20 BB	620	return;
27cb1c20 BB	621
f0557fbe	622	of_clk_parent_fill(np, parent_names, num_parents);
38d34c31	623
38d34c31	624	of_property_read_string(np, "clock-output-names", &name);
27cb1c20	625
38d34c31 BB	626	irq = irq_of_parse_and_map(np, 0);
	627	if (!irq)
	628	return;
	629
27cb1c20 BB	630	clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names,
27cb1c20 BB	631	num_parents);
38d34c31 BB	632	if (IS_ERR(clk))
	633	return;
	634
	635	of_clk_add_provider(np, of_clk_src_simple_get, clk);
	636	}