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1a748d2b BB |
1 | /* |
2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <linux/clk-provider.h> | |
12 | #include <linux/clkdev.h> | |
13 | #include <linux/clk/at91_pmc.h> | |
14 | #include <linux/of.h> | |
1bdf0232 BB |
15 | #include <linux/mfd/syscon.h> |
16 | #include <linux/regmap.h> | |
1a748d2b BB |
17 | |
18 | #include "pmc.h" | |
19 | ||
20 | #define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw) | |
21 | ||
22 | struct clk_plldiv { | |
23 | struct clk_hw hw; | |
1bdf0232 | 24 | struct regmap *regmap; |
1a748d2b BB |
25 | }; |
26 | ||
27 | static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw, | |
28 | unsigned long parent_rate) | |
29 | { | |
30 | struct clk_plldiv *plldiv = to_clk_plldiv(hw); | |
1bdf0232 | 31 | unsigned int mckr; |
1a748d2b | 32 | |
1bdf0232 BB |
33 | regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr); |
34 | ||
35 | if (mckr & AT91_PMC_PLLADIV2) | |
1a748d2b BB |
36 | return parent_rate / 2; |
37 | ||
38 | return parent_rate; | |
39 | } | |
40 | ||
41 | static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate, | |
42 | unsigned long *parent_rate) | |
43 | { | |
44 | unsigned long div; | |
45 | ||
46 | if (rate > *parent_rate) | |
47 | return *parent_rate; | |
48 | div = *parent_rate / 2; | |
49 | if (rate < div) | |
50 | return div; | |
51 | ||
52 | if (rate - div < *parent_rate - rate) | |
53 | return div; | |
54 | ||
55 | return *parent_rate; | |
56 | } | |
57 | ||
58 | static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate, | |
59 | unsigned long parent_rate) | |
60 | { | |
61 | struct clk_plldiv *plldiv = to_clk_plldiv(hw); | |
1a748d2b | 62 | |
1bdf0232 | 63 | if ((parent_rate != rate) && (parent_rate / 2 != rate)) |
1a748d2b BB |
64 | return -EINVAL; |
65 | ||
1bdf0232 BB |
66 | regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2, |
67 | parent_rate != rate ? AT91_PMC_PLLADIV2 : 0); | |
1a748d2b BB |
68 | |
69 | return 0; | |
70 | } | |
71 | ||
72 | static const struct clk_ops plldiv_ops = { | |
73 | .recalc_rate = clk_plldiv_recalc_rate, | |
74 | .round_rate = clk_plldiv_round_rate, | |
75 | .set_rate = clk_plldiv_set_rate, | |
76 | }; | |
77 | ||
78 | static struct clk * __init | |
1bdf0232 | 79 | at91_clk_register_plldiv(struct regmap *regmap, const char *name, |
1a748d2b BB |
80 | const char *parent_name) |
81 | { | |
82 | struct clk_plldiv *plldiv; | |
83 | struct clk *clk = NULL; | |
84 | struct clk_init_data init; | |
85 | ||
86 | plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL); | |
87 | if (!plldiv) | |
88 | return ERR_PTR(-ENOMEM); | |
89 | ||
90 | init.name = name; | |
91 | init.ops = &plldiv_ops; | |
92 | init.parent_names = parent_name ? &parent_name : NULL; | |
93 | init.num_parents = parent_name ? 1 : 0; | |
94 | init.flags = CLK_SET_RATE_GATE; | |
95 | ||
96 | plldiv->hw.init = &init; | |
1bdf0232 | 97 | plldiv->regmap = regmap; |
1a748d2b BB |
98 | |
99 | clk = clk_register(NULL, &plldiv->hw); | |
100 | ||
101 | if (IS_ERR(clk)) | |
102 | kfree(plldiv); | |
103 | ||
104 | return clk; | |
105 | } | |
106 | ||
107 | static void __init | |
1bdf0232 | 108 | of_at91sam9x5_clk_plldiv_setup(struct device_node *np) |
1a748d2b BB |
109 | { |
110 | struct clk *clk; | |
111 | const char *parent_name; | |
112 | const char *name = np->name; | |
1bdf0232 | 113 | struct regmap *regmap; |
1a748d2b BB |
114 | |
115 | parent_name = of_clk_get_parent_name(np, 0); | |
116 | ||
117 | of_property_read_string(np, "clock-output-names", &name); | |
118 | ||
1bdf0232 BB |
119 | regmap = syscon_node_to_regmap(of_get_parent(np)); |
120 | if (IS_ERR(regmap)) | |
121 | return; | |
1a748d2b | 122 | |
1bdf0232 | 123 | clk = at91_clk_register_plldiv(regmap, name, parent_name); |
1a748d2b BB |
124 | if (IS_ERR(clk)) |
125 | return; | |
126 | ||
127 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | |
128 | return; | |
129 | } | |
1bdf0232 BB |
130 | CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv", |
131 | of_at91sam9x5_clk_plldiv_setup); |