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9d9f78ed MT |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> | |
4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Simple multiplexer clock implementation | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/clk-provider.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/err.h> | |
19 | ||
20 | /* | |
21 | * DOC: basic adjustable multiplexer clock that cannot gate | |
22 | * | |
23 | * Traits of this clock: | |
24 | * prepare - clk_prepare only ensures that parents are prepared | |
25 | * enable - clk_enable only ensures that parents are enabled | |
26 | * rate - rate is only affected by parent switching. No clk_set_rate support | |
27 | * parent - parent is adjustable through clk_set_parent | |
28 | */ | |
29 | ||
30 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) | |
31 | ||
32 | static u8 clk_mux_get_parent(struct clk_hw *hw) | |
33 | { | |
34 | struct clk_mux *mux = to_clk_mux(hw); | |
35 | u32 val; | |
36 | ||
37 | /* | |
38 | * FIXME need a mux-specific flag to determine if val is bitwise or numeric | |
39 | * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 | |
40 | * to 0x7 (index starts at one) | |
41 | * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so | |
42 | * val = 0x4 really means "bit 2, index starts at bit 0" | |
43 | */ | |
44 | val = readl(mux->reg) >> mux->shift; | |
45 | val &= (1 << mux->width) - 1; | |
46 | ||
47 | if (val && (mux->flags & CLK_MUX_INDEX_BIT)) | |
48 | val = ffs(val) - 1; | |
49 | ||
50 | if (val && (mux->flags & CLK_MUX_INDEX_ONE)) | |
51 | val--; | |
52 | ||
53 | if (val >= __clk_get_num_parents(hw->clk)) | |
54 | return -EINVAL; | |
55 | ||
56 | return val; | |
57 | } | |
9d9f78ed MT |
58 | |
59 | static int clk_mux_set_parent(struct clk_hw *hw, u8 index) | |
60 | { | |
61 | struct clk_mux *mux = to_clk_mux(hw); | |
62 | u32 val; | |
63 | unsigned long flags = 0; | |
64 | ||
65 | if (mux->flags & CLK_MUX_INDEX_BIT) | |
66 | index = (1 << ffs(index)); | |
67 | ||
68 | if (mux->flags & CLK_MUX_INDEX_ONE) | |
69 | index++; | |
70 | ||
71 | if (mux->lock) | |
72 | spin_lock_irqsave(mux->lock, flags); | |
73 | ||
74 | val = readl(mux->reg); | |
75 | val &= ~(((1 << mux->width) - 1) << mux->shift); | |
76 | val |= index << mux->shift; | |
77 | writel(val, mux->reg); | |
78 | ||
79 | if (mux->lock) | |
80 | spin_unlock_irqrestore(mux->lock, flags); | |
81 | ||
82 | return 0; | |
83 | } | |
9d9f78ed | 84 | |
822c250e | 85 | const struct clk_ops clk_mux_ops = { |
9d9f78ed MT |
86 | .get_parent = clk_mux_get_parent, |
87 | .set_parent = clk_mux_set_parent, | |
88 | }; | |
89 | EXPORT_SYMBOL_GPL(clk_mux_ops); | |
90 | ||
91 | struct clk *clk_register_mux(struct device *dev, const char *name, | |
d305fb78 | 92 | const char **parent_names, u8 num_parents, unsigned long flags, |
9d9f78ed MT |
93 | void __iomem *reg, u8 shift, u8 width, |
94 | u8 clk_mux_flags, spinlock_t *lock) | |
95 | { | |
96 | struct clk_mux *mux; | |
27d54591 | 97 | struct clk *clk; |
0197b3ea | 98 | struct clk_init_data init; |
9d9f78ed | 99 | |
27d54591 | 100 | /* allocate the mux */ |
10363b58 | 101 | mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); |
9d9f78ed MT |
102 | if (!mux) { |
103 | pr_err("%s: could not allocate mux clk\n", __func__); | |
104 | return ERR_PTR(-ENOMEM); | |
105 | } | |
106 | ||
0197b3ea SK |
107 | init.name = name; |
108 | init.ops = &clk_mux_ops; | |
f7d8caad | 109 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
110 | init.parent_names = parent_names; |
111 | init.num_parents = num_parents; | |
112 | ||
9d9f78ed MT |
113 | /* struct clk_mux assignments */ |
114 | mux->reg = reg; | |
115 | mux->shift = shift; | |
116 | mux->width = width; | |
117 | mux->flags = clk_mux_flags; | |
118 | mux->lock = lock; | |
31df9db9 | 119 | mux->hw.init = &init; |
9d9f78ed | 120 | |
0197b3ea | 121 | clk = clk_register(dev, &mux->hw); |
27d54591 MT |
122 | |
123 | if (IS_ERR(clk)) | |
124 | kfree(mux); | |
125 | ||
126 | return clk; | |
9d9f78ed | 127 | } |