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9d9f78ed MT |
1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org> | |
4 | * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Simple multiplexer clock implementation | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/clk-provider.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/err.h> | |
19 | ||
20 | /* | |
21 | * DOC: basic adjustable multiplexer clock that cannot gate | |
22 | * | |
23 | * Traits of this clock: | |
24 | * prepare - clk_prepare only ensures that parents are prepared | |
25 | * enable - clk_enable only ensures that parents are enabled | |
26 | * rate - rate is only affected by parent switching. No clk_set_rate support | |
27 | * parent - parent is adjustable through clk_set_parent | |
28 | */ | |
29 | ||
30 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) | |
31 | ||
32 | static u8 clk_mux_get_parent(struct clk_hw *hw) | |
33 | { | |
34 | struct clk_mux *mux = to_clk_mux(hw); | |
ce4f3313 | 35 | int num_parents = __clk_get_num_parents(hw->clk); |
9d9f78ed MT |
36 | u32 val; |
37 | ||
38 | /* | |
39 | * FIXME need a mux-specific flag to determine if val is bitwise or numeric | |
40 | * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1 | |
41 | * to 0x7 (index starts at one) | |
42 | * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so | |
43 | * val = 0x4 really means "bit 2, index starts at bit 0" | |
44 | */ | |
45 | val = readl(mux->reg) >> mux->shift; | |
ce4f3313 PDS |
46 | val &= mux->mask; |
47 | ||
48 | if (mux->table) { | |
49 | int i; | |
50 | ||
51 | for (i = 0; i < num_parents; i++) | |
52 | if (mux->table[i] == val) | |
53 | return i; | |
54 | return -EINVAL; | |
55 | } | |
9d9f78ed MT |
56 | |
57 | if (val && (mux->flags & CLK_MUX_INDEX_BIT)) | |
58 | val = ffs(val) - 1; | |
59 | ||
60 | if (val && (mux->flags & CLK_MUX_INDEX_ONE)) | |
61 | val--; | |
62 | ||
ce4f3313 | 63 | if (val >= num_parents) |
9d9f78ed MT |
64 | return -EINVAL; |
65 | ||
66 | return val; | |
67 | } | |
9d9f78ed MT |
68 | |
69 | static int clk_mux_set_parent(struct clk_hw *hw, u8 index) | |
70 | { | |
71 | struct clk_mux *mux = to_clk_mux(hw); | |
72 | u32 val; | |
73 | unsigned long flags = 0; | |
74 | ||
ce4f3313 PDS |
75 | if (mux->table) |
76 | index = mux->table[index]; | |
9d9f78ed | 77 | |
ce4f3313 PDS |
78 | else { |
79 | if (mux->flags & CLK_MUX_INDEX_BIT) | |
80 | index = (1 << ffs(index)); | |
81 | ||
82 | if (mux->flags & CLK_MUX_INDEX_ONE) | |
83 | index++; | |
84 | } | |
9d9f78ed MT |
85 | |
86 | if (mux->lock) | |
87 | spin_lock_irqsave(mux->lock, flags); | |
88 | ||
ba492e90 HZ |
89 | if (mux->flags & CLK_MUX_HIWORD_MASK) { |
90 | val = mux->mask << (mux->shift + 16); | |
91 | } else { | |
92 | val = readl(mux->reg); | |
93 | val &= ~(mux->mask << mux->shift); | |
94 | } | |
9d9f78ed MT |
95 | val |= index << mux->shift; |
96 | writel(val, mux->reg); | |
97 | ||
98 | if (mux->lock) | |
99 | spin_unlock_irqrestore(mux->lock, flags); | |
100 | ||
101 | return 0; | |
102 | } | |
9d9f78ed | 103 | |
822c250e | 104 | const struct clk_ops clk_mux_ops = { |
9d9f78ed MT |
105 | .get_parent = clk_mux_get_parent, |
106 | .set_parent = clk_mux_set_parent, | |
107 | }; | |
108 | EXPORT_SYMBOL_GPL(clk_mux_ops); | |
109 | ||
ce4f3313 | 110 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
d305fb78 | 111 | const char **parent_names, u8 num_parents, unsigned long flags, |
ce4f3313 PDS |
112 | void __iomem *reg, u8 shift, u32 mask, |
113 | u8 clk_mux_flags, u32 *table, spinlock_t *lock) | |
9d9f78ed MT |
114 | { |
115 | struct clk_mux *mux; | |
27d54591 | 116 | struct clk *clk; |
0197b3ea | 117 | struct clk_init_data init; |
ba492e90 HZ |
118 | u8 width = 0; |
119 | ||
120 | if (clk_mux_flags & CLK_MUX_HIWORD_MASK) { | |
121 | width = fls(mask) - ffs(mask) + 1; | |
122 | if (width + shift > 16) { | |
123 | pr_err("mux value exceeds LOWORD field\n"); | |
124 | return ERR_PTR(-EINVAL); | |
125 | } | |
126 | } | |
9d9f78ed | 127 | |
27d54591 | 128 | /* allocate the mux */ |
10363b58 | 129 | mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); |
9d9f78ed MT |
130 | if (!mux) { |
131 | pr_err("%s: could not allocate mux clk\n", __func__); | |
132 | return ERR_PTR(-ENOMEM); | |
133 | } | |
134 | ||
0197b3ea SK |
135 | init.name = name; |
136 | init.ops = &clk_mux_ops; | |
f7d8caad | 137 | init.flags = flags | CLK_IS_BASIC; |
0197b3ea SK |
138 | init.parent_names = parent_names; |
139 | init.num_parents = num_parents; | |
140 | ||
9d9f78ed MT |
141 | /* struct clk_mux assignments */ |
142 | mux->reg = reg; | |
143 | mux->shift = shift; | |
ce4f3313 | 144 | mux->mask = mask; |
9d9f78ed MT |
145 | mux->flags = clk_mux_flags; |
146 | mux->lock = lock; | |
ce4f3313 | 147 | mux->table = table; |
31df9db9 | 148 | mux->hw.init = &init; |
9d9f78ed | 149 | |
0197b3ea | 150 | clk = clk_register(dev, &mux->hw); |
27d54591 MT |
151 | |
152 | if (IS_ERR(clk)) | |
153 | kfree(mux); | |
154 | ||
155 | return clk; | |
9d9f78ed | 156 | } |
ce4f3313 PDS |
157 | |
158 | struct clk *clk_register_mux(struct device *dev, const char *name, | |
159 | const char **parent_names, u8 num_parents, unsigned long flags, | |
160 | void __iomem *reg, u8 shift, u8 width, | |
161 | u8 clk_mux_flags, spinlock_t *lock) | |
162 | { | |
163 | u32 mask = BIT(width) - 1; | |
164 | ||
165 | return clk_register_mux_table(dev, name, parent_names, num_parents, | |
166 | flags, reg, shift, mask, clk_mux_flags, | |
167 | NULL, lock); | |
168 | } |