[deliverable/linux.git] / drivers / clk / clk-nomadik.c

/*
 * Nomadik clock implementation
 * Copyright (C) 2013 ST-Ericsson AB
 * License terms: GNU General Public License (GPL) version 2
 * Author: Linus Walleij <linus.walleij@linaro.org>
 */

#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/reboot.h>

/*
 * The Nomadik clock tree is described in the STN8815A12 DB V4.2
 * reference manual for the chip, page 94 ff.
 * Clock IDs are in the STn8815 Reference Manual table 3, page 27.
 */

#define SRC_CR			0x00U
#define SRC_CR_T0_ENSEL		BIT(15)
#define SRC_CR_T1_ENSEL		BIT(17)
#define SRC_CR_T2_ENSEL		BIT(19)
#define SRC_CR_T3_ENSEL		BIT(21)
#define SRC_CR_T4_ENSEL		BIT(23)
#define SRC_CR_T5_ENSEL		BIT(25)
#define SRC_CR_T6_ENSEL		BIT(27)
#define SRC_CR_T7_ENSEL		BIT(29)
#define SRC_XTALCR		0x0CU
#define SRC_XTALCR_XTALTIMEN	BIT(20)
#define SRC_XTALCR_SXTALDIS	BIT(19)
#define SRC_XTALCR_MXTALSTAT	BIT(2)
#define SRC_XTALCR_MXTALEN	BIT(1)
#define SRC_XTALCR_MXTALOVER	BIT(0)
#define SRC_PLLCR		0x10U
#define SRC_PLLCR_PLLTIMEN	BIT(29)
#define SRC_PLLCR_PLL2EN	BIT(28)
#define SRC_PLLCR_PLL1STAT	BIT(2)
#define SRC_PLLCR_PLL1EN	BIT(1)
#define SRC_PLLCR_PLL1OVER	BIT(0)
#define SRC_PLLFR		0x14U
#define SRC_PCKEN0		0x24U
#define SRC_PCKDIS0		0x28U
#define SRC_PCKENSR0		0x2CU
#define SRC_PCKSR0		0x30U
#define SRC_PCKEN1		0x34U
#define SRC_PCKDIS1		0x38U
#define SRC_PCKENSR1		0x3CU
#define SRC_PCKSR1		0x40U

/* Lock protecting the SRC_CR register */
static DEFINE_SPINLOCK(src_lock);
/* Base address of the SRC */
static void __iomem *src_base;

/**
 * struct clk_pll1 - Nomadik PLL1 clock
 * @hw: corresponding clock hardware entry
 * @id: PLL instance: 1 or 2
 */
struct clk_pll {
	struct clk_hw hw;
	int id;
};

/**
 * struct clk_src - Nomadik src clock
 * @hw: corresponding clock hardware entry
 * @id: the clock ID
 * @group1: true if the clock is in group1, else it is in group0
 * @clkbit: bit 0...31 corresponding to the clock in each clock register
 */
struct clk_src {
	struct clk_hw hw;
	int id;
	bool group1;
	u32 clkbit;
};

#define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
#define to_src(_hw) container_of(_hw, struct clk_src, hw)

static int pll_clk_enable(struct clk_hw *hw)
{
	struct clk_pll *pll = to_pll(hw);
	u32 val;

	spin_lock(&src_lock);
	val = readl(src_base + SRC_PLLCR);
	if (pll->id == 1) {
		if (val & SRC_PLLCR_PLL1OVER) {
			val |= SRC_PLLCR_PLL1EN;
			writel(val, src_base + SRC_PLLCR);
		}
	} else if (pll->id == 2) {
		val |= SRC_PLLCR_PLL2EN;
		writel(val, src_base + SRC_PLLCR);
	}
	spin_unlock(&src_lock);
	return 0;
}

static void pll_clk_disable(struct clk_hw *hw)
{
	struct clk_pll *pll = to_pll(hw);
	u32 val;

	spin_lock(&src_lock);
	val = readl(src_base + SRC_PLLCR);
	if (pll->id == 1) {
		if (val & SRC_PLLCR_PLL1OVER) {
			val &= ~SRC_PLLCR_PLL1EN;
			writel(val, src_base + SRC_PLLCR);
		}
	} else if (pll->id == 2) {
		val &= ~SRC_PLLCR_PLL2EN;
		writel(val, src_base + SRC_PLLCR);
	}
	spin_unlock(&src_lock);
}

static int pll_clk_is_enabled(struct clk_hw *hw)
{
	struct clk_pll *pll = to_pll(hw);
	u32 val;

	val = readl(src_base + SRC_PLLCR);
	if (pll->id == 1) {
		if (val & SRC_PLLCR_PLL1OVER)
			return !!(val & SRC_PLLCR_PLL1EN);
	} else if (pll->id == 2) {
		return !!(val & SRC_PLLCR_PLL2EN);
	}
	return 1;
}

static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
					  unsigned long parent_rate)
{
	struct clk_pll *pll = to_pll(hw);
	u32 val;

	val = readl(src_base + SRC_PLLFR);

	if (pll->id == 1) {
		u8 mul;
		u8 div;

		mul = (val >> 8) & 0x3FU;
		mul += 2;
		div = val & 0x07U;
		return (parent_rate * mul) >> div;
	}

	if (pll->id == 2) {
		u8 mul;

		mul = (val >> 24) & 0x3FU;
		mul += 2;
		return (parent_rate * mul);
	}

	/* Unknown PLL */
	return 0;
}


static const struct clk_ops pll_clk_ops = {
	.enable = pll_clk_enable,
	.disable = pll_clk_disable,
	.is_enabled = pll_clk_is_enabled,
	.recalc_rate = pll_clk_recalc_rate,
};

static struct clk * __init
pll_clk_register(struct device *dev, const char *name,
		 const char *parent_name, u32 id)
{
	struct clk *clk;
	struct clk_pll *pll;
	struct clk_init_data init;

	if (id != 1 && id != 2) {
		pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
		return ERR_PTR(-EINVAL);
	}

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (!pll) {
		pr_err("%s: could not allocate PLL clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	init.ops = &pll_clk_ops;
	init.parent_names = (parent_name ? &parent_name : NULL);
	init.num_parents = (parent_name ? 1 : 0);
	pll->hw.init = &init;
	pll->id = id;

	pr_debug("register PLL1 clock \"%s\"\n", name);

	clk = clk_register(dev, &pll->hw);
	if (IS_ERR(clk))
		kfree(pll);

	return clk;
}

/*
 * The Nomadik SRC clocks are gated, but not in the sense that
 * you read-modify-write a register. Instead there are separate
 * clock enable and clock disable registers. Writing a '1' bit in
 * the enable register for a certain clock ungates that clock without
 * affecting the other clocks. The disable register works the opposite
 * way.
 */

static int src_clk_enable(struct clk_hw *hw)
{
	struct clk_src *sclk = to_src(hw);
	u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;

	writel(sclk->clkbit, src_base + enreg);
	/* spin until enabled */
	while (!(readl(src_base + sreg) & sclk->clkbit))
		cpu_relax();
	return 0;
}

static void src_clk_disable(struct clk_hw *hw)
{
	struct clk_src *sclk = to_src(hw);
	u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;

	writel(sclk->clkbit, src_base + disreg);
	/* spin until disabled */
	while (readl(src_base + sreg) & sclk->clkbit)
		cpu_relax();
}

static int src_clk_is_enabled(struct clk_hw *hw)
{
	struct clk_src *sclk = to_src(hw);
	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
	u32 val = readl(src_base + sreg);

	return !!(val & sclk->clkbit);
}

static unsigned long
src_clk_recalc_rate(struct clk_hw *hw,
		    unsigned long parent_rate)
{
	return parent_rate;
}

static const struct clk_ops src_clk_ops = {
	.enable = src_clk_enable,
	.disable = src_clk_disable,
	.is_enabled = src_clk_is_enabled,
	.recalc_rate = src_clk_recalc_rate,
};

static struct clk * __init
src_clk_register(struct device *dev, const char *name,
		 const char *parent_name, u8 id)
{
	struct clk *clk;
	struct clk_src *sclk;
	struct clk_init_data init;

	sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
	if (!sclk) {
		pr_err("could not allocate SRC clock %s\n",
			name);
		return ERR_PTR(-ENOMEM);
	}
	init.name = name;
	init.ops = &src_clk_ops;
	/* Do not force-disable the static SDRAM controller */
	if (id == 2)
		init.flags = CLK_IGNORE_UNUSED;
	else
		init.flags = 0;
	init.parent_names = (parent_name ? &parent_name : NULL);
	init.num_parents = (parent_name ? 1 : 0);
	sclk->hw.init = &init;
	sclk->id = id;
	sclk->group1 = (id > 31);
	sclk->clkbit = BIT(id & 0x1f);

	pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
		 name, id, sclk->group1, sclk->clkbit);

	clk = clk_register(dev, &sclk->hw);
	if (IS_ERR(clk))
		kfree(sclk);

	return clk;
}

#ifdef CONFIG_DEBUG_FS

static u32 src_pcksr0_boot;
static u32 src_pcksr1_boot;

static const char * const src_clk_names[] = {
	"HCLKDMA0  ",
	"HCLKSMC   ",
	"HCLKSDRAM ",
	"HCLKDMA1  ",
	"HCLKCLCD  ",
	"PCLKIRDA  ",
	"PCLKSSP   ",
	"PCLKUART0 ",
	"PCLKSDI   ",
	"PCLKI2C0  ",
	"PCLKI2C1  ",
	"PCLKUART1 ",
	"PCLMSP0   ",
	"HCLKUSB   ",
	"HCLKDIF   ",
	"HCLKSAA   ",
	"HCLKSVA   ",
	"PCLKHSI   ",
	"PCLKXTI   ",
	"PCLKUART2 ",
	"PCLKMSP1  ",
	"PCLKMSP2  ",
	"PCLKOWM   ",
	"HCLKHPI   ",
	"PCLKSKE   ",
	"PCLKHSEM  ",
	"HCLK3D    ",
	"HCLKHASH  ",
	"HCLKCRYP  ",
	"PCLKMSHC  ",
	"HCLKUSBM  ",
	"HCLKRNG   ",
	"RESERVED  ",
	"RESERVED  ",
	"RESERVED  ",
	"RESERVED  ",
	"CLDCLK    ",
	"IRDACLK   ",
	"SSPICLK   ",
	"UART0CLK  ",
	"SDICLK    ",
	"I2C0CLK   ",
	"I2C1CLK   ",
	"UART1CLK  ",
	"MSPCLK0   ",
	"USBCLK    ",
	"DIFCLK    ",
	"IPI2CCLK  ",
	"IPBMCCLK  ",
	"HSICLKRX  ",
	"HSICLKTX  ",
	"UART2CLK  ",
	"MSPCLK1   ",
	"MSPCLK2   ",
	"OWMCLK    ",
	"RESERVED  ",
	"SKECLK    ",
	"RESERVED  ",
	"3DCLK     ",
	"PCLKMSP3  ",
	"MSPCLK3   ",
	"MSHCCLK   ",
	"USBMCLK   ",
	"RNGCCLK   ",
};

static int nomadik_src_clk_show(struct seq_file *s, void *what)
{
	int i;
	u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
	u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
	u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
	u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);

	seq_printf(s, "Clock:      Boot:   Now:    Request: ASKED:\n");
	for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
		u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
		u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
		u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
		u32 mask = BIT(i & 0x1f);

		seq_printf(s, "%s  %s     %s     %s\n",
			   src_clk_names[i],
			   (pcksrb & mask) ? "on " : "off",
			   (pcksr & mask) ? "on " : "off",
			   (pckreq & mask) ? "on " : "off");
	}
	return 0;
}

static int nomadik_src_clk_open(struct inode *inode, struct file *file)
{
	return single_open(file, nomadik_src_clk_show, NULL);
}

static const struct file_operations nomadik_src_clk_debugfs_ops = {
	.open           = nomadik_src_clk_open,
	.read           = seq_read,
        .llseek         = seq_lseek,
	.release        = single_release,
};

static int __init nomadik_src_clk_init_debugfs(void)
{
	src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
	src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
	debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
			    NULL, NULL, &nomadik_src_clk_debugfs_ops);
	return 0;
}

module_init(nomadik_src_clk_init_debugfs);

#endif

static void __init of_nomadik_pll_setup(struct device_node *np)
{
	struct clk *clk = ERR_PTR(-EINVAL);
	const char *clk_name = np->name;
	const char *parent_name;
	u32 pll_id;

	if (of_property_read_u32(np, "pll-id", &pll_id)) {
		pr_err("%s: PLL \"%s\" missing pll-id property\n",
			__func__, clk_name);
		return;
	}
	parent_name = of_clk_get_parent_name(np, 0);
	clk = pll_clk_register(NULL, clk_name, parent_name, pll_id);
	if (!IS_ERR(clk))
		of_clk_add_provider(np, of_clk_src_simple_get, clk);
}

static void __init of_nomadik_hclk_setup(struct device_node *np)
{
	struct clk *clk = ERR_PTR(-EINVAL);
	const char *clk_name = np->name;
	const char *parent_name;

	parent_name = of_clk_get_parent_name(np, 0);
	/*
	 * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
	 */
	clk = clk_register_divider(NULL, clk_name, parent_name,
			   0, src_base + SRC_CR,
			   13, 2,
			   CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
			   &src_lock);
	if (!IS_ERR(clk))
		of_clk_add_provider(np, of_clk_src_simple_get, clk);
}

static void __init of_nomadik_src_clk_setup(struct device_node *np)
{
	struct clk *clk = ERR_PTR(-EINVAL);
	const char *clk_name = np->name;
	const char *parent_name;
	u32 clk_id;

	if (of_property_read_u32(np, "clock-id", &clk_id)) {
		pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
			__func__, clk_name);
		return;
	}
	parent_name = of_clk_get_parent_name(np, 0);
	clk = src_clk_register(NULL, clk_name, parent_name, clk_id);
	if (!IS_ERR(clk))
		of_clk_add_provider(np, of_clk_src_simple_get, clk);
}

static const struct of_device_id nomadik_src_match[] __initconst = {
	{ .compatible = "stericsson,nomadik-src" },
	{ /* sentinel */ }
};

static const struct of_device_id nomadik_src_clk_match[] __initconst = {
	{
		.compatible = "fixed-clock",
		.data = of_fixed_clk_setup,
	},
	{
		.compatible = "fixed-factor-clock",
		.data = of_fixed_factor_clk_setup,
	},
	{
		.compatible = "st,nomadik-pll-clock",
		.data = of_nomadik_pll_setup,
	},
	{
		.compatible = "st,nomadik-hclk-clock",
		.data = of_nomadik_hclk_setup,
	},
	{
		.compatible = "st,nomadik-src-clock",
		.data = of_nomadik_src_clk_setup,
	},
	{ /* sentinel */ }
};

static int nomadik_clk_reboot_handler(struct notifier_block *this,
				unsigned long code,
				void *unused)
{
	u32 val;

	/* The main chrystal need to be enabled for reboot to work */
	val = readl(src_base + SRC_XTALCR);
	val &= ~SRC_XTALCR_MXTALOVER;
	val |= SRC_XTALCR_MXTALEN;
	pr_crit("force-enabling MXTALO\n");
	writel(val, src_base + SRC_XTALCR);
	return NOTIFY_OK;
}

static struct notifier_block nomadik_clk_reboot_notifier = {
	.notifier_call = nomadik_clk_reboot_handler,
};

void __init nomadik_clk_init(void)
{
	struct device_node *np;
	u32 val;

	np = of_find_matching_node(NULL, nomadik_src_match);
	if (!np) {
		pr_crit("no matching node for SRC, aborting clock init\n");
		return;
	}
	src_base = of_iomap(np, 0);
	if (!src_base) {
		pr_err("%s: must have src parent node with REGS (%s)\n",
		       __func__, np->name);
		return;
	}

	/* Set all timers to use the 2.4 MHz TIMCLK */
	val = readl(src_base + SRC_CR);
	val |= SRC_CR_T0_ENSEL;
	val |= SRC_CR_T1_ENSEL;
	val |= SRC_CR_T2_ENSEL;
	val |= SRC_CR_T3_ENSEL;
	val |= SRC_CR_T4_ENSEL;
	val |= SRC_CR_T5_ENSEL;
	val |= SRC_CR_T6_ENSEL;
	val |= SRC_CR_T7_ENSEL;
	writel(val, src_base + SRC_CR);

	val = readl(src_base + SRC_XTALCR);
	pr_info("SXTALO is %s\n",
		(val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
	pr_info("MXTAL is %s\n",
		(val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
	if (of_property_read_bool(np, "disable-sxtalo")) {
		/* The machine uses an external oscillator circuit */
		val |= SRC_XTALCR_SXTALDIS;
		pr_info("disabling SXTALO\n");
	}
	if (of_property_read_bool(np, "disable-mxtalo")) {
		/* Disable this too: also run by external oscillator */
		val |= SRC_XTALCR_MXTALOVER;
		val &= ~SRC_XTALCR_MXTALEN;
		pr_info("disabling MXTALO\n");
	}
	writel(val, src_base + SRC_XTALCR);
	register_reboot_notifier(&nomadik_clk_reboot_notifier);

	of_clk_init(nomadik_src_clk_match);
}
Commit	Line	Data
ef6eb322 LW	1	/*
	2	* Nomadik clock implementation
	3	* Copyright (C) 2013 ST-Ericsson AB
	4	* License terms: GNU General Public License (GPL) version 2
	5	* Author: Linus Walleij <linus.walleij@linaro.org>
	6	*/
	7
	8	#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt
	9
	10	#include <linux/bitops.h>
4a31bd28 LW	11	#include <linux/clk.h>
	12	#include <linux/clkdev.h>
	13	#include <linux/err.h>
	14	#include <linux/io.h>
	15	#include <linux/clk-provider.h>
6e2b07a1	16	#include <linux/of.h>
ef6eb322 LW	17	#include <linux/of_address.h>
	18	#include <linux/debugfs.h>
	19	#include <linux/seq_file.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/reboot.h>
4a31bd28 LW	22
	23	/*
	24	* The Nomadik clock tree is described in the STN8815A12 DB V4.2
	25	* reference manual for the chip, page 94 ff.
ef6eb322 LW	26	* Clock IDs are in the STn8815 Reference Manual table 3, page 27.
	27	*/
	28
	29	#define SRC_CR 0x00U
b9b5ab11 LW	30	#define SRC_CR_T0_ENSEL BIT(15)
	31	#define SRC_CR_T1_ENSEL BIT(17)
	32	#define SRC_CR_T2_ENSEL BIT(19)
	33	#define SRC_CR_T3_ENSEL BIT(21)
	34	#define SRC_CR_T4_ENSEL BIT(23)
	35	#define SRC_CR_T5_ENSEL BIT(25)
	36	#define SRC_CR_T6_ENSEL BIT(27)
	37	#define SRC_CR_T7_ENSEL BIT(29)
ef6eb322 LW	38	#define SRC_XTALCR 0x0CU
	39	#define SRC_XTALCR_XTALTIMEN BIT(20)
	40	#define SRC_XTALCR_SXTALDIS BIT(19)
	41	#define SRC_XTALCR_MXTALSTAT BIT(2)
	42	#define SRC_XTALCR_MXTALEN BIT(1)
	43	#define SRC_XTALCR_MXTALOVER BIT(0)
	44	#define SRC_PLLCR 0x10U
	45	#define SRC_PLLCR_PLLTIMEN BIT(29)
	46	#define SRC_PLLCR_PLL2EN BIT(28)
	47	#define SRC_PLLCR_PLL1STAT BIT(2)
	48	#define SRC_PLLCR_PLL1EN BIT(1)
	49	#define SRC_PLLCR_PLL1OVER BIT(0)
	50	#define SRC_PLLFR 0x14U
	51	#define SRC_PCKEN0 0x24U
	52	#define SRC_PCKDIS0 0x28U
	53	#define SRC_PCKENSR0 0x2CU
	54	#define SRC_PCKSR0 0x30U
	55	#define SRC_PCKEN1 0x34U
	56	#define SRC_PCKDIS1 0x38U
	57	#define SRC_PCKENSR1 0x3CU
	58	#define SRC_PCKSR1 0x40U
	59
	60	/* Lock protecting the SRC_CR register */
	61	static DEFINE_SPINLOCK(src_lock);
	62	/* Base address of the SRC */
	63	static void __iomem *src_base;
	64
	65	/**
	66	* struct clk_pll1 - Nomadik PLL1 clock
	67	* @hw: corresponding clock hardware entry
	68	* @id: PLL instance: 1 or 2
	69	*/
	70	struct clk_pll {
	71	struct clk_hw hw;
	72	int id;
	73	};
	74
	75	/**
	76	* struct clk_src - Nomadik src clock
	77	* @hw: corresponding clock hardware entry
	78	* @id: the clock ID
	79	* @group1: true if the clock is in group1, else it is in group0
	80	* @clkbit: bit 0...31 corresponding to the clock in each clock register
	81	*/
	82	struct clk_src {
	83	struct clk_hw hw;
	84	int id;
	85	bool group1;
	86	u32 clkbit;
	87	};
	88
	89	#define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
	90	#define to_src(_hw) container_of(_hw, struct clk_src, hw)
	91
	92	static int pll_clk_enable(struct clk_hw *hw)
	93	{
	94	struct clk_pll *pll = to_pll(hw);
	95	u32 val;
	96
	97	spin_lock(&src_lock);
	98	val = readl(src_base + SRC_PLLCR);
	99	if (pll->id == 1) {
	100	if (val & SRC_PLLCR_PLL1OVER) {
	101	val \|= SRC_PLLCR_PLL1EN;
102	writel(val, src_base + SRC_PLLCR);
103	}
104	} else if (pll->id == 2) {
105	val \|= SRC_PLLCR_PLL2EN;
106	writel(val, src_base + SRC_PLLCR);
107	}
108	spin_unlock(&src_lock);
109	return 0;
110	}
111
112	static void pll_clk_disable(struct clk_hw *hw)
113	{
114	struct clk_pll *pll = to_pll(hw);
115	u32 val;
116
117	spin_lock(&src_lock);
118	val = readl(src_base + SRC_PLLCR);
119	if (pll->id == 1) {
120	if (val & SRC_PLLCR_PLL1OVER) {
121	val &= ~SRC_PLLCR_PLL1EN;
122	writel(val, src_base + SRC_PLLCR);
123	}
124	} else if (pll->id == 2) {
125	val &= ~SRC_PLLCR_PLL2EN;
126	writel(val, src_base + SRC_PLLCR);
127	}
128	spin_unlock(&src_lock);
129	}
130
131	static int pll_clk_is_enabled(struct clk_hw *hw)
132	{
133	struct clk_pll *pll = to_pll(hw);
134	u32 val;
135
136	val = readl(src_base + SRC_PLLCR);
137	if (pll->id == 1) {
138	if (val & SRC_PLLCR_PLL1OVER)
139	return !!(val & SRC_PLLCR_PLL1EN);
140	} else if (pll->id == 2) {
141	return !!(val & SRC_PLLCR_PLL2EN);
142	}
143	return 1;
144	}
145
146	static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
147	unsigned long parent_rate)
148	{
149	struct clk_pll *pll = to_pll(hw);
150	u32 val;
151
152	val = readl(src_base + SRC_PLLFR);
153
154	if (pll->id == 1) {
155	u8 mul;
156	u8 div;
157
158	mul = (val >> 8) & 0x3FU;
159	mul += 2;
160	div = val & 0x07U;
161	return (parent_rate * mul) >> div;
162	}
163
164	if (pll->id == 2) {
165	u8 mul;
166
167	mul = (val >> 24) & 0x3FU;
168	mul += 2;
169	return (parent_rate * mul);
170	}
171
172	/* Unknown PLL */
173	return 0;
174	}
175
176
177	static const struct clk_ops pll_clk_ops = {
178	.enable = pll_clk_enable,
179	.disable = pll_clk_disable,
180	.is_enabled = pll_clk_is_enabled,
181	.recalc_rate = pll_clk_recalc_rate,
182	};
183
184	static struct clk * __init
185	pll_clk_register(struct device dev, const char name,
186	const char *parent_name, u32 id)
187	{
188	struct clk *clk;
189	struct clk_pll *pll;
190	struct clk_init_data init;
191
192	if (id != 1 && id != 2) {
193	pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
194	return ERR_PTR(-EINVAL);
195	}
196
197	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
198	if (!pll) {
199	pr_err("%s: could not allocate PLL clk\n", __func__);
200	return ERR_PTR(-ENOMEM);
201	}
202
203	init.name = name;
204	init.ops = &pll_clk_ops;
205	init.parent_names = (parent_name ? &parent_name : NULL);
206	init.num_parents = (parent_name ? 1 : 0);
207	pll->hw.init = &init;
208	pll->id = id;
209
210	pr_debug("register PLL1 clock \"%s\"\n", name);
211
212	clk = clk_register(dev, &pll->hw);
213	if (IS_ERR(clk))
214	kfree(pll);
215
216	return clk;
217	}
218
219	/*
220	* The Nomadik SRC clocks are gated, but not in the sense that
221	* you read-modify-write a register. Instead there are separate
222	* clock enable and clock disable registers. Writing a '1' bit in
223	* the enable register for a certain clock ungates that clock without
224	* affecting the other clocks. The disable register works the opposite
225	* way.
4a31bd28 LW	226	*/
4a31bd28 LW	227
ef6eb322 LW	228	static int src_clk_enable(struct clk_hw *hw)
	229	{
	230	struct clk_src *sclk = to_src(hw);
	231	u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
	232	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
	233
	234	writel(sclk->clkbit, src_base + enreg);
	235	/* spin until enabled */
	236	while (!(readl(src_base + sreg) & sclk->clkbit))
	237	cpu_relax();
	238	return 0;
	239	}
	240
	241	static void src_clk_disable(struct clk_hw *hw)
	242	{
	243	struct clk_src *sclk = to_src(hw);
	244	u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
	245	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
	246
	247	writel(sclk->clkbit, src_base + disreg);
	248	/* spin until disabled */
	249	while (readl(src_base + sreg) & sclk->clkbit)
	250	cpu_relax();
	251	}
	252
	253	static int src_clk_is_enabled(struct clk_hw *hw)
	254	{
	255	struct clk_src *sclk = to_src(hw);
	256	u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
	257	u32 val = readl(src_base + sreg);
	258
	259	return !!(val & sclk->clkbit);
	260	}
	261
	262	static unsigned long
	263	src_clk_recalc_rate(struct clk_hw *hw,
	264	unsigned long parent_rate)
	265	{
	266	return parent_rate;
	267	}
	268
	269	static const struct clk_ops src_clk_ops = {
	270	.enable = src_clk_enable,
	271	.disable = src_clk_disable,
	272	.is_enabled = src_clk_is_enabled,
	273	.recalc_rate = src_clk_recalc_rate,
	274	};
	275
	276	static struct clk * __init
	277	src_clk_register(struct device dev, const char name,
	278	const char *parent_name, u8 id)
	279	{
	280	struct clk *clk;
	281	struct clk_src *sclk;
	282	struct clk_init_data init;
	283
	284	sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
	285	if (!sclk) {
	286	pr_err("could not allocate SRC clock %s\n",
	287	name);
	288	return ERR_PTR(-ENOMEM);
	289	}
	290	init.name = name;
	291	init.ops = &src_clk_ops;
292	/* Do not force-disable the static SDRAM controller */
293	if (id == 2)
294	init.flags = CLK_IGNORE_UNUSED;
295	else
296	init.flags = 0;
297	init.parent_names = (parent_name ? &parent_name : NULL);
298	init.num_parents = (parent_name ? 1 : 0);
299	sclk->hw.init = &init;
300	sclk->id = id;
301	sclk->group1 = (id > 31);
302	sclk->clkbit = BIT(id & 0x1f);
303
304	pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
305	name, id, sclk->group1, sclk->clkbit);
306
307	clk = clk_register(dev, &sclk->hw);
308	if (IS_ERR(clk))
309	kfree(sclk);
310
311	return clk;
312	}
313
314	#ifdef CONFIG_DEBUG_FS
315
316	static u32 src_pcksr0_boot;
317	static u32 src_pcksr1_boot;
318
319	static const char * const src_clk_names[] = {
320	"HCLKDMA0 ",
321	"HCLKSMC ",
322	"HCLKSDRAM ",
323	"HCLKDMA1 ",
324	"HCLKCLCD ",
325	"PCLKIRDA ",
326	"PCLKSSP ",
327	"PCLKUART0 ",
328	"PCLKSDI ",
329	"PCLKI2C0 ",
330	"PCLKI2C1 ",
331	"PCLKUART1 ",
332	"PCLMSP0 ",
333	"HCLKUSB ",
334	"HCLKDIF ",
335	"HCLKSAA ",
336	"HCLKSVA ",
337	"PCLKHSI ",
338	"PCLKXTI ",
339	"PCLKUART2 ",
340	"PCLKMSP1 ",
341	"PCLKMSP2 ",
342	"PCLKOWM ",
343	"HCLKHPI ",
344	"PCLKSKE ",
345	"PCLKHSEM ",
346	"HCLK3D ",
347	"HCLKHASH ",
348	"HCLKCRYP ",
349	"PCLKMSHC ",
350	"HCLKUSBM ",
351	"HCLKRNG ",
352	"RESERVED ",
353	"RESERVED ",
354	"RESERVED ",
355	"RESERVED ",
356	"CLDCLK ",
357	"IRDACLK ",
358	"SSPICLK ",
359	"UART0CLK ",
360	"SDICLK ",
361	"I2C0CLK ",
362	"I2C1CLK ",
363	"UART1CLK ",
364	"MSPCLK0 ",
365	"USBCLK ",
366	"DIFCLK ",
367	"IPI2CCLK ",
368	"IPBMCCLK ",
369	"HSICLKRX ",
370	"HSICLKTX ",
371	"UART2CLK ",
372	"MSPCLK1 ",
373	"MSPCLK2 ",
374	"OWMCLK ",
375	"RESERVED ",
376	"SKECLK ",
377	"RESERVED ",
378	"3DCLK ",
379	"PCLKMSP3 ",
380	"MSPCLK3 ",
381	"MSHCCLK ",
382	"USBMCLK ",
383	"RNGCCLK ",
384	};
385
386	static int nomadik_src_clk_show(struct seq_file s, void what)
387	{
388	int i;
389	u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
390	u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
391	u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
392	u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);
393
394	seq_printf(s, "Clock: Boot: Now: Request: ASKED:\n");
395	for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
396	u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
397	u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
398	u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
399	u32 mask = BIT(i & 0x1f);
400
401	seq_printf(s, "%s %s %s %s\n",
402	src_clk_names[i],
403	(pcksrb & mask) ? "on " : "off",
404	(pcksr & mask) ? "on " : "off",
405	(pckreq & mask) ? "on " : "off");
406	}
407	return 0;
408	}
409
410	static int nomadik_src_clk_open(struct inode inode, struct file file)
411	{
412	return single_open(file, nomadik_src_clk_show, NULL);
413	}
414
415	static const struct file_operations nomadik_src_clk_debugfs_ops = {
416	.open = nomadik_src_clk_open,
417	.read = seq_read,
418	.llseek = seq_lseek,
419	.release = single_release,
420	};
421
422	static int __init nomadik_src_clk_init_debugfs(void)
423	{
424	src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
425	src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
426	debugfs_create_file("nomadik-src-clk", S_IFREG \| S_IRUGO,
427	NULL, NULL, &nomadik_src_clk_debugfs_ops);
428	return 0;
429	}
430
431	module_init(nomadik_src_clk_init_debugfs);
432
433	#endif
434
435	static void __init of_nomadik_pll_setup(struct device_node *np)
436	{
437	struct clk *clk = ERR_PTR(-EINVAL);
438	const char *clk_name = np->name;
439	const char *parent_name;
440	u32 pll_id;
441
442	if (of_property_read_u32(np, "pll-id", &pll_id)) {
443	pr_err("%s: PLL \"%s\" missing pll-id property\n",
444	__func__, clk_name);
445	return;
446	}
447	parent_name = of_clk_get_parent_name(np, 0);
448	clk = pll_clk_register(NULL, clk_name, parent_name, pll_id);
449	if (!IS_ERR(clk))
450	of_clk_add_provider(np, of_clk_src_simple_get, clk);
451	}
452
453	static void __init of_nomadik_hclk_setup(struct device_node *np)
454	{
455	struct clk *clk = ERR_PTR(-EINVAL);
456	const char *clk_name = np->name;
457	const char *parent_name;
458
459	parent_name = of_clk_get_parent_name(np, 0);
460	/*
461	* The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
462	*/
463	clk = clk_register_divider(NULL, clk_name, parent_name,
464	0, src_base + SRC_CR,
465	13, 2,
466	CLK_DIVIDER_ONE_BASED \| CLK_DIVIDER_ALLOW_ZERO,
467	&src_lock);
468	if (!IS_ERR(clk))
469	of_clk_add_provider(np, of_clk_src_simple_get, clk);
470	}
471
472	static void __init of_nomadik_src_clk_setup(struct device_node *np)
473	{
474	struct clk *clk = ERR_PTR(-EINVAL);
475	const char *clk_name = np->name;
476	const char *parent_name;
477	u32 clk_id;
478
479	if (of_property_read_u32(np, "clock-id", &clk_id)) {
480	pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
481	__func__, clk_name);
482	return;
483	}
484	parent_name = of_clk_get_parent_name(np, 0);
485	clk = src_clk_register(NULL, clk_name, parent_name, clk_id);
486	if (!IS_ERR(clk))
487	of_clk_add_provider(np, of_clk_src_simple_get, clk);
488	}
489
330d83b1	490	static const struct of_device_id nomadik_src_match[] __initconst = {
ef6eb322	491	{ .compatible = "stericsson,nomadik-src" },
6e2b07a1 LW	492	{ /* sentinel */ }
	493	};
	494
330d83b1	495	static const struct of_device_id nomadik_src_clk_match[] __initconst = {
ef6eb322 LW	496	{
	497	.compatible = "fixed-clock",
	498	.data = of_fixed_clk_setup,
	499	},
	500	{
	501	.compatible = "fixed-factor-clock",
	502	.data = of_fixed_factor_clk_setup,
	503	},
	504	{
	505	.compatible = "st,nomadik-pll-clock",
	506	.data = of_nomadik_pll_setup,
	507	},
	508	{
	509	.compatible = "st,nomadik-hclk-clock",
	510	.data = of_nomadik_hclk_setup,
	511	},
	512	{
	513	.compatible = "st,nomadik-src-clock",
	514	.data = of_nomadik_src_clk_setup,
	515	},
	516	{ /* sentinel */ }
	517	};
	518
	519	static int nomadik_clk_reboot_handler(struct notifier_block *this,
	520	unsigned long code,
	521	void *unused)
	522	{
	523	u32 val;
	524
	525	/* The main chrystal need to be enabled for reboot to work */
	526	val = readl(src_base + SRC_XTALCR);
	527	val &= ~SRC_XTALCR_MXTALOVER;
	528	val \|= SRC_XTALCR_MXTALEN;
	529	pr_crit("force-enabling MXTALO\n");
	530	writel(val, src_base + SRC_XTALCR);
	531	return NOTIFY_OK;
	532	}
	533
	534	static struct notifier_block nomadik_clk_reboot_notifier = {
	535	.notifier_call = nomadik_clk_reboot_handler,
	536	};
	537
4a31bd28 LW	538	void __init nomadik_clk_init(void)
4a31bd28 LW	539	{
ef6eb322 LW	540	struct device_node *np;
	541	u32 val;
	542
	543	np = of_find_matching_node(NULL, nomadik_src_match);
	544	if (!np) {
	545	pr_crit("no matching node for SRC, aborting clock init\n");
	546	return;
	547	}
	548	src_base = of_iomap(np, 0);
	549	if (!src_base) {
	550	pr_err("%s: must have src parent node with REGS (%s)\n",
	551	__func__, np->name);
	552	return;
	553	}
b9b5ab11 LW	554
	555	/* Set all timers to use the 2.4 MHz TIMCLK */
	556	val = readl(src_base + SRC_CR);
	557	val \|= SRC_CR_T0_ENSEL;
	558	val \|= SRC_CR_T1_ENSEL;
	559	val \|= SRC_CR_T2_ENSEL;
	560	val \|= SRC_CR_T3_ENSEL;
	561	val \|= SRC_CR_T4_ENSEL;
	562	val \|= SRC_CR_T5_ENSEL;
	563	val \|= SRC_CR_T6_ENSEL;
	564	val \|= SRC_CR_T7_ENSEL;
	565	writel(val, src_base + SRC_CR);
	566
ef6eb322 LW	567	val = readl(src_base + SRC_XTALCR);
	568	pr_info("SXTALO is %s\n",
	569	(val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
	570	pr_info("MXTAL is %s\n",
	571	(val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
	572	if (of_property_read_bool(np, "disable-sxtalo")) {
	573	/* The machine uses an external oscillator circuit */
	574	val \|= SRC_XTALCR_SXTALDIS;
	575	pr_info("disabling SXTALO\n");
	576	}
	577	if (of_property_read_bool(np, "disable-mxtalo")) {
	578	/* Disable this too: also run by external oscillator */
	579	val \|= SRC_XTALCR_MXTALOVER;
	580	val &= ~SRC_XTALCR_MXTALEN;
	581	pr_info("disabling MXTALO\n");
	582	}
	583	writel(val, src_base + SRC_XTALCR);
	584	register_reboot_notifier(&nomadik_clk_reboot_notifier);
	585
	586	of_clk_init(nomadik_src_clk_match);
4a31bd28	587	}