[deliverable/linux.git] / drivers / clk / clk-nomadik.c

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk-provider.h>

/*
 * The Nomadik clock tree is described in the STN8815A12 DB V4.2
 * reference manual for the chip, page 94 ff.
 */

void __init nomadik_clk_init(void)
{
	struct clk *clk;

	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
	clk_register_clkdev(clk, "apb_pclk", NULL);
	clk_register_clkdev(clk, NULL, "gpio.0");
	clk_register_clkdev(clk, NULL, "gpio.1");
	clk_register_clkdev(clk, NULL, "gpio.2");
	clk_register_clkdev(clk, NULL, "gpio.3");
	clk_register_clkdev(clk, NULL, "rng");
	clk_register_clkdev(clk, NULL, "fsmc-nand");

	/*
	 * The 2.4 MHz TIMCLK reference clock is active at boot time, this is
	 * actually the MXTALCLK @19.2 MHz divided by 8. This clock is used
	 * by the timers and watchdog. See page 105 ff.
	 */
	clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT,
				      2400000);
	clk_register_clkdev(clk, NULL, "mtu0");
	clk_register_clkdev(clk, NULL, "mtu1");

	/*
	 * At boot time, PLL2 is set to generate a set of fixed clocks,
	 * one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD
	 * I2C, IrDA, USB and SSP blocks.
	 */
	clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT,
				      48000000);
	clk_register_clkdev(clk, NULL, "uart0");
	clk_register_clkdev(clk, NULL, "uart1");
	clk_register_clkdev(clk, NULL, "mmci");
	clk_register_clkdev(clk, NULL, "ssp");
	clk_register_clkdev(clk, NULL, "nmk-i2c.0");
	clk_register_clkdev(clk, NULL, "nmk-i2c.1");
}
Commit	Line	Data
4a31bd28 LW	1	#include <linux/clk.h>
	2	#include <linux/clkdev.h>
	3	#include <linux/err.h>
	4	#include <linux/io.h>
	5	#include <linux/clk-provider.h>
	6
	7	/*
	8	* The Nomadik clock tree is described in the STN8815A12 DB V4.2
	9	* reference manual for the chip, page 94 ff.
	10	*/
	11
	12	void __init nomadik_clk_init(void)
	13	{
	14	struct clk *clk;
	15
	16	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
	17	clk_register_clkdev(clk, "apb_pclk", NULL);
	18	clk_register_clkdev(clk, NULL, "gpio.0");
	19	clk_register_clkdev(clk, NULL, "gpio.1");
	20	clk_register_clkdev(clk, NULL, "gpio.2");
	21	clk_register_clkdev(clk, NULL, "gpio.3");
	22	clk_register_clkdev(clk, NULL, "rng");
41863f73	23	clk_register_clkdev(clk, NULL, "fsmc-nand");
4a31bd28 LW	24
	25	/*
	26	* The 2.4 MHz TIMCLK reference clock is active at boot time, this is
	27	* actually the MXTALCLK @19.2 MHz divided by 8. This clock is used
	28	* by the timers and watchdog. See page 105 ff.
	29	*/
	30	clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT,
	31	2400000);
	32	clk_register_clkdev(clk, NULL, "mtu0");
	33	clk_register_clkdev(clk, NULL, "mtu1");
	34
	35	/*
	36	* At boot time, PLL2 is set to generate a set of fixed clocks,
	37	* one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD
	38	* I2C, IrDA, USB and SSP blocks.
	39	*/
	40	clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT,
	41	48000000);
	42	clk_register_clkdev(clk, NULL, "uart0");
	43	clk_register_clkdev(clk, NULL, "uart1");
	44	clk_register_clkdev(clk, NULL, "mmci");
	45	clk_register_clkdev(clk, NULL, "ssp");
	46	clk_register_clkdev(clk, NULL, "nmk-i2c.0");
	47	clk_register_clkdev(clk, NULL, "nmk-i2c.1");
	48	}