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555eae97 TY |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
93a17c05 | 8 | * clock driver for Freescale QorIQ SoCs. |
555eae97 | 9 | */ |
c88b2b66 EM |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
0dfc86b3 | 13 | #include <linux/clk.h> |
555eae97 | 14 | #include <linux/clk-provider.h> |
0dfc86b3 | 15 | #include <linux/fsl/guts.h> |
555eae97 TY |
16 | #include <linux/io.h> |
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
c11eede6 | 19 | #include <linux/of_address.h> |
555eae97 TY |
20 | #include <linux/of_platform.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/slab.h> | |
23 | ||
0dfc86b3 SW |
24 | #define PLL_DIV1 0 |
25 | #define PLL_DIV2 1 | |
26 | #define PLL_DIV3 2 | |
27 | #define PLL_DIV4 3 | |
28 | ||
29 | #define PLATFORM_PLL 0 | |
30 | #define CGA_PLL1 1 | |
31 | #define CGA_PLL2 2 | |
32 | #define CGA_PLL3 3 | |
33 | #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */ | |
34 | #define CGB_PLL1 4 | |
35 | #define CGB_PLL2 5 | |
36 | ||
37 | struct clockgen_pll_div { | |
38 | struct clk *clk; | |
39 | char name[32]; | |
40 | }; | |
41 | ||
42 | struct clockgen_pll { | |
43 | struct clockgen_pll_div div[4]; | |
44 | }; | |
45 | ||
46 | #define CLKSEL_VALID 1 | |
47 | #define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */ | |
48 | ||
49 | struct clockgen_sourceinfo { | |
50 | u32 flags; /* CLKSEL_xxx */ | |
51 | int pll; /* CGx_PLLn */ | |
52 | int div; /* PLL_DIVn */ | |
53 | }; | |
54 | ||
55 | #define NUM_MUX_PARENTS 16 | |
56 | ||
57 | struct clockgen_muxinfo { | |
58 | struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; | |
59 | }; | |
60 | ||
61 | #define NUM_HWACCEL 5 | |
62 | #define NUM_CMUX 8 | |
63 | ||
64 | struct clockgen; | |
65 | ||
66 | /* | |
67 | * cmux freq must be >= platform pll. | |
68 | * If not set, cmux freq must be >= platform pll/2 | |
69 | */ | |
70 | #define CG_CMUX_GE_PLAT 1 | |
9e19ca2f | 71 | |
0dfc86b3 | 72 | #define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */ |
9e19ca2f SW |
73 | #define CG_VER3 4 /* version 3 cg: reg layout different */ |
74 | #define CG_LITTLE_ENDIAN 8 | |
0dfc86b3 SW |
75 | |
76 | struct clockgen_chipinfo { | |
77 | const char *compat, *guts_compat; | |
78 | const struct clockgen_muxinfo *cmux_groups[2]; | |
79 | const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL]; | |
80 | void (*init_periph)(struct clockgen *cg); | |
81 | int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */ | |
82 | u32 pll_mask; /* 1 << n bit set if PLL n is valid */ | |
83 | u32 flags; /* CG_xxx */ | |
84 | }; | |
85 | ||
86 | struct clockgen { | |
87 | struct device_node *node; | |
88 | void __iomem *regs; | |
89 | struct clockgen_chipinfo info; /* mutable copy */ | |
90 | struct clk *sysclk; | |
91 | struct clockgen_pll pll[6]; | |
92 | struct clk *cmux[NUM_CMUX]; | |
93 | struct clk *hwaccel[NUM_HWACCEL]; | |
94 | struct clk *fman[2]; | |
95 | struct ccsr_guts __iomem *guts; | |
96 | }; | |
97 | ||
98 | static struct clockgen clockgen; | |
99 | ||
9e19ca2f SW |
100 | static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) |
101 | { | |
102 | if (cg->info.flags & CG_LITTLE_ENDIAN) | |
103 | iowrite32(val, reg); | |
104 | else | |
105 | iowrite32be(val, reg); | |
106 | } | |
107 | ||
108 | static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) | |
109 | { | |
110 | u32 val; | |
111 | ||
112 | if (cg->info.flags & CG_LITTLE_ENDIAN) | |
113 | val = ioread32(reg); | |
114 | else | |
115 | val = ioread32be(reg); | |
116 | ||
117 | return val; | |
118 | } | |
119 | ||
0dfc86b3 SW |
120 | static const struct clockgen_muxinfo p2041_cmux_grp1 = { |
121 | { | |
122 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
123 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
124 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, | |
125 | } | |
126 | }; | |
127 | ||
128 | static const struct clockgen_muxinfo p2041_cmux_grp2 = { | |
129 | { | |
130 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
2c7693e0 SW |
131 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, |
132 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
0dfc86b3 SW |
133 | } |
134 | }; | |
135 | ||
136 | static const struct clockgen_muxinfo p5020_cmux_grp1 = { | |
137 | { | |
138 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
139 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
140 | [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 }, | |
141 | } | |
142 | }; | |
143 | ||
144 | static const struct clockgen_muxinfo p5020_cmux_grp2 = { | |
145 | { | |
146 | [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, | |
147 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, | |
148 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
149 | } | |
150 | }; | |
151 | ||
152 | static const struct clockgen_muxinfo p5040_cmux_grp1 = { | |
153 | { | |
154 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
155 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
156 | [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 }, | |
157 | [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 }, | |
158 | } | |
159 | }; | |
160 | ||
161 | static const struct clockgen_muxinfo p5040_cmux_grp2 = { | |
162 | { | |
163 | [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, | |
164 | [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 }, | |
165 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, | |
166 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
167 | } | |
168 | }; | |
169 | ||
170 | static const struct clockgen_muxinfo p4080_cmux_grp1 = { | |
171 | { | |
172 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
173 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
174 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, | |
175 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
176 | [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 }, | |
177 | } | |
178 | }; | |
179 | ||
180 | static const struct clockgen_muxinfo p4080_cmux_grp2 = { | |
181 | { | |
182 | [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 }, | |
183 | [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 }, | |
184 | [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 }, | |
185 | [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 }, | |
186 | [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 }, | |
187 | } | |
188 | }; | |
189 | ||
190 | static const struct clockgen_muxinfo t1023_cmux = { | |
191 | { | |
192 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
193 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
194 | } | |
195 | }; | |
196 | ||
197 | static const struct clockgen_muxinfo t1040_cmux = { | |
198 | { | |
199 | [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
200 | [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
201 | [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, | |
202 | [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
203 | } | |
204 | }; | |
205 | ||
206 | ||
207 | static const struct clockgen_muxinfo clockgen2_cmux_cga = { | |
208 | { | |
209 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
210 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
211 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, | |
212 | {}, | |
213 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, | |
214 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
215 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, | |
216 | {}, | |
217 | { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 }, | |
218 | { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 }, | |
219 | { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 }, | |
220 | }, | |
221 | }; | |
222 | ||
223 | static const struct clockgen_muxinfo clockgen2_cmux_cga12 = { | |
224 | { | |
225 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
226 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
227 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, | |
228 | {}, | |
229 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, | |
230 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
231 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, | |
232 | }, | |
233 | }; | |
234 | ||
235 | static const struct clockgen_muxinfo clockgen2_cmux_cgb = { | |
236 | { | |
237 | { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 }, | |
238 | { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, | |
239 | { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 }, | |
240 | {}, | |
241 | { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 }, | |
242 | { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, | |
243 | { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 }, | |
244 | }, | |
245 | }; | |
246 | ||
247 | static const struct clockgen_muxinfo t1023_hwa1 = { | |
248 | { | |
249 | {}, | |
250 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
251 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
252 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, | |
253 | }, | |
254 | }; | |
255 | ||
256 | static const struct clockgen_muxinfo t1023_hwa2 = { | |
257 | { | |
258 | [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
259 | }, | |
260 | }; | |
261 | ||
262 | static const struct clockgen_muxinfo t2080_hwa1 = { | |
263 | { | |
264 | {}, | |
265 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
266 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
267 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, | |
268 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, | |
269 | { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, | |
270 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
271 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, | |
272 | }, | |
273 | }; | |
274 | ||
275 | static const struct clockgen_muxinfo t2080_hwa2 = { | |
276 | { | |
277 | {}, | |
278 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, | |
279 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
280 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, | |
281 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 }, | |
282 | { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, | |
283 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
284 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, | |
285 | }, | |
286 | }; | |
287 | ||
288 | static const struct clockgen_muxinfo t4240_hwa1 = { | |
289 | { | |
290 | { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 }, | |
291 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 }, | |
292 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, | |
293 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, | |
294 | { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, | |
295 | {}, | |
296 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, | |
297 | { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, | |
298 | }, | |
299 | }; | |
300 | ||
301 | static const struct clockgen_muxinfo t4240_hwa4 = { | |
302 | { | |
303 | [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, | |
304 | [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 }, | |
305 | [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 }, | |
306 | [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, | |
307 | [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, | |
308 | }, | |
309 | }; | |
310 | ||
311 | static const struct clockgen_muxinfo t4240_hwa5 = { | |
312 | { | |
313 | [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 }, | |
314 | [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 }, | |
315 | [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 }, | |
316 | [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, | |
317 | [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 }, | |
318 | [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 }, | |
319 | }, | |
320 | }; | |
321 | ||
322 | #define RCWSR7_FM1_CLK_SEL 0x40000000 | |
323 | #define RCWSR7_FM2_CLK_SEL 0x20000000 | |
324 | #define RCWSR7_HWA_ASYNC_DIV 0x04000000 | |
325 | ||
326 | static void __init p2041_init_periph(struct clockgen *cg) | |
327 | { | |
328 | u32 reg; | |
329 | ||
330 | reg = ioread32be(&cg->guts->rcwsr[7]); | |
331 | ||
332 | if (reg & RCWSR7_FM1_CLK_SEL) | |
333 | cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; | |
334 | else | |
335 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; | |
336 | } | |
337 | ||
338 | static void __init p4080_init_periph(struct clockgen *cg) | |
339 | { | |
340 | u32 reg; | |
341 | ||
342 | reg = ioread32be(&cg->guts->rcwsr[7]); | |
343 | ||
344 | if (reg & RCWSR7_FM1_CLK_SEL) | |
345 | cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; | |
346 | else | |
347 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; | |
348 | ||
349 | if (reg & RCWSR7_FM2_CLK_SEL) | |
350 | cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; | |
351 | else | |
352 | cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; | |
353 | } | |
354 | ||
355 | static void __init p5020_init_periph(struct clockgen *cg) | |
356 | { | |
357 | u32 reg; | |
358 | int div = PLL_DIV2; | |
359 | ||
360 | reg = ioread32be(&cg->guts->rcwsr[7]); | |
361 | if (reg & RCWSR7_HWA_ASYNC_DIV) | |
362 | div = PLL_DIV4; | |
363 | ||
364 | if (reg & RCWSR7_FM1_CLK_SEL) | |
365 | cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; | |
366 | else | |
367 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; | |
368 | } | |
369 | ||
370 | static void __init p5040_init_periph(struct clockgen *cg) | |
371 | { | |
372 | u32 reg; | |
373 | int div = PLL_DIV2; | |
374 | ||
375 | reg = ioread32be(&cg->guts->rcwsr[7]); | |
376 | if (reg & RCWSR7_HWA_ASYNC_DIV) | |
377 | div = PLL_DIV4; | |
378 | ||
379 | if (reg & RCWSR7_FM1_CLK_SEL) | |
380 | cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; | |
381 | else | |
382 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; | |
383 | ||
384 | if (reg & RCWSR7_FM2_CLK_SEL) | |
385 | cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; | |
386 | else | |
387 | cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; | |
388 | } | |
389 | ||
390 | static void __init t1023_init_periph(struct clockgen *cg) | |
391 | { | |
392 | cg->fman[0] = cg->hwaccel[1]; | |
393 | } | |
394 | ||
395 | static void __init t1040_init_periph(struct clockgen *cg) | |
396 | { | |
397 | cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; | |
398 | } | |
399 | ||
400 | static void __init t2080_init_periph(struct clockgen *cg) | |
401 | { | |
402 | cg->fman[0] = cg->hwaccel[0]; | |
403 | } | |
404 | ||
405 | static void __init t4240_init_periph(struct clockgen *cg) | |
406 | { | |
407 | cg->fman[0] = cg->hwaccel[3]; | |
408 | cg->fman[1] = cg->hwaccel[4]; | |
409 | } | |
410 | ||
411 | static const struct clockgen_chipinfo chipinfo[] = { | |
412 | { | |
413 | .compat = "fsl,b4420-clockgen", | |
414 | .guts_compat = "fsl,b4860-device-config", | |
415 | .init_periph = t2080_init_periph, | |
416 | .cmux_groups = { | |
417 | &clockgen2_cmux_cga12, &clockgen2_cmux_cgb | |
418 | }, | |
419 | .hwaccel = { | |
420 | &t2080_hwa1 | |
421 | }, | |
422 | .cmux_to_group = { | |
423 | 0, 1, 1, 1, -1 | |
424 | }, | |
425 | .pll_mask = 0x3f, | |
426 | .flags = CG_PLL_8BIT, | |
427 | }, | |
428 | { | |
429 | .compat = "fsl,b4860-clockgen", | |
430 | .guts_compat = "fsl,b4860-device-config", | |
431 | .init_periph = t2080_init_periph, | |
432 | .cmux_groups = { | |
433 | &clockgen2_cmux_cga12, &clockgen2_cmux_cgb | |
434 | }, | |
435 | .hwaccel = { | |
436 | &t2080_hwa1 | |
437 | }, | |
438 | .cmux_to_group = { | |
439 | 0, 1, 1, 1, -1 | |
440 | }, | |
441 | .pll_mask = 0x3f, | |
442 | .flags = CG_PLL_8BIT, | |
443 | }, | |
444 | { | |
445 | .compat = "fsl,ls1021a-clockgen", | |
446 | .cmux_groups = { | |
447 | &t1023_cmux | |
448 | }, | |
449 | .cmux_to_group = { | |
450 | 0, -1 | |
451 | }, | |
452 | .pll_mask = 0x03, | |
453 | }, | |
9e19ca2f SW |
454 | { |
455 | .compat = "fsl,ls2080a-clockgen", | |
456 | .cmux_groups = { | |
457 | &clockgen2_cmux_cga12, &clockgen2_cmux_cgb | |
458 | }, | |
459 | .cmux_to_group = { | |
460 | 0, 0, 1, 1, -1 | |
461 | }, | |
462 | .pll_mask = 0x37, | |
463 | .flags = CG_VER3 | CG_LITTLE_ENDIAN, | |
464 | }, | |
0dfc86b3 SW |
465 | { |
466 | .compat = "fsl,p2041-clockgen", | |
467 | .guts_compat = "fsl,qoriq-device-config-1.0", | |
468 | .init_periph = p2041_init_periph, | |
469 | .cmux_groups = { | |
470 | &p2041_cmux_grp1, &p2041_cmux_grp2 | |
471 | }, | |
472 | .cmux_to_group = { | |
473 | 0, 0, 1, 1, -1 | |
474 | }, | |
475 | .pll_mask = 0x07, | |
476 | }, | |
477 | { | |
478 | .compat = "fsl,p3041-clockgen", | |
479 | .guts_compat = "fsl,qoriq-device-config-1.0", | |
480 | .init_periph = p2041_init_periph, | |
481 | .cmux_groups = { | |
482 | &p2041_cmux_grp1, &p2041_cmux_grp2 | |
483 | }, | |
484 | .cmux_to_group = { | |
485 | 0, 0, 1, 1, -1 | |
486 | }, | |
487 | .pll_mask = 0x07, | |
488 | }, | |
489 | { | |
490 | .compat = "fsl,p4080-clockgen", | |
491 | .guts_compat = "fsl,qoriq-device-config-1.0", | |
492 | .init_periph = p4080_init_periph, | |
493 | .cmux_groups = { | |
494 | &p4080_cmux_grp1, &p4080_cmux_grp2 | |
495 | }, | |
496 | .cmux_to_group = { | |
497 | 0, 0, 0, 0, 1, 1, 1, 1 | |
498 | }, | |
499 | .pll_mask = 0x1f, | |
500 | }, | |
501 | { | |
502 | .compat = "fsl,p5020-clockgen", | |
503 | .guts_compat = "fsl,qoriq-device-config-1.0", | |
504 | .init_periph = p5020_init_periph, | |
505 | .cmux_groups = { | |
506 | &p2041_cmux_grp1, &p2041_cmux_grp2 | |
507 | }, | |
508 | .cmux_to_group = { | |
509 | 0, 1, -1 | |
510 | }, | |
511 | .pll_mask = 0x07, | |
512 | }, | |
513 | { | |
514 | .compat = "fsl,p5040-clockgen", | |
515 | .guts_compat = "fsl,p5040-device-config", | |
516 | .init_periph = p5040_init_periph, | |
517 | .cmux_groups = { | |
518 | &p5040_cmux_grp1, &p5040_cmux_grp2 | |
519 | }, | |
520 | .cmux_to_group = { | |
521 | 0, 0, 1, 1, -1 | |
522 | }, | |
523 | .pll_mask = 0x0f, | |
524 | }, | |
525 | { | |
526 | .compat = "fsl,t1023-clockgen", | |
527 | .guts_compat = "fsl,t1023-device-config", | |
528 | .init_periph = t1023_init_periph, | |
529 | .cmux_groups = { | |
530 | &t1023_cmux | |
531 | }, | |
532 | .hwaccel = { | |
533 | &t1023_hwa1, &t1023_hwa2 | |
534 | }, | |
535 | .cmux_to_group = { | |
536 | 0, 0, -1 | |
537 | }, | |
538 | .pll_mask = 0x03, | |
539 | .flags = CG_PLL_8BIT, | |
540 | }, | |
541 | { | |
542 | .compat = "fsl,t1040-clockgen", | |
543 | .guts_compat = "fsl,t1040-device-config", | |
544 | .init_periph = t1040_init_periph, | |
545 | .cmux_groups = { | |
546 | &t1040_cmux | |
547 | }, | |
548 | .cmux_to_group = { | |
549 | 0, 0, 0, 0, -1 | |
550 | }, | |
551 | .pll_mask = 0x07, | |
552 | .flags = CG_PLL_8BIT, | |
553 | }, | |
554 | { | |
555 | .compat = "fsl,t2080-clockgen", | |
556 | .guts_compat = "fsl,t2080-device-config", | |
557 | .init_periph = t2080_init_periph, | |
558 | .cmux_groups = { | |
559 | &clockgen2_cmux_cga12 | |
560 | }, | |
561 | .hwaccel = { | |
562 | &t2080_hwa1, &t2080_hwa2 | |
563 | }, | |
564 | .cmux_to_group = { | |
565 | 0, -1 | |
566 | }, | |
567 | .pll_mask = 0x07, | |
568 | .flags = CG_PLL_8BIT, | |
569 | }, | |
570 | { | |
571 | .compat = "fsl,t4240-clockgen", | |
572 | .guts_compat = "fsl,t4240-device-config", | |
573 | .init_periph = t4240_init_periph, | |
574 | .cmux_groups = { | |
575 | &clockgen2_cmux_cga, &clockgen2_cmux_cgb | |
576 | }, | |
577 | .hwaccel = { | |
578 | &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5 | |
579 | }, | |
580 | .cmux_to_group = { | |
581 | 0, 0, 1, -1 | |
582 | }, | |
583 | .pll_mask = 0x3f, | |
584 | .flags = CG_PLL_8BIT, | |
585 | }, | |
586 | {}, | |
587 | }; | |
588 | ||
589 | struct mux_hwclock { | |
555eae97 | 590 | struct clk_hw hw; |
0dfc86b3 SW |
591 | struct clockgen *cg; |
592 | const struct clockgen_muxinfo *info; | |
593 | u32 __iomem *reg; | |
594 | u8 parent_to_clksel[NUM_MUX_PARENTS]; | |
595 | s8 clksel_to_parent[NUM_MUX_PARENTS]; | |
596 | int num_parents; | |
555eae97 TY |
597 | }; |
598 | ||
0dfc86b3 SW |
599 | #define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw) |
600 | #define CLKSEL_MASK 0x78000000 | |
555eae97 | 601 | #define CLKSEL_SHIFT 27 |
555eae97 | 602 | |
0dfc86b3 | 603 | static int mux_set_parent(struct clk_hw *hw, u8 idx) |
555eae97 | 604 | { |
0dfc86b3 | 605 | struct mux_hwclock *hwc = to_mux_hwclock(hw); |
555eae97 TY |
606 | u32 clksel; |
607 | ||
0dfc86b3 SW |
608 | if (idx >= hwc->num_parents) |
609 | return -EINVAL; | |
610 | ||
611 | clksel = hwc->parent_to_clksel[idx]; | |
9e19ca2f | 612 | cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); |
555eae97 TY |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
0dfc86b3 | 617 | static u8 mux_get_parent(struct clk_hw *hw) |
555eae97 | 618 | { |
0dfc86b3 | 619 | struct mux_hwclock *hwc = to_mux_hwclock(hw); |
555eae97 | 620 | u32 clksel; |
0dfc86b3 | 621 | s8 ret; |
555eae97 | 622 | |
9e19ca2f | 623 | clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; |
555eae97 | 624 | |
0dfc86b3 SW |
625 | ret = hwc->clksel_to_parent[clksel]; |
626 | if (ret < 0) { | |
627 | pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); | |
628 | return 0; | |
629 | } | |
630 | ||
631 | return ret; | |
555eae97 TY |
632 | } |
633 | ||
334680dd | 634 | static const struct clk_ops cmux_ops = { |
0dfc86b3 SW |
635 | .get_parent = mux_get_parent, |
636 | .set_parent = mux_set_parent, | |
555eae97 TY |
637 | }; |
638 | ||
0dfc86b3 SW |
639 | /* |
640 | * Don't allow setting for now, as the clock options haven't been | |
641 | * sanitized for additional restrictions. | |
642 | */ | |
643 | static const struct clk_ops hwaccel_ops = { | |
644 | .get_parent = mux_get_parent, | |
645 | }; | |
646 | ||
647 | static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg, | |
648 | struct mux_hwclock *hwc, | |
649 | int idx) | |
555eae97 | 650 | { |
0dfc86b3 | 651 | int pll, div; |
555eae97 | 652 | |
0dfc86b3 SW |
653 | if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) |
654 | return NULL; | |
555eae97 | 655 | |
0dfc86b3 SW |
656 | pll = hwc->info->clksel[idx].pll; |
657 | div = hwc->info->clksel[idx].div; | |
555eae97 | 658 | |
0dfc86b3 SW |
659 | return &cg->pll[pll].div[div]; |
660 | } | |
555eae97 | 661 | |
0dfc86b3 SW |
662 | static struct clk * __init create_mux_common(struct clockgen *cg, |
663 | struct mux_hwclock *hwc, | |
664 | const struct clk_ops *ops, | |
665 | unsigned long min_rate, | |
666 | unsigned long pct80_rate, | |
667 | const char *fmt, int idx) | |
668 | { | |
669 | struct clk_init_data init = {}; | |
670 | struct clk *clk; | |
671 | const struct clockgen_pll_div *div; | |
672 | const char *parent_names[NUM_MUX_PARENTS]; | |
673 | char name[32]; | |
674 | int i, j; | |
8002cab6 | 675 | |
0dfc86b3 | 676 | snprintf(name, sizeof(name), fmt, idx); |
555eae97 | 677 | |
0dfc86b3 SW |
678 | for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) { |
679 | unsigned long rate; | |
57bfd7ee | 680 | |
0dfc86b3 | 681 | hwc->clksel_to_parent[i] = -1; |
57bfd7ee | 682 | |
0dfc86b3 SW |
683 | div = get_pll_div(cg, hwc, i); |
684 | if (!div) | |
685 | continue; | |
555eae97 | 686 | |
0dfc86b3 SW |
687 | rate = clk_get_rate(div->clk); |
688 | ||
689 | if (hwc->info->clksel[i].flags & CLKSEL_80PCT && | |
690 | rate > pct80_rate) | |
691 | continue; | |
692 | if (rate < min_rate) | |
693 | continue; | |
694 | ||
695 | parent_names[j] = div->name; | |
696 | hwc->parent_to_clksel[j] = i; | |
697 | hwc->clksel_to_parent[i] = j; | |
698 | j++; | |
555eae97 TY |
699 | } |
700 | ||
0dfc86b3 SW |
701 | init.name = name; |
702 | init.ops = ops; | |
555eae97 | 703 | init.parent_names = parent_names; |
0dfc86b3 | 704 | init.num_parents = hwc->num_parents = j; |
555eae97 | 705 | init.flags = 0; |
0dfc86b3 SW |
706 | hwc->hw.init = &init; |
707 | hwc->cg = cg; | |
555eae97 | 708 | |
0dfc86b3 | 709 | clk = clk_register(NULL, &hwc->hw); |
555eae97 | 710 | if (IS_ERR(clk)) { |
0dfc86b3 SW |
711 | pr_err("%s: Couldn't register %s: %ld\n", __func__, name, |
712 | PTR_ERR(clk)); | |
713 | kfree(hwc); | |
714 | return NULL; | |
715 | } | |
716 | ||
717 | return clk; | |
718 | } | |
719 | ||
720 | static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) | |
721 | { | |
722 | struct mux_hwclock *hwc; | |
723 | const struct clockgen_pll_div *div; | |
724 | unsigned long plat_rate, min_rate; | |
725 | u64 pct80_rate; | |
726 | u32 clksel; | |
727 | ||
728 | hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); | |
729 | if (!hwc) | |
730 | return NULL; | |
731 | ||
732 | hwc->reg = cg->regs + 0x20 * idx; | |
733 | hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; | |
734 | ||
735 | /* | |
736 | * Find the rate for the default clksel, and treat it as the | |
737 | * maximum rated core frequency. If this is an incorrect | |
738 | * assumption, certain clock options (possibly including the | |
739 | * default clksel) may be inappropriately excluded on certain | |
740 | * chips. | |
741 | */ | |
9e19ca2f | 742 | clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; |
0dfc86b3 SW |
743 | div = get_pll_div(cg, hwc, clksel); |
744 | if (!div) | |
745 | return NULL; | |
746 | ||
747 | pct80_rate = clk_get_rate(div->clk); | |
748 | pct80_rate *= 8; | |
749 | do_div(pct80_rate, 10); | |
750 | ||
751 | plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); | |
752 | ||
753 | if (cg->info.flags & CG_CMUX_GE_PLAT) | |
754 | min_rate = plat_rate; | |
755 | else | |
756 | min_rate = plat_rate / 2; | |
757 | ||
758 | return create_mux_common(cg, hwc, &cmux_ops, min_rate, | |
759 | pct80_rate, "cg-cmux%d", idx); | |
760 | } | |
761 | ||
762 | static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) | |
763 | { | |
764 | struct mux_hwclock *hwc; | |
765 | ||
766 | hwc = kzalloc(sizeof(*hwc), GFP_KERNEL); | |
767 | if (!hwc) | |
768 | return NULL; | |
769 | ||
770 | hwc->reg = cg->regs + 0x20 * idx + 0x10; | |
771 | hwc->info = cg->info.hwaccel[idx]; | |
772 | ||
773 | return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0, | |
774 | "cg-hwaccel%d", idx); | |
775 | } | |
776 | ||
777 | static void __init create_muxes(struct clockgen *cg) | |
778 | { | |
779 | int i; | |
780 | ||
781 | for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { | |
782 | if (cg->info.cmux_to_group[i] < 0) | |
783 | break; | |
784 | if (cg->info.cmux_to_group[i] >= | |
785 | ARRAY_SIZE(cg->info.cmux_groups)) { | |
786 | WARN_ON_ONCE(1); | |
787 | continue; | |
788 | } | |
789 | ||
790 | cg->cmux[i] = create_one_cmux(cg, i); | |
555eae97 TY |
791 | } |
792 | ||
0dfc86b3 SW |
793 | for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { |
794 | if (!cg->info.hwaccel[i]) | |
795 | continue; | |
796 | ||
797 | cg->hwaccel[i] = create_one_hwaccel(cg, i); | |
798 | } | |
799 | } | |
800 | ||
801 | static void __init clockgen_init(struct device_node *np); | |
802 | ||
803 | /* Legacy nodes may get probed before the parent clockgen node */ | |
804 | static void __init legacy_init_clockgen(struct device_node *np) | |
805 | { | |
806 | if (!clockgen.node) | |
807 | clockgen_init(of_get_parent(np)); | |
808 | } | |
809 | ||
810 | /* Legacy node */ | |
811 | static void __init core_mux_init(struct device_node *np) | |
812 | { | |
813 | struct clk *clk; | |
814 | struct resource res; | |
815 | int idx, rc; | |
816 | ||
817 | legacy_init_clockgen(np); | |
818 | ||
819 | if (of_address_to_resource(np, 0, &res)) | |
820 | return; | |
821 | ||
822 | idx = (res.start & 0xf0) >> 5; | |
823 | clk = clockgen.cmux[idx]; | |
824 | ||
555eae97 TY |
825 | rc = of_clk_add_provider(np, of_clk_src_simple_get, clk); |
826 | if (rc) { | |
0dfc86b3 SW |
827 | pr_err("%s: Couldn't register clk provider for node %s: %d\n", |
828 | __func__, np->name, rc); | |
829 | return; | |
555eae97 | 830 | } |
0dfc86b3 | 831 | } |
555eae97 | 832 | |
0dfc86b3 SW |
833 | static struct clk *sysclk_from_fixed(struct device_node *node, const char *name) |
834 | { | |
835 | u32 rate; | |
836 | ||
837 | if (of_property_read_u32(node, "clock-frequency", &rate)) | |
838 | return ERR_PTR(-ENODEV); | |
839 | ||
840 | return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); | |
555eae97 TY |
841 | } |
842 | ||
0dfc86b3 SW |
843 | static struct clk *sysclk_from_parent(const char *name) |
844 | { | |
845 | struct clk *clk; | |
846 | const char *parent_name; | |
847 | ||
848 | clk = of_clk_get(clockgen.node, 0); | |
849 | if (IS_ERR(clk)) | |
850 | return clk; | |
851 | ||
852 | /* Register the input clock under the desired name. */ | |
853 | parent_name = __clk_get_name(clk); | |
854 | clk = clk_register_fixed_factor(NULL, name, parent_name, | |
855 | 0, 1, 1); | |
856 | if (IS_ERR(clk)) | |
857 | pr_err("%s: Couldn't register %s: %ld\n", __func__, name, | |
858 | PTR_ERR(clk)); | |
859 | ||
860 | return clk; | |
861 | } | |
862 | ||
863 | static struct clk * __init create_sysclk(const char *name) | |
864 | { | |
865 | struct device_node *sysclk; | |
866 | struct clk *clk; | |
867 | ||
868 | clk = sysclk_from_fixed(clockgen.node, name); | |
869 | if (!IS_ERR(clk)) | |
870 | return clk; | |
871 | ||
872 | clk = sysclk_from_parent(name); | |
873 | if (!IS_ERR(clk)) | |
874 | return clk; | |
875 | ||
876 | sysclk = of_get_child_by_name(clockgen.node, "sysclk"); | |
877 | if (sysclk) { | |
878 | clk = sysclk_from_fixed(sysclk, name); | |
879 | if (!IS_ERR(clk)) | |
880 | return clk; | |
881 | } | |
882 | ||
883 | pr_err("%s: No input clock\n", __func__); | |
884 | return NULL; | |
885 | } | |
886 | ||
887 | /* Legacy node */ | |
888 | static void __init sysclk_init(struct device_node *node) | |
889 | { | |
890 | struct clk *clk; | |
891 | ||
892 | legacy_init_clockgen(node); | |
893 | ||
894 | clk = clockgen.sysclk; | |
895 | if (clk) | |
896 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
897 | } | |
898 | ||
899 | #define PLL_KILL BIT(31) | |
900 | ||
901 | static void __init create_one_pll(struct clockgen *cg, int idx) | |
555eae97 | 902 | { |
0dfc86b3 | 903 | u32 __iomem *reg; |
00fa6e5d | 904 | u32 mult; |
0dfc86b3 SW |
905 | struct clockgen_pll *pll = &cg->pll[idx]; |
906 | int i; | |
555eae97 | 907 | |
0dfc86b3 | 908 | if (!(cg->info.pll_mask & (1 << idx))) |
555eae97 | 909 | return; |
555eae97 | 910 | |
9e19ca2f SW |
911 | if (cg->info.flags & CG_VER3) { |
912 | switch (idx) { | |
913 | case PLATFORM_PLL: | |
914 | reg = cg->regs + 0x60080; | |
915 | break; | |
916 | case CGA_PLL1: | |
917 | reg = cg->regs + 0x80; | |
918 | break; | |
919 | case CGA_PLL2: | |
920 | reg = cg->regs + 0xa0; | |
921 | break; | |
922 | case CGB_PLL1: | |
923 | reg = cg->regs + 0x10080; | |
924 | break; | |
925 | case CGB_PLL2: | |
926 | reg = cg->regs + 0x100a0; | |
927 | break; | |
928 | default: | |
929 | WARN_ONCE(1, "index %d\n", idx); | |
930 | return; | |
931 | } | |
932 | } else { | |
933 | if (idx == PLATFORM_PLL) | |
934 | reg = cg->regs + 0xc00; | |
935 | else | |
936 | reg = cg->regs + 0x800 + 0x20 * (idx - 1); | |
937 | } | |
555eae97 | 938 | |
0dfc86b3 | 939 | /* Get the multiple of PLL */ |
9e19ca2f | 940 | mult = cg_in(cg, reg); |
0dfc86b3 SW |
941 | |
942 | /* Check if this PLL is disabled */ | |
555eae97 | 943 | if (mult & PLL_KILL) { |
0dfc86b3 SW |
944 | pr_debug("%s(): pll %p disabled\n", __func__, reg); |
945 | return; | |
555eae97 | 946 | } |
555eae97 | 947 | |
9e19ca2f SW |
948 | if ((cg->info.flags & CG_VER3) || |
949 | ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) | |
0dfc86b3 SW |
950 | mult = (mult & GENMASK(8, 1)) >> 1; |
951 | else | |
952 | mult = (mult & GENMASK(6, 1)) >> 1; | |
953 | ||
954 | for (i = 0; i < ARRAY_SIZE(pll->div); i++) { | |
955 | struct clk *clk; | |
956 | ||
957 | snprintf(pll->div[i].name, sizeof(pll->div[i].name), | |
958 | "cg-pll%d-div%d", idx, i + 1); | |
959 | ||
960 | clk = clk_register_fixed_factor(NULL, | |
961 | pll->div[i].name, "cg-sysclk", 0, mult, i + 1); | |
962 | if (IS_ERR(clk)) { | |
963 | pr_err("%s: %s: register failed %ld\n", | |
964 | __func__, pll->div[i].name, PTR_ERR(clk)); | |
965 | continue; | |
966 | } | |
967 | ||
968 | pll->div[i].clk = clk; | |
555eae97 | 969 | } |
0dfc86b3 SW |
970 | } |
971 | ||
972 | static void __init create_plls(struct clockgen *cg) | |
973 | { | |
974 | int i; | |
975 | ||
976 | for (i = 0; i < ARRAY_SIZE(cg->pll); i++) | |
977 | create_one_pll(cg, i); | |
978 | } | |
555eae97 | 979 | |
0dfc86b3 SW |
980 | static void __init legacy_pll_init(struct device_node *np, int idx) |
981 | { | |
982 | struct clockgen_pll *pll; | |
983 | struct clk_onecell_data *onecell_data; | |
984 | struct clk **subclks; | |
985 | int count, rc; | |
986 | ||
987 | legacy_init_clockgen(np); | |
988 | ||
989 | pll = &clockgen.pll[idx]; | |
555eae97 | 990 | count = of_property_count_strings(np, "clock-output-names"); |
555eae97 | 991 | |
0dfc86b3 SW |
992 | BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4); |
993 | subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL); | |
8002cab6 | 994 | if (!subclks) |
0dfc86b3 | 995 | return; |
555eae97 | 996 | |
6ef1ccac | 997 | onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL); |
8002cab6 | 998 | if (!onecell_data) |
555eae97 | 999 | goto err_clks; |
555eae97 | 1000 | |
0dfc86b3 SW |
1001 | if (count <= 3) { |
1002 | subclks[0] = pll->div[0].clk; | |
1003 | subclks[1] = pll->div[1].clk; | |
1004 | subclks[2] = pll->div[3].clk; | |
1005 | } else { | |
1006 | subclks[0] = pll->div[0].clk; | |
1007 | subclks[1] = pll->div[1].clk; | |
1008 | subclks[2] = pll->div[2].clk; | |
1009 | subclks[3] = pll->div[3].clk; | |
555eae97 TY |
1010 | } |
1011 | ||
1012 | onecell_data->clks = subclks; | |
1013 | onecell_data->clk_num = count; | |
1014 | ||
1015 | rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data); | |
1016 | if (rc) { | |
0dfc86b3 SW |
1017 | pr_err("%s: Couldn't register clk provider for node %s: %d\n", |
1018 | __func__, np->name, rc); | |
555eae97 TY |
1019 | goto err_cell; |
1020 | } | |
1021 | ||
1022 | return; | |
1023 | err_cell: | |
1024 | kfree(onecell_data); | |
1025 | err_clks: | |
1026 | kfree(subclks); | |
00fa6e5d TY |
1027 | } |
1028 | ||
0dfc86b3 SW |
1029 | /* Legacy node */ |
1030 | static void __init pltfrm_pll_init(struct device_node *np) | |
00fa6e5d | 1031 | { |
0dfc86b3 SW |
1032 | legacy_pll_init(np, PLATFORM_PLL); |
1033 | } | |
00fa6e5d | 1034 | |
0dfc86b3 SW |
1035 | /* Legacy node */ |
1036 | static void __init core_pll_init(struct device_node *np) | |
1037 | { | |
1038 | struct resource res; | |
1039 | int idx; | |
1040 | ||
1041 | if (of_address_to_resource(np, 0, &res)) | |
00fa6e5d | 1042 | return; |
0dfc86b3 SW |
1043 | |
1044 | if ((res.start & 0xfff) == 0xc00) { | |
1045 | /* | |
1046 | * ls1021a devtree labels the platform PLL | |
1047 | * with the core PLL compatible | |
1048 | */ | |
1049 | pltfrm_pll_init(np); | |
1050 | } else { | |
1051 | idx = (res.start & 0xf0) >> 5; | |
1052 | legacy_pll_init(np, CGA_PLL1 + idx); | |
00fa6e5d | 1053 | } |
0dfc86b3 | 1054 | } |
00fa6e5d | 1055 | |
0dfc86b3 SW |
1056 | static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data) |
1057 | { | |
1058 | struct clockgen *cg = data; | |
1059 | struct clk *clk; | |
1060 | struct clockgen_pll *pll; | |
1061 | u32 type, idx; | |
1062 | ||
1063 | if (clkspec->args_count < 2) { | |
1064 | pr_err("%s: insufficient phandle args\n", __func__); | |
1065 | return ERR_PTR(-EINVAL); | |
00fa6e5d TY |
1066 | } |
1067 | ||
0dfc86b3 SW |
1068 | type = clkspec->args[0]; |
1069 | idx = clkspec->args[1]; | |
00fa6e5d | 1070 | |
0dfc86b3 SW |
1071 | switch (type) { |
1072 | case 0: | |
1073 | if (idx != 0) | |
1074 | goto bad_args; | |
1075 | clk = cg->sysclk; | |
1076 | break; | |
1077 | case 1: | |
1078 | if (idx >= ARRAY_SIZE(cg->cmux)) | |
1079 | goto bad_args; | |
1080 | clk = cg->cmux[idx]; | |
1081 | break; | |
1082 | case 2: | |
1083 | if (idx >= ARRAY_SIZE(cg->hwaccel)) | |
1084 | goto bad_args; | |
1085 | clk = cg->hwaccel[idx]; | |
1086 | break; | |
1087 | case 3: | |
1088 | if (idx >= ARRAY_SIZE(cg->fman)) | |
1089 | goto bad_args; | |
1090 | clk = cg->fman[idx]; | |
1091 | break; | |
1092 | case 4: | |
1093 | pll = &cg->pll[PLATFORM_PLL]; | |
1094 | if (idx >= ARRAY_SIZE(pll->div)) | |
1095 | goto bad_args; | |
1096 | clk = pll->div[idx].clk; | |
1097 | break; | |
1098 | default: | |
1099 | goto bad_args; | |
1100 | } | |
1101 | ||
1102 | if (!clk) | |
1103 | return ERR_PTR(-ENOENT); | |
1104 | return clk; | |
1105 | ||
1106 | bad_args: | |
1107 | pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx); | |
1108 | return ERR_PTR(-EINVAL); | |
555eae97 | 1109 | } |
a513b72c | 1110 | |
0dfc86b3 SW |
1111 | #ifdef CONFIG_PPC |
1112 | #include <asm/mpc85xx.h> | |
1113 | ||
1114 | static const u32 a4510_svrs[] __initconst = { | |
1115 | (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */ | |
1116 | (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */ | |
1117 | (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */ | |
1118 | (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */ | |
1119 | (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */ | |
1120 | (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */ | |
1121 | (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */ | |
1122 | (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */ | |
1123 | (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */ | |
1124 | (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */ | |
1125 | (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */ | |
1126 | (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */ | |
1127 | (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */ | |
1128 | }; | |
1129 | ||
1130 | #define SVR_SECURITY 0x80000 /* The Security (E) bit */ | |
1131 | ||
1132 | static bool __init has_erratum_a4510(void) | |
a513b72c | 1133 | { |
0dfc86b3 SW |
1134 | u32 svr = mfspr(SPRN_SVR); |
1135 | int i; | |
1136 | ||
1137 | svr &= ~SVR_SECURITY; | |
1138 | ||
1139 | for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) { | |
1140 | if (svr == a4510_svrs[i]) | |
1141 | return true; | |
a513b72c EM |
1142 | } |
1143 | ||
0dfc86b3 SW |
1144 | return false; |
1145 | } | |
1146 | #else | |
1147 | static bool __init has_erratum_a4510(void) | |
1148 | { | |
1149 | return false; | |
1150 | } | |
1151 | #endif | |
a513b72c | 1152 | |
0dfc86b3 SW |
1153 | static void __init clockgen_init(struct device_node *np) |
1154 | { | |
1155 | int i, ret; | |
1156 | bool is_old_ls1021a = false; | |
a513b72c | 1157 | |
0dfc86b3 SW |
1158 | /* May have already been called by a legacy probe */ |
1159 | if (clockgen.node) | |
a513b72c | 1160 | return; |
a513b72c | 1161 | |
0dfc86b3 SW |
1162 | clockgen.node = np; |
1163 | clockgen.regs = of_iomap(np, 0); | |
1164 | if (!clockgen.regs && | |
1165 | of_device_is_compatible(of_root, "fsl,ls1021a")) { | |
1166 | /* Compatibility hack for old, broken device trees */ | |
1167 | clockgen.regs = ioremap(0x1ee1000, 0x1000); | |
1168 | is_old_ls1021a = true; | |
1169 | } | |
1170 | if (!clockgen.regs) { | |
1171 | pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name); | |
a513b72c EM |
1172 | return; |
1173 | } | |
1174 | ||
0dfc86b3 SW |
1175 | for (i = 0; i < ARRAY_SIZE(chipinfo); i++) { |
1176 | if (of_device_is_compatible(np, chipinfo[i].compat)) | |
1177 | break; | |
1178 | if (is_old_ls1021a && | |
1179 | !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen")) | |
1180 | break; | |
a513b72c EM |
1181 | } |
1182 | ||
0dfc86b3 SW |
1183 | if (i == ARRAY_SIZE(chipinfo)) { |
1184 | pr_err("%s: unknown clockgen node %s\n", __func__, | |
1185 | np->full_name); | |
1186 | goto err; | |
1187 | } | |
1188 | clockgen.info = chipinfo[i]; | |
1189 | ||
1190 | if (clockgen.info.guts_compat) { | |
1191 | struct device_node *guts; | |
a513b72c | 1192 | |
0dfc86b3 SW |
1193 | guts = of_find_compatible_node(NULL, NULL, |
1194 | clockgen.info.guts_compat); | |
1195 | if (guts) { | |
1196 | clockgen.guts = of_iomap(guts, 0); | |
1197 | if (!clockgen.guts) { | |
1198 | pr_err("%s: Couldn't map %s regs\n", __func__, | |
1199 | guts->full_name); | |
1200 | } | |
a513b72c | 1201 | } |
0dfc86b3 | 1202 | |
a513b72c EM |
1203 | } |
1204 | ||
0dfc86b3 SW |
1205 | if (has_erratum_a4510()) |
1206 | clockgen.info.flags |= CG_CMUX_GE_PLAT; | |
1207 | ||
1208 | clockgen.sysclk = create_sysclk("cg-sysclk"); | |
1209 | create_plls(&clockgen); | |
1210 | create_muxes(&clockgen); | |
1211 | ||
1212 | if (clockgen.info.init_periph) | |
1213 | clockgen.info.init_periph(&clockgen); | |
1214 | ||
1215 | ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen); | |
1216 | if (ret) { | |
1217 | pr_err("%s: Couldn't register clk provider for node %s: %d\n", | |
1218 | __func__, np->name, ret); | |
a513b72c EM |
1219 | } |
1220 | ||
1221 | return; | |
0dfc86b3 SW |
1222 | err: |
1223 | iounmap(clockgen.regs); | |
1224 | clockgen.regs = NULL; | |
a513b72c EM |
1225 | } |
1226 | ||
0dfc86b3 SW |
1227 | CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); |
1228 | CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); | |
1229 | CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); | |
9e19ca2f | 1230 | CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); |
0dfc86b3 SW |
1231 | |
1232 | /* Legacy nodes */ | |
66619ac5 KH |
1233 | CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); |
1234 | CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init); | |
1235 | CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init); | |
1236 | CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init); | |
1237 | CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init); | |
1238 | CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init); | |
a513b72c EM |
1239 | CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init); |
1240 | CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init); |