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85814d69 TP |
1 | /* |
2 | * Clock implementation for VIA/Wondermedia SoC's | |
3 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
4 | * | |
5 | * This software is licensed under the terms of the GNU General Public | |
6 | * License version 2, as published by the Free Software Foundation, and | |
7 | * may be copied, distributed, and modified under those terms. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <linux/io.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/bitops.h> | |
20 | #include <linux/clkdev.h> | |
21 | #include <linux/clk-provider.h> | |
22 | ||
23 | /* All clocks share the same lock as none can be changed concurrently */ | |
24 | static DEFINE_SPINLOCK(_lock); | |
25 | ||
26 | struct clk_device { | |
27 | struct clk_hw hw; | |
28 | void __iomem *div_reg; | |
29 | unsigned int div_mask; | |
30 | void __iomem *en_reg; | |
31 | int en_bit; | |
32 | spinlock_t *lock; | |
33 | }; | |
34 | ||
35 | /* | |
36 | * Add new PLL_TYPE_x definitions here as required. Use the first known model | |
37 | * to support the new type as the name. | |
38 | * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and | |
39 | * vtwm_pll_set_rate() to handle the new PLL_TYPE_x | |
40 | */ | |
41 | ||
42 | #define PLL_TYPE_VT8500 0 | |
43 | #define PLL_TYPE_WM8650 1 | |
abb165a8 | 44 | #define PLL_TYPE_WM8750 2 |
85814d69 TP |
45 | |
46 | struct clk_pll { | |
47 | struct clk_hw hw; | |
48 | void __iomem *reg; | |
49 | spinlock_t *lock; | |
50 | int type; | |
51 | }; | |
52 | ||
53 | static void __iomem *pmc_base; | |
54 | ||
55 | #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw) | |
56 | ||
57 | #define VT8500_PMC_BUSY_MASK 0x18 | |
58 | ||
59 | static void vt8500_pmc_wait_busy(void) | |
60 | { | |
61 | while (readl(pmc_base) & VT8500_PMC_BUSY_MASK) | |
62 | cpu_relax(); | |
63 | } | |
64 | ||
65 | static int vt8500_dclk_enable(struct clk_hw *hw) | |
66 | { | |
67 | struct clk_device *cdev = to_clk_device(hw); | |
68 | u32 en_val; | |
69 | unsigned long flags = 0; | |
70 | ||
71 | spin_lock_irqsave(cdev->lock, flags); | |
72 | ||
73 | en_val = readl(cdev->en_reg); | |
74 | en_val |= BIT(cdev->en_bit); | |
75 | writel(en_val, cdev->en_reg); | |
76 | ||
77 | spin_unlock_irqrestore(cdev->lock, flags); | |
78 | return 0; | |
79 | } | |
80 | ||
81 | static void vt8500_dclk_disable(struct clk_hw *hw) | |
82 | { | |
83 | struct clk_device *cdev = to_clk_device(hw); | |
84 | u32 en_val; | |
85 | unsigned long flags = 0; | |
86 | ||
87 | spin_lock_irqsave(cdev->lock, flags); | |
88 | ||
89 | en_val = readl(cdev->en_reg); | |
90 | en_val &= ~BIT(cdev->en_bit); | |
91 | writel(en_val, cdev->en_reg); | |
92 | ||
93 | spin_unlock_irqrestore(cdev->lock, flags); | |
94 | } | |
95 | ||
96 | static int vt8500_dclk_is_enabled(struct clk_hw *hw) | |
97 | { | |
98 | struct clk_device *cdev = to_clk_device(hw); | |
99 | u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit)); | |
100 | ||
101 | return en_val ? 1 : 0; | |
102 | } | |
103 | ||
104 | static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw, | |
105 | unsigned long parent_rate) | |
106 | { | |
107 | struct clk_device *cdev = to_clk_device(hw); | |
108 | u32 div = readl(cdev->div_reg) & cdev->div_mask; | |
109 | ||
110 | /* Special case for SDMMC devices */ | |
111 | if ((cdev->div_mask == 0x3F) && (div & BIT(5))) | |
112 | div = 64 * (div & 0x1f); | |
113 | ||
114 | /* div == 0 is actually the highest divisor */ | |
115 | if (div == 0) | |
116 | div = (cdev->div_mask + 1); | |
117 | ||
118 | return parent_rate / div; | |
119 | } | |
120 | ||
121 | static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, | |
122 | unsigned long *prate) | |
123 | { | |
973e1d1d | 124 | struct clk_device *cdev = to_clk_device(hw); |
58eb5a67 TP |
125 | u32 divisor; |
126 | ||
127 | if (rate == 0) | |
128 | return 0; | |
129 | ||
130 | divisor = *prate / rate; | |
85814d69 | 131 | |
72480014 TP |
132 | /* If prate / rate would be decimal, incr the divisor */ |
133 | if (rate * divisor < *prate) | |
134 | divisor++; | |
135 | ||
973e1d1d TP |
136 | /* |
137 | * If this is a request for SDMMC we have to adjust the divisor | |
138 | * when >31 to use the fixed predivisor | |
139 | */ | |
140 | if ((cdev->div_mask == 0x3F) && (divisor > 31)) { | |
141 | divisor = 64 * ((divisor / 64) + 1); | |
142 | } | |
143 | ||
85814d69 TP |
144 | return *prate / divisor; |
145 | } | |
146 | ||
147 | static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, | |
148 | unsigned long parent_rate) | |
149 | { | |
150 | struct clk_device *cdev = to_clk_device(hw); | |
58eb5a67 | 151 | u32 divisor; |
85814d69 TP |
152 | unsigned long flags = 0; |
153 | ||
58eb5a67 TP |
154 | if (rate == 0) |
155 | return 0; | |
156 | ||
157 | divisor = parent_rate / rate; | |
158 | ||
72480014 | 159 | /* If prate / rate would be decimal, incr the divisor */ |
d6d1053a | 160 | if (rate * divisor < parent_rate) |
72480014 TP |
161 | divisor++; |
162 | ||
85814d69 TP |
163 | if (divisor == cdev->div_mask + 1) |
164 | divisor = 0; | |
165 | ||
973e1d1d TP |
166 | /* SDMMC mask may need to be corrected before testing if its valid */ |
167 | if ((cdev->div_mask == 0x3F) && (divisor > 31)) { | |
168 | /* | |
169 | * Bit 5 is a fixed /64 predivisor. If the requested divisor | |
170 | * is >31 then correct for the fixed divisor being required. | |
171 | */ | |
172 | divisor = 0x20 + (divisor / 64); | |
173 | } | |
174 | ||
85814d69 TP |
175 | if (divisor > cdev->div_mask) { |
176 | pr_err("%s: invalid divisor for clock\n", __func__); | |
177 | return -EINVAL; | |
178 | } | |
179 | ||
180 | spin_lock_irqsave(cdev->lock, flags); | |
181 | ||
182 | vt8500_pmc_wait_busy(); | |
183 | writel(divisor, cdev->div_reg); | |
184 | vt8500_pmc_wait_busy(); | |
185 | ||
419e321d | 186 | spin_unlock_irqrestore(cdev->lock, flags); |
85814d69 TP |
187 | |
188 | return 0; | |
189 | } | |
190 | ||
191 | ||
192 | static const struct clk_ops vt8500_gated_clk_ops = { | |
193 | .enable = vt8500_dclk_enable, | |
194 | .disable = vt8500_dclk_disable, | |
195 | .is_enabled = vt8500_dclk_is_enabled, | |
196 | }; | |
197 | ||
198 | static const struct clk_ops vt8500_divisor_clk_ops = { | |
199 | .round_rate = vt8500_dclk_round_rate, | |
200 | .set_rate = vt8500_dclk_set_rate, | |
201 | .recalc_rate = vt8500_dclk_recalc_rate, | |
202 | }; | |
203 | ||
204 | static const struct clk_ops vt8500_gated_divisor_clk_ops = { | |
205 | .enable = vt8500_dclk_enable, | |
206 | .disable = vt8500_dclk_disable, | |
207 | .is_enabled = vt8500_dclk_is_enabled, | |
208 | .round_rate = vt8500_dclk_round_rate, | |
209 | .set_rate = vt8500_dclk_set_rate, | |
210 | .recalc_rate = vt8500_dclk_recalc_rate, | |
211 | }; | |
212 | ||
213 | #define CLK_INIT_GATED BIT(0) | |
214 | #define CLK_INIT_DIVISOR BIT(1) | |
215 | #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED) | |
216 | ||
217 | static __init void vtwm_device_clk_init(struct device_node *node) | |
218 | { | |
219 | u32 en_reg, div_reg; | |
220 | struct clk *clk; | |
221 | struct clk_device *dev_clk; | |
222 | const char *clk_name = node->name; | |
223 | const char *parent_name; | |
224 | struct clk_init_data init; | |
225 | int rc; | |
226 | int clk_init_flags = 0; | |
227 | ||
228 | dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL); | |
229 | if (WARN_ON(!dev_clk)) | |
230 | return; | |
231 | ||
232 | dev_clk->lock = &_lock; | |
233 | ||
234 | rc = of_property_read_u32(node, "enable-reg", &en_reg); | |
235 | if (!rc) { | |
236 | dev_clk->en_reg = pmc_base + en_reg; | |
237 | rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit); | |
238 | if (rc) { | |
239 | pr_err("%s: enable-bit property required for gated clock\n", | |
240 | __func__); | |
241 | return; | |
242 | } | |
243 | clk_init_flags |= CLK_INIT_GATED; | |
244 | } | |
245 | ||
246 | rc = of_property_read_u32(node, "divisor-reg", &div_reg); | |
247 | if (!rc) { | |
248 | dev_clk->div_reg = pmc_base + div_reg; | |
249 | /* | |
250 | * use 0x1f as the default mask since it covers | |
251 | * almost all the clocks and reduces dts properties | |
252 | */ | |
253 | dev_clk->div_mask = 0x1f; | |
254 | ||
255 | of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); | |
256 | clk_init_flags |= CLK_INIT_DIVISOR; | |
257 | } | |
258 | ||
259 | of_property_read_string(node, "clock-output-names", &clk_name); | |
260 | ||
261 | switch (clk_init_flags) { | |
262 | case CLK_INIT_GATED: | |
263 | init.ops = &vt8500_gated_clk_ops; | |
264 | break; | |
265 | case CLK_INIT_DIVISOR: | |
266 | init.ops = &vt8500_divisor_clk_ops; | |
267 | break; | |
268 | case CLK_INIT_GATED_DIVISOR: | |
269 | init.ops = &vt8500_gated_divisor_clk_ops; | |
270 | break; | |
271 | default: | |
272 | pr_err("%s: Invalid clock description in device tree\n", | |
273 | __func__); | |
274 | kfree(dev_clk); | |
275 | return; | |
276 | } | |
277 | ||
278 | init.name = clk_name; | |
279 | init.flags = 0; | |
280 | parent_name = of_clk_get_parent_name(node, 0); | |
281 | init.parent_names = &parent_name; | |
282 | init.num_parents = 1; | |
283 | ||
284 | dev_clk->hw.init = &init; | |
285 | ||
286 | clk = clk_register(NULL, &dev_clk->hw); | |
287 | if (WARN_ON(IS_ERR(clk))) { | |
288 | kfree(dev_clk); | |
289 | return; | |
290 | } | |
291 | rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
292 | clk_register_clkdev(clk, clk_name, NULL); | |
293 | } | |
5b6e0adb | 294 | CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init); |
85814d69 TP |
295 | |
296 | /* PLL clock related functions */ | |
297 | ||
298 | #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) | |
299 | ||
300 | /* Helper macros for PLL_VT8500 */ | |
301 | #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1) | |
302 | #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2) | |
303 | ||
304 | #define VT8500_BITS_TO_FREQ(r, m, d) \ | |
305 | ((r / d) * m) | |
306 | ||
307 | #define VT8500_BITS_TO_VAL(m, d) \ | |
308 | ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F)) | |
309 | ||
310 | /* Helper macros for PLL_WM8650 */ | |
311 | #define WM8650_PLL_MUL(x) (x & 0x3FF) | |
312 | #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3))) | |
313 | ||
314 | #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \ | |
315 | (r * m / (d1 * (1 << d2))) | |
316 | ||
317 | #define WM8650_BITS_TO_VAL(m, d1, d2) \ | |
318 | ((d2 << 13) | (d1 << 10) | (m & 0x3FF)) | |
319 | ||
abb165a8 TP |
320 | /* Helper macros for PLL_WM8750 */ |
321 | #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1) | |
322 | #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7))) | |
323 | ||
324 | #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \ | |
325 | (r * (m+1) / ((d1+1) * (1 << d2))) | |
326 | ||
327 | #define WM8750_BITS_TO_VAL(f, m, d1, d2) \ | |
328 | ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2) | |
329 | ||
85814d69 TP |
330 | |
331 | static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, | |
332 | u32 *multiplier, u32 *prediv) | |
333 | { | |
334 | unsigned long tclk; | |
335 | ||
336 | /* sanity check */ | |
337 | if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { | |
338 | pr_err("%s: requested rate out of range\n", __func__); | |
339 | *multiplier = 0; | |
340 | *prediv = 1; | |
341 | return; | |
342 | } | |
343 | if (rate <= parent_rate * 31) | |
344 | /* use the prediv to double the resolution */ | |
345 | *prediv = 2; | |
346 | else | |
347 | *prediv = 1; | |
348 | ||
349 | *multiplier = rate / (parent_rate / *prediv); | |
350 | tclk = (parent_rate / *prediv) * *multiplier; | |
351 | ||
352 | if (tclk != rate) | |
353 | pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, | |
354 | rate, tclk); | |
355 | } | |
356 | ||
357 | static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate, | |
358 | u32 *multiplier, u32 *divisor1, u32 *divisor2) | |
359 | { | |
360 | u32 mul, div1, div2; | |
361 | u32 best_mul, best_div1, best_div2; | |
362 | unsigned long tclk, rate_err, best_err; | |
363 | ||
364 | best_err = (unsigned long)-1; | |
365 | ||
366 | /* Find the closest match (lower or equal to requested) */ | |
367 | for (div1 = 5; div1 >= 3; div1--) | |
368 | for (div2 = 3; div2 >= 0; div2--) | |
369 | for (mul = 3; mul <= 1023; mul++) { | |
370 | tclk = parent_rate * mul / (div1 * (1 << div2)); | |
371 | if (tclk > rate) | |
372 | continue; | |
373 | /* error will always be +ve */ | |
374 | rate_err = rate - tclk; | |
375 | if (rate_err == 0) { | |
376 | *multiplier = mul; | |
377 | *divisor1 = div1; | |
378 | *divisor2 = div2; | |
379 | return; | |
380 | } | |
381 | ||
382 | if (rate_err < best_err) { | |
383 | best_err = rate_err; | |
384 | best_mul = mul; | |
385 | best_div1 = div1; | |
386 | best_div2 = div2; | |
387 | } | |
388 | } | |
389 | ||
390 | /* if we got here, it wasn't an exact match */ | |
391 | pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, | |
392 | rate - best_err); | |
35a5db55 TP |
393 | *multiplier = best_mul; |
394 | *divisor1 = best_div1; | |
395 | *divisor2 = best_div2; | |
85814d69 TP |
396 | } |
397 | ||
abb165a8 TP |
398 | static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1) |
399 | { | |
400 | /* calculate frequency (MHz) after pre-divisor */ | |
401 | u32 freq = (parent_rate / 1000000) / (divisor1 + 1); | |
402 | ||
403 | if ((freq < 10) || (freq > 200)) | |
404 | pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", | |
405 | __func__, freq); | |
406 | ||
407 | if (freq >= 166) | |
408 | return 7; | |
409 | else if (freq >= 104) | |
410 | return 6; | |
411 | else if (freq >= 65) | |
412 | return 5; | |
413 | else if (freq >= 42) | |
414 | return 4; | |
415 | else if (freq >= 26) | |
416 | return 3; | |
417 | else if (freq >= 16) | |
418 | return 2; | |
419 | else if (freq >= 10) | |
420 | return 1; | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate, | |
426 | u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2) | |
427 | { | |
428 | u32 mul, div1, div2; | |
429 | u32 best_mul, best_div1, best_div2; | |
430 | unsigned long tclk, rate_err, best_err; | |
431 | ||
432 | best_err = (unsigned long)-1; | |
433 | ||
434 | /* Find the closest match (lower or equal to requested) */ | |
435 | for (div1 = 1; div1 >= 0; div1--) | |
436 | for (div2 = 7; div2 >= 0; div2--) | |
437 | for (mul = 0; mul <= 255; mul++) { | |
438 | tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); | |
439 | if (tclk > rate) | |
440 | continue; | |
441 | /* error will always be +ve */ | |
442 | rate_err = rate - tclk; | |
443 | if (rate_err == 0) { | |
444 | *filter = wm8750_get_filter(parent_rate, div1); | |
445 | *multiplier = mul; | |
446 | *divisor1 = div1; | |
447 | *divisor2 = div2; | |
448 | return; | |
449 | } | |
450 | ||
451 | if (rate_err < best_err) { | |
452 | best_err = rate_err; | |
453 | best_mul = mul; | |
454 | best_div1 = div1; | |
455 | best_div2 = div2; | |
456 | } | |
457 | } | |
458 | ||
459 | /* if we got here, it wasn't an exact match */ | |
460 | pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, | |
461 | rate - best_err); | |
462 | ||
463 | *filter = wm8750_get_filter(parent_rate, best_div1); | |
464 | *multiplier = best_mul; | |
465 | *divisor1 = best_div1; | |
466 | *divisor2 = best_div2; | |
467 | } | |
468 | ||
85814d69 TP |
469 | static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
470 | unsigned long parent_rate) | |
471 | { | |
472 | struct clk_pll *pll = to_clk_pll(hw); | |
abb165a8 | 473 | u32 filter, mul, div1, div2; |
85814d69 TP |
474 | u32 pll_val; |
475 | unsigned long flags = 0; | |
476 | ||
477 | /* sanity check */ | |
478 | ||
479 | switch (pll->type) { | |
480 | case PLL_TYPE_VT8500: | |
481 | vt8500_find_pll_bits(rate, parent_rate, &mul, &div1); | |
482 | pll_val = VT8500_BITS_TO_VAL(mul, div1); | |
483 | break; | |
484 | case PLL_TYPE_WM8650: | |
485 | wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); | |
486 | pll_val = WM8650_BITS_TO_VAL(mul, div1, div2); | |
487 | break; | |
abb165a8 TP |
488 | case PLL_TYPE_WM8750: |
489 | wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2); | |
490 | pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2); | |
bdca21ec | 491 | break; |
85814d69 TP |
492 | default: |
493 | pr_err("%s: invalid pll type\n", __func__); | |
494 | return 0; | |
495 | } | |
496 | ||
497 | spin_lock_irqsave(pll->lock, flags); | |
498 | ||
499 | vt8500_pmc_wait_busy(); | |
500 | writel(pll_val, pll->reg); | |
501 | vt8500_pmc_wait_busy(); | |
502 | ||
503 | spin_unlock_irqrestore(pll->lock, flags); | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
508 | static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, | |
509 | unsigned long *prate) | |
510 | { | |
511 | struct clk_pll *pll = to_clk_pll(hw); | |
abb165a8 | 512 | u32 filter, mul, div1, div2; |
85814d69 TP |
513 | long round_rate; |
514 | ||
515 | switch (pll->type) { | |
516 | case PLL_TYPE_VT8500: | |
517 | vt8500_find_pll_bits(rate, *prate, &mul, &div1); | |
518 | round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1); | |
519 | break; | |
520 | case PLL_TYPE_WM8650: | |
521 | wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); | |
522 | round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); | |
523 | break; | |
abb165a8 TP |
524 | case PLL_TYPE_WM8750: |
525 | wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); | |
526 | round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); | |
bdca21ec | 527 | break; |
85814d69 TP |
528 | default: |
529 | round_rate = 0; | |
530 | } | |
531 | ||
532 | return round_rate; | |
533 | } | |
534 | ||
535 | static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw, | |
536 | unsigned long parent_rate) | |
537 | { | |
538 | struct clk_pll *pll = to_clk_pll(hw); | |
539 | u32 pll_val = readl(pll->reg); | |
540 | unsigned long pll_freq; | |
541 | ||
542 | switch (pll->type) { | |
543 | case PLL_TYPE_VT8500: | |
544 | pll_freq = parent_rate * VT8500_PLL_MUL(pll_val); | |
545 | pll_freq /= VT8500_PLL_DIV(pll_val); | |
546 | break; | |
547 | case PLL_TYPE_WM8650: | |
548 | pll_freq = parent_rate * WM8650_PLL_MUL(pll_val); | |
549 | pll_freq /= WM8650_PLL_DIV(pll_val); | |
550 | break; | |
abb165a8 TP |
551 | case PLL_TYPE_WM8750: |
552 | pll_freq = parent_rate * WM8750_PLL_MUL(pll_val); | |
553 | pll_freq /= WM8750_PLL_DIV(pll_val); | |
554 | break; | |
85814d69 TP |
555 | default: |
556 | pll_freq = 0; | |
557 | } | |
558 | ||
559 | return pll_freq; | |
560 | } | |
561 | ||
562 | const struct clk_ops vtwm_pll_ops = { | |
563 | .round_rate = vtwm_pll_round_rate, | |
564 | .set_rate = vtwm_pll_set_rate, | |
565 | .recalc_rate = vtwm_pll_recalc_rate, | |
566 | }; | |
567 | ||
568 | static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type) | |
569 | { | |
570 | u32 reg; | |
571 | struct clk *clk; | |
572 | struct clk_pll *pll_clk; | |
573 | const char *clk_name = node->name; | |
574 | const char *parent_name; | |
575 | struct clk_init_data init; | |
576 | int rc; | |
577 | ||
578 | rc = of_property_read_u32(node, "reg", ®); | |
579 | if (WARN_ON(rc)) | |
580 | return; | |
581 | ||
582 | pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); | |
583 | if (WARN_ON(!pll_clk)) | |
584 | return; | |
585 | ||
586 | pll_clk->reg = pmc_base + reg; | |
587 | pll_clk->lock = &_lock; | |
588 | pll_clk->type = pll_type; | |
589 | ||
590 | of_property_read_string(node, "clock-output-names", &clk_name); | |
591 | ||
592 | init.name = clk_name; | |
593 | init.ops = &vtwm_pll_ops; | |
594 | init.flags = 0; | |
595 | parent_name = of_clk_get_parent_name(node, 0); | |
596 | init.parent_names = &parent_name; | |
597 | init.num_parents = 1; | |
598 | ||
599 | pll_clk->hw.init = &init; | |
600 | ||
601 | clk = clk_register(NULL, &pll_clk->hw); | |
602 | if (WARN_ON(IS_ERR(clk))) { | |
603 | kfree(pll_clk); | |
604 | return; | |
605 | } | |
606 | rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
607 | clk_register_clkdev(clk, clk_name, NULL); | |
608 | } | |
609 | ||
610 | ||
611 | /* Wrappers for initialization functions */ | |
612 | ||
613 | static void __init vt8500_pll_init(struct device_node *node) | |
614 | { | |
615 | vtwm_pll_clk_init(node, PLL_TYPE_VT8500); | |
616 | } | |
5b6e0adb | 617 | CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init); |
85814d69 TP |
618 | |
619 | static void __init wm8650_pll_init(struct device_node *node) | |
620 | { | |
621 | vtwm_pll_clk_init(node, PLL_TYPE_WM8650); | |
622 | } | |
5b6e0adb | 623 | CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init); |
85814d69 | 624 | |
abb165a8 TP |
625 | static void __init wm8750_pll_init(struct device_node *node) |
626 | { | |
627 | vtwm_pll_clk_init(node, PLL_TYPE_WM8750); | |
628 | } | |
5b6e0adb | 629 | CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init); |
85814d69 TP |
630 | |
631 | void __init vtwm_clk_init(void __iomem *base) | |
632 | { | |
633 | if (!base) | |
634 | return; | |
635 | ||
636 | pmc_base = base; | |
637 | ||
5b6e0adb | 638 | of_clk_init(NULL); |
85814d69 | 639 | } |