i40e: Implement ndo_features_check()
[deliverable/linux.git] / drivers / clk / clk.c
CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
b09d6d99 12#include <linux/clk-provider.h>
86be408b 13#include <linux/clk/clk-conf.h>
b2476490
MT
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/spinlock.h>
17#include <linux/err.h>
18#include <linux/list.h>
19#include <linux/slab.h>
766e6a4e 20#include <linux/of.h>
46c8773a 21#include <linux/device.h>
f2f6c255 22#include <linux/init.h>
533ddeb1 23#include <linux/sched.h>
562ef0b0 24#include <linux/clkdev.h>
b2476490 25
d6782c26
SN
26#include "clk.h"
27
b2476490
MT
28static DEFINE_SPINLOCK(enable_lock);
29static DEFINE_MUTEX(prepare_lock);
30
533ddeb1
MT
31static struct task_struct *prepare_owner;
32static struct task_struct *enable_owner;
33
34static int prepare_refcnt;
35static int enable_refcnt;
36
b2476490
MT
37static HLIST_HEAD(clk_root_list);
38static HLIST_HEAD(clk_orphan_list);
39static LIST_HEAD(clk_notifier_list);
40
b09d6d99
MT
41/*** private data structures ***/
42
43struct clk_core {
44 const char *name;
45 const struct clk_ops *ops;
46 struct clk_hw *hw;
47 struct module *owner;
48 struct clk_core *parent;
49 const char **parent_names;
50 struct clk_core **parents;
51 u8 num_parents;
52 u8 new_parent_index;
53 unsigned long rate;
1c8e6004 54 unsigned long req_rate;
b09d6d99
MT
55 unsigned long new_rate;
56 struct clk_core *new_parent;
57 struct clk_core *new_child;
58 unsigned long flags;
59 unsigned int enable_count;
60 unsigned int prepare_count;
61 unsigned long accuracy;
62 int phase;
63 struct hlist_head children;
64 struct hlist_node child_node;
1c8e6004 65 struct hlist_head clks;
b09d6d99
MT
66 unsigned int notifier_count;
67#ifdef CONFIG_DEBUG_FS
68 struct dentry *dentry;
8c9a8a8f 69 struct hlist_node debug_node;
b09d6d99
MT
70#endif
71 struct kref ref;
72};
73
dfc202ea
SB
74#define CREATE_TRACE_POINTS
75#include <trace/events/clk.h>
76
b09d6d99
MT
77struct clk {
78 struct clk_core *core;
79 const char *dev_id;
80 const char *con_id;
1c8e6004
TV
81 unsigned long min_rate;
82 unsigned long max_rate;
50595f8b 83 struct hlist_node clks_node;
b09d6d99
MT
84};
85
eab89f69
MT
86/*** locking ***/
87static void clk_prepare_lock(void)
88{
533ddeb1
MT
89 if (!mutex_trylock(&prepare_lock)) {
90 if (prepare_owner == current) {
91 prepare_refcnt++;
92 return;
93 }
94 mutex_lock(&prepare_lock);
95 }
96 WARN_ON_ONCE(prepare_owner != NULL);
97 WARN_ON_ONCE(prepare_refcnt != 0);
98 prepare_owner = current;
99 prepare_refcnt = 1;
eab89f69
MT
100}
101
102static void clk_prepare_unlock(void)
103{
533ddeb1
MT
104 WARN_ON_ONCE(prepare_owner != current);
105 WARN_ON_ONCE(prepare_refcnt == 0);
106
107 if (--prepare_refcnt)
108 return;
109 prepare_owner = NULL;
eab89f69
MT
110 mutex_unlock(&prepare_lock);
111}
112
113static unsigned long clk_enable_lock(void)
114{
115 unsigned long flags;
533ddeb1
MT
116
117 if (!spin_trylock_irqsave(&enable_lock, flags)) {
118 if (enable_owner == current) {
119 enable_refcnt++;
120 return flags;
121 }
122 spin_lock_irqsave(&enable_lock, flags);
123 }
124 WARN_ON_ONCE(enable_owner != NULL);
125 WARN_ON_ONCE(enable_refcnt != 0);
126 enable_owner = current;
127 enable_refcnt = 1;
eab89f69
MT
128 return flags;
129}
130
131static void clk_enable_unlock(unsigned long flags)
132{
533ddeb1
MT
133 WARN_ON_ONCE(enable_owner != current);
134 WARN_ON_ONCE(enable_refcnt == 0);
135
136 if (--enable_refcnt)
137 return;
138 enable_owner = NULL;
eab89f69
MT
139 spin_unlock_irqrestore(&enable_lock, flags);
140}
141
4dff95dc
SB
142static bool clk_core_is_prepared(struct clk_core *core)
143{
144 /*
145 * .is_prepared is optional for clocks that can prepare
146 * fall back to software usage counter if it is missing
147 */
148 if (!core->ops->is_prepared)
149 return core->prepare_count;
b2476490 150
4dff95dc
SB
151 return core->ops->is_prepared(core->hw);
152}
b2476490 153
4dff95dc
SB
154static bool clk_core_is_enabled(struct clk_core *core)
155{
156 /*
157 * .is_enabled is only mandatory for clocks that gate
158 * fall back to software usage counter if .is_enabled is missing
159 */
160 if (!core->ops->is_enabled)
161 return core->enable_count;
6b44c854 162
4dff95dc
SB
163 return core->ops->is_enabled(core->hw);
164}
6b44c854 165
4dff95dc 166static void clk_unprepare_unused_subtree(struct clk_core *core)
1af599df 167{
4dff95dc
SB
168 struct clk_core *child;
169
170 lockdep_assert_held(&prepare_lock);
171
172 hlist_for_each_entry(child, &core->children, child_node)
173 clk_unprepare_unused_subtree(child);
174
175 if (core->prepare_count)
1af599df
PG
176 return;
177
4dff95dc
SB
178 if (core->flags & CLK_IGNORE_UNUSED)
179 return;
180
181 if (clk_core_is_prepared(core)) {
182 trace_clk_unprepare(core);
183 if (core->ops->unprepare_unused)
184 core->ops->unprepare_unused(core->hw);
185 else if (core->ops->unprepare)
186 core->ops->unprepare(core->hw);
187 trace_clk_unprepare_complete(core);
188 }
1af599df
PG
189}
190
4dff95dc 191static void clk_disable_unused_subtree(struct clk_core *core)
1af599df 192{
035a61c3 193 struct clk_core *child;
4dff95dc 194 unsigned long flags;
1af599df 195
4dff95dc 196 lockdep_assert_held(&prepare_lock);
1af599df 197
4dff95dc
SB
198 hlist_for_each_entry(child, &core->children, child_node)
199 clk_disable_unused_subtree(child);
1af599df 200
4dff95dc
SB
201 flags = clk_enable_lock();
202
203 if (core->enable_count)
204 goto unlock_out;
205
206 if (core->flags & CLK_IGNORE_UNUSED)
207 goto unlock_out;
208
209 /*
210 * some gate clocks have special needs during the disable-unused
211 * sequence. call .disable_unused if available, otherwise fall
212 * back to .disable
213 */
214 if (clk_core_is_enabled(core)) {
215 trace_clk_disable(core);
216 if (core->ops->disable_unused)
217 core->ops->disable_unused(core->hw);
218 else if (core->ops->disable)
219 core->ops->disable(core->hw);
220 trace_clk_disable_complete(core);
221 }
222
223unlock_out:
224 clk_enable_unlock(flags);
1af599df
PG
225}
226
4dff95dc
SB
227static bool clk_ignore_unused;
228static int __init clk_ignore_unused_setup(char *__unused)
1af599df 229{
4dff95dc
SB
230 clk_ignore_unused = true;
231 return 1;
232}
233__setup("clk_ignore_unused", clk_ignore_unused_setup);
1af599df 234
4dff95dc
SB
235static int clk_disable_unused(void)
236{
237 struct clk_core *core;
238
239 if (clk_ignore_unused) {
240 pr_warn("clk: Not disabling unused clocks\n");
241 return 0;
242 }
1af599df 243
eab89f69 244 clk_prepare_lock();
1af599df 245
4dff95dc
SB
246 hlist_for_each_entry(core, &clk_root_list, child_node)
247 clk_disable_unused_subtree(core);
248
249 hlist_for_each_entry(core, &clk_orphan_list, child_node)
250 clk_disable_unused_subtree(core);
251
252 hlist_for_each_entry(core, &clk_root_list, child_node)
253 clk_unprepare_unused_subtree(core);
254
255 hlist_for_each_entry(core, &clk_orphan_list, child_node)
256 clk_unprepare_unused_subtree(core);
1af599df 257
eab89f69 258 clk_prepare_unlock();
1af599df
PG
259
260 return 0;
261}
4dff95dc 262late_initcall_sync(clk_disable_unused);
1af599df 263
4dff95dc 264/*** helper functions ***/
1af599df 265
4dff95dc 266const char *__clk_get_name(struct clk *clk)
1af599df 267{
4dff95dc 268 return !clk ? NULL : clk->core->name;
1af599df 269}
4dff95dc 270EXPORT_SYMBOL_GPL(__clk_get_name);
1af599df 271
4dff95dc
SB
272struct clk_hw *__clk_get_hw(struct clk *clk)
273{
274 return !clk ? NULL : clk->core->hw;
275}
276EXPORT_SYMBOL_GPL(__clk_get_hw);
1af599df 277
4dff95dc 278u8 __clk_get_num_parents(struct clk *clk)
bddca894 279{
4dff95dc
SB
280 return !clk ? 0 : clk->core->num_parents;
281}
282EXPORT_SYMBOL_GPL(__clk_get_num_parents);
bddca894 283
4dff95dc
SB
284struct clk *__clk_get_parent(struct clk *clk)
285{
286 if (!clk)
287 return NULL;
288
289 /* TODO: Create a per-user clk and change callers to call clk_put */
290 return !clk->core->parent ? NULL : clk->core->parent->hw->clk;
bddca894 291}
4dff95dc 292EXPORT_SYMBOL_GPL(__clk_get_parent);
bddca894 293
4dff95dc
SB
294static struct clk_core *__clk_lookup_subtree(const char *name,
295 struct clk_core *core)
bddca894 296{
035a61c3 297 struct clk_core *child;
4dff95dc 298 struct clk_core *ret;
bddca894 299
4dff95dc
SB
300 if (!strcmp(core->name, name))
301 return core;
bddca894 302
4dff95dc
SB
303 hlist_for_each_entry(child, &core->children, child_node) {
304 ret = __clk_lookup_subtree(name, child);
305 if (ret)
306 return ret;
bddca894
PG
307 }
308
4dff95dc 309 return NULL;
bddca894
PG
310}
311
4dff95dc 312static struct clk_core *clk_core_lookup(const char *name)
bddca894 313{
4dff95dc
SB
314 struct clk_core *root_clk;
315 struct clk_core *ret;
bddca894 316
4dff95dc
SB
317 if (!name)
318 return NULL;
bddca894 319
4dff95dc
SB
320 /* search the 'proper' clk tree first */
321 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
322 ret = __clk_lookup_subtree(name, root_clk);
323 if (ret)
324 return ret;
bddca894
PG
325 }
326
4dff95dc
SB
327 /* if not found, then search the orphan tree */
328 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
329 ret = __clk_lookup_subtree(name, root_clk);
330 if (ret)
331 return ret;
332 }
bddca894 333
4dff95dc 334 return NULL;
bddca894
PG
335}
336
4dff95dc
SB
337static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
338 u8 index)
bddca894 339{
4dff95dc
SB
340 if (!core || index >= core->num_parents)
341 return NULL;
342 else if (!core->parents)
343 return clk_core_lookup(core->parent_names[index]);
344 else if (!core->parents[index])
345 return core->parents[index] =
346 clk_core_lookup(core->parent_names[index]);
347 else
348 return core->parents[index];
bddca894
PG
349}
350
4dff95dc 351struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
b2476490 352{
4dff95dc 353 struct clk_core *parent;
b2476490 354
4dff95dc
SB
355 if (!clk)
356 return NULL;
b2476490 357
4dff95dc 358 parent = clk_core_get_parent_by_index(clk->core, index);
5279fc40 359
4dff95dc
SB
360 return !parent ? NULL : parent->hw->clk;
361}
362EXPORT_SYMBOL_GPL(clk_get_parent_by_index);
e59c5371 363
4dff95dc
SB
364unsigned int __clk_get_enable_count(struct clk *clk)
365{
366 return !clk ? 0 : clk->core->enable_count;
367}
b2476490 368
4dff95dc
SB
369static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
370{
371 unsigned long ret;
b2476490 372
4dff95dc
SB
373 if (!core) {
374 ret = 0;
375 goto out;
376 }
b2476490 377
4dff95dc 378 ret = core->rate;
b2476490 379
4dff95dc
SB
380 if (core->flags & CLK_IS_ROOT)
381 goto out;
c646cbf1 382
4dff95dc
SB
383 if (!core->parent)
384 ret = 0;
b2476490 385
b2476490
MT
386out:
387 return ret;
388}
389
4dff95dc 390unsigned long __clk_get_rate(struct clk *clk)
b2476490 391{
4dff95dc
SB
392 if (!clk)
393 return 0;
6314b679 394
4dff95dc
SB
395 return clk_core_get_rate_nolock(clk->core);
396}
397EXPORT_SYMBOL_GPL(__clk_get_rate);
b2476490 398
4dff95dc
SB
399static unsigned long __clk_get_accuracy(struct clk_core *core)
400{
401 if (!core)
402 return 0;
b2476490 403
4dff95dc 404 return core->accuracy;
b2476490
MT
405}
406
4dff95dc 407unsigned long __clk_get_flags(struct clk *clk)
fcb0ee6a 408{
4dff95dc 409 return !clk ? 0 : clk->core->flags;
fcb0ee6a 410}
4dff95dc 411EXPORT_SYMBOL_GPL(__clk_get_flags);
fcb0ee6a 412
4dff95dc 413bool __clk_is_prepared(struct clk *clk)
fb2b3c9f 414{
4dff95dc
SB
415 if (!clk)
416 return false;
fb2b3c9f 417
4dff95dc 418 return clk_core_is_prepared(clk->core);
fb2b3c9f 419}
fb2b3c9f 420
4dff95dc 421bool __clk_is_enabled(struct clk *clk)
b2476490 422{
4dff95dc
SB
423 if (!clk)
424 return false;
b2476490 425
4dff95dc
SB
426 return clk_core_is_enabled(clk->core);
427}
428EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 429
4dff95dc
SB
430static bool mux_is_better_rate(unsigned long rate, unsigned long now,
431 unsigned long best, unsigned long flags)
432{
433 if (flags & CLK_MUX_ROUND_CLOSEST)
434 return abs(now - rate) < abs(best - rate);
1af599df 435
4dff95dc
SB
436 return now <= rate && now > best;
437}
bddca894 438
4dff95dc
SB
439static long
440clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate,
441 unsigned long min_rate,
442 unsigned long max_rate,
443 unsigned long *best_parent_rate,
444 struct clk_hw **best_parent_p,
445 unsigned long flags)
446{
447 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
448 int i, num_parents;
449 unsigned long parent_rate, best = 0;
b2476490 450
4dff95dc
SB
451 /* if NO_REPARENT flag set, pass through to current parent */
452 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
453 parent = core->parent;
454 if (core->flags & CLK_SET_RATE_PARENT)
455 best = __clk_determine_rate(parent ? parent->hw : NULL,
456 rate, min_rate, max_rate);
457 else if (parent)
458 best = clk_core_get_rate_nolock(parent);
459 else
460 best = clk_core_get_rate_nolock(core);
461 goto out;
462 }
b2476490 463
4dff95dc
SB
464 /* find the parent that can provide the fastest rate <= rate */
465 num_parents = core->num_parents;
466 for (i = 0; i < num_parents; i++) {
467 parent = clk_core_get_parent_by_index(core, i);
468 if (!parent)
469 continue;
470 if (core->flags & CLK_SET_RATE_PARENT)
471 parent_rate = __clk_determine_rate(parent->hw, rate,
472 min_rate,
473 max_rate);
474 else
475 parent_rate = clk_core_get_rate_nolock(parent);
476 if (mux_is_better_rate(rate, parent_rate, best, flags)) {
477 best_parent = parent;
478 best = parent_rate;
479 }
480 }
b2476490 481
4dff95dc
SB
482out:
483 if (best_parent)
484 *best_parent_p = best_parent->hw;
485 *best_parent_rate = best;
b2476490 486
4dff95dc 487 return best;
b33d212f 488}
4dff95dc
SB
489
490struct clk *__clk_lookup(const char *name)
fcb0ee6a 491{
4dff95dc
SB
492 struct clk_core *core = clk_core_lookup(name);
493
494 return !core ? NULL : core->hw->clk;
fcb0ee6a 495}
b2476490 496
4dff95dc
SB
497static void clk_core_get_boundaries(struct clk_core *core,
498 unsigned long *min_rate,
499 unsigned long *max_rate)
1c155b3d 500{
4dff95dc 501 struct clk *clk_user;
1c155b3d 502
4dff95dc
SB
503 *min_rate = 0;
504 *max_rate = ULONG_MAX;
496eadf8 505
4dff95dc
SB
506 hlist_for_each_entry(clk_user, &core->clks, clks_node)
507 *min_rate = max(*min_rate, clk_user->min_rate);
1c155b3d 508
4dff95dc
SB
509 hlist_for_each_entry(clk_user, &core->clks, clks_node)
510 *max_rate = min(*max_rate, clk_user->max_rate);
511}
1c155b3d 512
4dff95dc
SB
513/*
514 * Helper for finding best parent to provide a given frequency. This can be used
515 * directly as a determine_rate callback (e.g. for a mux), or from a more
516 * complex clock that may combine a mux with other operations.
517 */
518long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
519 unsigned long min_rate,
520 unsigned long max_rate,
521 unsigned long *best_parent_rate,
522 struct clk_hw **best_parent_p)
523{
524 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
525 best_parent_rate,
526 best_parent_p, 0);
1c155b3d 527}
4dff95dc 528EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
1c155b3d 529
4dff95dc
SB
530long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
531 unsigned long min_rate,
532 unsigned long max_rate,
533 unsigned long *best_parent_rate,
534 struct clk_hw **best_parent_p)
b2476490 535{
4dff95dc
SB
536 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
537 best_parent_rate,
538 best_parent_p,
539 CLK_MUX_ROUND_CLOSEST);
540}
541EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
b2476490 542
4dff95dc 543/*** clk api ***/
496eadf8 544
4dff95dc
SB
545static void clk_core_unprepare(struct clk_core *core)
546{
a6334725
SB
547 lockdep_assert_held(&prepare_lock);
548
4dff95dc
SB
549 if (!core)
550 return;
b2476490 551
4dff95dc
SB
552 if (WARN_ON(core->prepare_count == 0))
553 return;
b2476490 554
4dff95dc
SB
555 if (--core->prepare_count > 0)
556 return;
b2476490 557
4dff95dc 558 WARN_ON(core->enable_count > 0);
b2476490 559
4dff95dc 560 trace_clk_unprepare(core);
b2476490 561
4dff95dc
SB
562 if (core->ops->unprepare)
563 core->ops->unprepare(core->hw);
564
565 trace_clk_unprepare_complete(core);
566 clk_core_unprepare(core->parent);
b2476490
MT
567}
568
4dff95dc
SB
569/**
570 * clk_unprepare - undo preparation of a clock source
571 * @clk: the clk being unprepared
572 *
573 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
574 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
575 * if the operation may sleep. One example is a clk which is accessed over
576 * I2c. In the complex case a clk gate operation may require a fast and a slow
577 * part. It is this reason that clk_unprepare and clk_disable are not mutually
578 * exclusive. In fact clk_disable must be called before clk_unprepare.
579 */
580void clk_unprepare(struct clk *clk)
1e435256 581{
4dff95dc
SB
582 if (IS_ERR_OR_NULL(clk))
583 return;
584
585 clk_prepare_lock();
586 clk_core_unprepare(clk->core);
587 clk_prepare_unlock();
1e435256 588}
4dff95dc 589EXPORT_SYMBOL_GPL(clk_unprepare);
1e435256 590
4dff95dc 591static int clk_core_prepare(struct clk_core *core)
b2476490 592{
4dff95dc 593 int ret = 0;
b2476490 594
a6334725
SB
595 lockdep_assert_held(&prepare_lock);
596
4dff95dc 597 if (!core)
1e435256 598 return 0;
1e435256 599
4dff95dc
SB
600 if (core->prepare_count == 0) {
601 ret = clk_core_prepare(core->parent);
602 if (ret)
603 return ret;
b2476490 604
4dff95dc 605 trace_clk_prepare(core);
b2476490 606
4dff95dc
SB
607 if (core->ops->prepare)
608 ret = core->ops->prepare(core->hw);
b2476490 609
4dff95dc 610 trace_clk_prepare_complete(core);
1c155b3d 611
4dff95dc
SB
612 if (ret) {
613 clk_core_unprepare(core->parent);
614 return ret;
615 }
616 }
1c155b3d 617
4dff95dc 618 core->prepare_count++;
b2476490
MT
619
620 return 0;
621}
b2476490 622
4dff95dc
SB
623/**
624 * clk_prepare - prepare a clock source
625 * @clk: the clk being prepared
626 *
627 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
628 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
629 * operation may sleep. One example is a clk which is accessed over I2c. In
630 * the complex case a clk ungate operation may require a fast and a slow part.
631 * It is this reason that clk_prepare and clk_enable are not mutually
632 * exclusive. In fact clk_prepare must be called before clk_enable.
633 * Returns 0 on success, -EERROR otherwise.
634 */
635int clk_prepare(struct clk *clk)
b2476490 636{
4dff95dc 637 int ret;
b2476490 638
4dff95dc
SB
639 if (!clk)
640 return 0;
b2476490 641
4dff95dc
SB
642 clk_prepare_lock();
643 ret = clk_core_prepare(clk->core);
644 clk_prepare_unlock();
645
646 return ret;
b2476490 647}
4dff95dc 648EXPORT_SYMBOL_GPL(clk_prepare);
b2476490 649
4dff95dc 650static void clk_core_disable(struct clk_core *core)
b2476490 651{
a6334725
SB
652 lockdep_assert_held(&enable_lock);
653
4dff95dc
SB
654 if (!core)
655 return;
035a61c3 656
4dff95dc
SB
657 if (WARN_ON(core->enable_count == 0))
658 return;
b2476490 659
4dff95dc
SB
660 if (--core->enable_count > 0)
661 return;
035a61c3 662
4dff95dc 663 trace_clk_disable(core);
035a61c3 664
4dff95dc
SB
665 if (core->ops->disable)
666 core->ops->disable(core->hw);
035a61c3 667
4dff95dc 668 trace_clk_disable_complete(core);
035a61c3 669
4dff95dc 670 clk_core_disable(core->parent);
035a61c3 671}
7ef3dcc8 672
4dff95dc
SB
673/**
674 * clk_disable - gate a clock
675 * @clk: the clk being gated
676 *
677 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
678 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
679 * clk if the operation is fast and will never sleep. One example is a
680 * SoC-internal clk which is controlled via simple register writes. In the
681 * complex case a clk gate operation may require a fast and a slow part. It is
682 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
683 * In fact clk_disable must be called before clk_unprepare.
684 */
685void clk_disable(struct clk *clk)
b2476490 686{
4dff95dc
SB
687 unsigned long flags;
688
689 if (IS_ERR_OR_NULL(clk))
690 return;
691
692 flags = clk_enable_lock();
693 clk_core_disable(clk->core);
694 clk_enable_unlock(flags);
b2476490 695}
4dff95dc 696EXPORT_SYMBOL_GPL(clk_disable);
b2476490 697
4dff95dc 698static int clk_core_enable(struct clk_core *core)
b2476490 699{
4dff95dc 700 int ret = 0;
b2476490 701
a6334725
SB
702 lockdep_assert_held(&enable_lock);
703
4dff95dc
SB
704 if (!core)
705 return 0;
b2476490 706
4dff95dc
SB
707 if (WARN_ON(core->prepare_count == 0))
708 return -ESHUTDOWN;
b2476490 709
4dff95dc
SB
710 if (core->enable_count == 0) {
711 ret = clk_core_enable(core->parent);
b2476490 712
4dff95dc
SB
713 if (ret)
714 return ret;
b2476490 715
4dff95dc 716 trace_clk_enable(core);
035a61c3 717
4dff95dc
SB
718 if (core->ops->enable)
719 ret = core->ops->enable(core->hw);
035a61c3 720
4dff95dc
SB
721 trace_clk_enable_complete(core);
722
723 if (ret) {
724 clk_core_disable(core->parent);
725 return ret;
726 }
727 }
728
729 core->enable_count++;
730 return 0;
035a61c3 731}
b2476490 732
4dff95dc
SB
733/**
734 * clk_enable - ungate a clock
735 * @clk: the clk being ungated
736 *
737 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
738 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
739 * if the operation will never sleep. One example is a SoC-internal clk which
740 * is controlled via simple register writes. In the complex case a clk ungate
741 * operation may require a fast and a slow part. It is this reason that
742 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
743 * must be called before clk_enable. Returns 0 on success, -EERROR
744 * otherwise.
745 */
746int clk_enable(struct clk *clk)
5279fc40 747{
4dff95dc
SB
748 unsigned long flags;
749 int ret;
750
751 if (!clk)
5279fc40
BB
752 return 0;
753
4dff95dc
SB
754 flags = clk_enable_lock();
755 ret = clk_core_enable(clk->core);
756 clk_enable_unlock(flags);
5279fc40 757
4dff95dc 758 return ret;
b2476490 759}
4dff95dc 760EXPORT_SYMBOL_GPL(clk_enable);
b2476490 761
4dff95dc
SB
762static unsigned long clk_core_round_rate_nolock(struct clk_core *core,
763 unsigned long rate,
764 unsigned long min_rate,
765 unsigned long max_rate)
3d6ee287 766{
4dff95dc
SB
767 unsigned long parent_rate = 0;
768 struct clk_core *parent;
769 struct clk_hw *parent_hw;
770
771 lockdep_assert_held(&prepare_lock);
3d6ee287 772
d6968fca 773 if (!core)
4dff95dc 774 return 0;
3d6ee287 775
4dff95dc
SB
776 parent = core->parent;
777 if (parent)
778 parent_rate = parent->rate;
3d6ee287 779
4dff95dc
SB
780 if (core->ops->determine_rate) {
781 parent_hw = parent ? parent->hw : NULL;
782 return core->ops->determine_rate(core->hw, rate,
783 min_rate, max_rate,
784 &parent_rate, &parent_hw);
785 } else if (core->ops->round_rate)
786 return core->ops->round_rate(core->hw, rate, &parent_rate);
787 else if (core->flags & CLK_SET_RATE_PARENT)
788 return clk_core_round_rate_nolock(core->parent, rate, min_rate,
789 max_rate);
790 else
791 return core->rate;
3d6ee287
UH
792}
793
4dff95dc
SB
794/**
795 * __clk_determine_rate - get the closest rate actually supported by a clock
796 * @hw: determine the rate of this clock
797 * @rate: target rate
798 * @min_rate: returned rate must be greater than this rate
799 * @max_rate: returned rate must be less than this rate
800 *
6e5ab41b 801 * Useful for clk_ops such as .set_rate and .determine_rate.
4dff95dc
SB
802 */
803unsigned long __clk_determine_rate(struct clk_hw *hw,
804 unsigned long rate,
805 unsigned long min_rate,
806 unsigned long max_rate)
035a61c3 807{
4dff95dc
SB
808 if (!hw)
809 return 0;
035a61c3 810
4dff95dc 811 return clk_core_round_rate_nolock(hw->core, rate, min_rate, max_rate);
035a61c3 812}
4dff95dc 813EXPORT_SYMBOL_GPL(__clk_determine_rate);
035a61c3 814
4dff95dc
SB
815/**
816 * __clk_round_rate - round the given rate for a clk
817 * @clk: round the rate of this clock
818 * @rate: the rate which is to be rounded
819 *
6e5ab41b 820 * Useful for clk_ops such as .set_rate
4dff95dc
SB
821 */
822unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
b2476490 823{
4dff95dc
SB
824 unsigned long min_rate;
825 unsigned long max_rate;
b2476490 826
4dff95dc
SB
827 if (!clk)
828 return 0;
b2476490 829
4dff95dc 830 clk_core_get_boundaries(clk->core, &min_rate, &max_rate);
b2476490 831
4dff95dc 832 return clk_core_round_rate_nolock(clk->core, rate, min_rate, max_rate);
b2476490 833}
4dff95dc 834EXPORT_SYMBOL_GPL(__clk_round_rate);
035a61c3 835
4dff95dc
SB
836/**
837 * clk_round_rate - round the given rate for a clk
838 * @clk: the clk for which we are rounding a rate
839 * @rate: the rate which is to be rounded
840 *
841 * Takes in a rate as input and rounds it to a rate that the clk can actually
842 * use which is then returned. If clk doesn't support round_rate operation
843 * then the parent rate is returned.
844 */
845long clk_round_rate(struct clk *clk, unsigned long rate)
035a61c3 846{
4dff95dc
SB
847 unsigned long ret;
848
035a61c3 849 if (!clk)
4dff95dc 850 return 0;
035a61c3 851
4dff95dc
SB
852 clk_prepare_lock();
853 ret = __clk_round_rate(clk, rate);
854 clk_prepare_unlock();
855
856 return ret;
035a61c3 857}
4dff95dc 858EXPORT_SYMBOL_GPL(clk_round_rate);
b2476490 859
4dff95dc
SB
860/**
861 * __clk_notify - call clk notifier chain
862 * @core: clk that is changing rate
863 * @msg: clk notifier type (see include/linux/clk.h)
864 * @old_rate: old clk rate
865 * @new_rate: new clk rate
866 *
867 * Triggers a notifier call chain on the clk rate-change notification
868 * for 'clk'. Passes a pointer to the struct clk and the previous
869 * and current rates to the notifier callback. Intended to be called by
870 * internal clock code only. Returns NOTIFY_DONE from the last driver
871 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
872 * a driver returns that.
873 */
874static int __clk_notify(struct clk_core *core, unsigned long msg,
875 unsigned long old_rate, unsigned long new_rate)
b2476490 876{
4dff95dc
SB
877 struct clk_notifier *cn;
878 struct clk_notifier_data cnd;
879 int ret = NOTIFY_DONE;
b2476490 880
4dff95dc
SB
881 cnd.old_rate = old_rate;
882 cnd.new_rate = new_rate;
b2476490 883
4dff95dc
SB
884 list_for_each_entry(cn, &clk_notifier_list, node) {
885 if (cn->clk->core == core) {
886 cnd.clk = cn->clk;
887 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
888 &cnd);
889 }
b2476490
MT
890 }
891
4dff95dc 892 return ret;
b2476490
MT
893}
894
4dff95dc
SB
895/**
896 * __clk_recalc_accuracies
897 * @core: first clk in the subtree
898 *
899 * Walks the subtree of clks starting with clk and recalculates accuracies as
900 * it goes. Note that if a clk does not implement the .recalc_accuracy
6e5ab41b 901 * callback then it is assumed that the clock will take on the accuracy of its
4dff95dc 902 * parent.
4dff95dc
SB
903 */
904static void __clk_recalc_accuracies(struct clk_core *core)
b2476490 905{
4dff95dc
SB
906 unsigned long parent_accuracy = 0;
907 struct clk_core *child;
b2476490 908
4dff95dc 909 lockdep_assert_held(&prepare_lock);
b2476490 910
4dff95dc
SB
911 if (core->parent)
912 parent_accuracy = core->parent->accuracy;
b2476490 913
4dff95dc
SB
914 if (core->ops->recalc_accuracy)
915 core->accuracy = core->ops->recalc_accuracy(core->hw,
916 parent_accuracy);
917 else
918 core->accuracy = parent_accuracy;
b2476490 919
4dff95dc
SB
920 hlist_for_each_entry(child, &core->children, child_node)
921 __clk_recalc_accuracies(child);
b2476490
MT
922}
923
4dff95dc 924static long clk_core_get_accuracy(struct clk_core *core)
e366fdd7 925{
4dff95dc 926 unsigned long accuracy;
15a02c1f 927
4dff95dc
SB
928 clk_prepare_lock();
929 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
930 __clk_recalc_accuracies(core);
15a02c1f 931
4dff95dc
SB
932 accuracy = __clk_get_accuracy(core);
933 clk_prepare_unlock();
e366fdd7 934
4dff95dc 935 return accuracy;
e366fdd7 936}
15a02c1f 937
4dff95dc
SB
938/**
939 * clk_get_accuracy - return the accuracy of clk
940 * @clk: the clk whose accuracy is being returned
941 *
942 * Simply returns the cached accuracy of the clk, unless
943 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
944 * issued.
945 * If clk is NULL then returns 0.
946 */
947long clk_get_accuracy(struct clk *clk)
035a61c3 948{
4dff95dc
SB
949 if (!clk)
950 return 0;
035a61c3 951
4dff95dc 952 return clk_core_get_accuracy(clk->core);
035a61c3 953}
4dff95dc 954EXPORT_SYMBOL_GPL(clk_get_accuracy);
035a61c3 955
4dff95dc
SB
956static unsigned long clk_recalc(struct clk_core *core,
957 unsigned long parent_rate)
1c8e6004 958{
4dff95dc
SB
959 if (core->ops->recalc_rate)
960 return core->ops->recalc_rate(core->hw, parent_rate);
961 return parent_rate;
1c8e6004
TV
962}
963
4dff95dc
SB
964/**
965 * __clk_recalc_rates
966 * @core: first clk in the subtree
967 * @msg: notification type (see include/linux/clk.h)
968 *
969 * Walks the subtree of clks starting with clk and recalculates rates as it
970 * goes. Note that if a clk does not implement the .recalc_rate callback then
971 * it is assumed that the clock will take on the rate of its parent.
972 *
973 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
974 * if necessary.
15a02c1f 975 */
4dff95dc 976static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
15a02c1f 977{
4dff95dc
SB
978 unsigned long old_rate;
979 unsigned long parent_rate = 0;
980 struct clk_core *child;
e366fdd7 981
4dff95dc 982 lockdep_assert_held(&prepare_lock);
15a02c1f 983
4dff95dc 984 old_rate = core->rate;
b2476490 985
4dff95dc
SB
986 if (core->parent)
987 parent_rate = core->parent->rate;
b2476490 988
4dff95dc 989 core->rate = clk_recalc(core, parent_rate);
b2476490 990
4dff95dc
SB
991 /*
992 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
993 * & ABORT_RATE_CHANGE notifiers
994 */
995 if (core->notifier_count && msg)
996 __clk_notify(core, msg, old_rate, core->rate);
b2476490 997
4dff95dc
SB
998 hlist_for_each_entry(child, &core->children, child_node)
999 __clk_recalc_rates(child, msg);
1000}
b2476490 1001
4dff95dc
SB
1002static unsigned long clk_core_get_rate(struct clk_core *core)
1003{
1004 unsigned long rate;
dfc202ea 1005
4dff95dc 1006 clk_prepare_lock();
b2476490 1007
4dff95dc
SB
1008 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1009 __clk_recalc_rates(core, 0);
1010
1011 rate = clk_core_get_rate_nolock(core);
1012 clk_prepare_unlock();
1013
1014 return rate;
b2476490
MT
1015}
1016
1017/**
4dff95dc
SB
1018 * clk_get_rate - return the rate of clk
1019 * @clk: the clk whose rate is being returned
b2476490 1020 *
4dff95dc
SB
1021 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1022 * is set, which means a recalc_rate will be issued.
1023 * If clk is NULL then returns 0.
b2476490 1024 */
4dff95dc 1025unsigned long clk_get_rate(struct clk *clk)
b2476490 1026{
4dff95dc
SB
1027 if (!clk)
1028 return 0;
63589e92 1029
4dff95dc 1030 return clk_core_get_rate(clk->core);
b2476490 1031}
4dff95dc 1032EXPORT_SYMBOL_GPL(clk_get_rate);
b2476490 1033
4dff95dc
SB
1034static int clk_fetch_parent_index(struct clk_core *core,
1035 struct clk_core *parent)
b2476490 1036{
4dff95dc 1037 int i;
b2476490 1038
4dff95dc
SB
1039 if (!core->parents) {
1040 core->parents = kcalloc(core->num_parents,
1041 sizeof(struct clk *), GFP_KERNEL);
1042 if (!core->parents)
1043 return -ENOMEM;
1044 }
dfc202ea 1045
4dff95dc
SB
1046 /*
1047 * find index of new parent clock using cached parent ptrs,
1048 * or if not yet cached, use string name comparison and cache
1049 * them now to avoid future calls to clk_core_lookup.
1050 */
1051 for (i = 0; i < core->num_parents; i++) {
1052 if (core->parents[i] == parent)
1053 return i;
dfc202ea 1054
4dff95dc
SB
1055 if (core->parents[i])
1056 continue;
dfc202ea 1057
4dff95dc
SB
1058 if (!strcmp(core->parent_names[i], parent->name)) {
1059 core->parents[i] = clk_core_lookup(parent->name);
1060 return i;
b2476490
MT
1061 }
1062 }
1063
4dff95dc 1064 return -EINVAL;
b2476490
MT
1065}
1066
4dff95dc 1067static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
b2476490 1068{
4dff95dc 1069 hlist_del(&core->child_node);
035a61c3 1070
4dff95dc
SB
1071 if (new_parent) {
1072 /* avoid duplicate POST_RATE_CHANGE notifications */
1073 if (new_parent->new_child == core)
1074 new_parent->new_child = NULL;
b2476490 1075
4dff95dc
SB
1076 hlist_add_head(&core->child_node, &new_parent->children);
1077 } else {
1078 hlist_add_head(&core->child_node, &clk_orphan_list);
1079 }
dfc202ea 1080
4dff95dc 1081 core->parent = new_parent;
035a61c3
TV
1082}
1083
4dff95dc
SB
1084static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1085 struct clk_core *parent)
b2476490
MT
1086{
1087 unsigned long flags;
4dff95dc 1088 struct clk_core *old_parent = core->parent;
b2476490 1089
4dff95dc
SB
1090 /*
1091 * Migrate prepare state between parents and prevent race with
1092 * clk_enable().
1093 *
1094 * If the clock is not prepared, then a race with
1095 * clk_enable/disable() is impossible since we already have the
1096 * prepare lock (future calls to clk_enable() need to be preceded by
1097 * a clk_prepare()).
1098 *
1099 * If the clock is prepared, migrate the prepared state to the new
1100 * parent and also protect against a race with clk_enable() by
1101 * forcing the clock and the new parent on. This ensures that all
1102 * future calls to clk_enable() are practically NOPs with respect to
1103 * hardware and software states.
1104 *
1105 * See also: Comment for clk_set_parent() below.
1106 */
1107 if (core->prepare_count) {
1108 clk_core_prepare(parent);
d2a5d46b 1109 flags = clk_enable_lock();
4dff95dc
SB
1110 clk_core_enable(parent);
1111 clk_core_enable(core);
d2a5d46b 1112 clk_enable_unlock(flags);
4dff95dc 1113 }
63589e92 1114
4dff95dc 1115 /* update the clk tree topology */
eab89f69 1116 flags = clk_enable_lock();
4dff95dc 1117 clk_reparent(core, parent);
eab89f69 1118 clk_enable_unlock(flags);
4dff95dc
SB
1119
1120 return old_parent;
b2476490 1121}
b2476490 1122
4dff95dc
SB
1123static void __clk_set_parent_after(struct clk_core *core,
1124 struct clk_core *parent,
1125 struct clk_core *old_parent)
b2476490 1126{
d2a5d46b
DA
1127 unsigned long flags;
1128
4dff95dc
SB
1129 /*
1130 * Finish the migration of prepare state and undo the changes done
1131 * for preventing a race with clk_enable().
1132 */
1133 if (core->prepare_count) {
d2a5d46b 1134 flags = clk_enable_lock();
4dff95dc
SB
1135 clk_core_disable(core);
1136 clk_core_disable(old_parent);
d2a5d46b 1137 clk_enable_unlock(flags);
4dff95dc
SB
1138 clk_core_unprepare(old_parent);
1139 }
1140}
b2476490 1141
4dff95dc
SB
1142static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
1143 u8 p_index)
1144{
1145 unsigned long flags;
1146 int ret = 0;
1147 struct clk_core *old_parent;
b2476490 1148
4dff95dc 1149 old_parent = __clk_set_parent_before(core, parent);
b2476490 1150
4dff95dc 1151 trace_clk_set_parent(core, parent);
b2476490 1152
4dff95dc
SB
1153 /* change clock input source */
1154 if (parent && core->ops->set_parent)
1155 ret = core->ops->set_parent(core->hw, p_index);
dfc202ea 1156
4dff95dc 1157 trace_clk_set_parent_complete(core, parent);
dfc202ea 1158
4dff95dc
SB
1159 if (ret) {
1160 flags = clk_enable_lock();
1161 clk_reparent(core, old_parent);
1162 clk_enable_unlock(flags);
dfc202ea 1163
4dff95dc 1164 if (core->prepare_count) {
d2a5d46b 1165 flags = clk_enable_lock();
4dff95dc
SB
1166 clk_core_disable(core);
1167 clk_core_disable(parent);
d2a5d46b 1168 clk_enable_unlock(flags);
4dff95dc 1169 clk_core_unprepare(parent);
b2476490 1170 }
4dff95dc 1171 return ret;
b2476490
MT
1172 }
1173
4dff95dc
SB
1174 __clk_set_parent_after(core, parent, old_parent);
1175
b2476490
MT
1176 return 0;
1177}
1178
1179/**
4dff95dc
SB
1180 * __clk_speculate_rates
1181 * @core: first clk in the subtree
1182 * @parent_rate: the "future" rate of clk's parent
b2476490 1183 *
4dff95dc
SB
1184 * Walks the subtree of clks starting with clk, speculating rates as it
1185 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1186 *
1187 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1188 * pre-rate change notifications and returns early if no clks in the
1189 * subtree have subscribed to the notifications. Note that if a clk does not
1190 * implement the .recalc_rate callback then it is assumed that the clock will
1191 * take on the rate of its parent.
b2476490 1192 */
4dff95dc
SB
1193static int __clk_speculate_rates(struct clk_core *core,
1194 unsigned long parent_rate)
b2476490 1195{
4dff95dc
SB
1196 struct clk_core *child;
1197 unsigned long new_rate;
1198 int ret = NOTIFY_DONE;
b2476490 1199
4dff95dc 1200 lockdep_assert_held(&prepare_lock);
864e160a 1201
4dff95dc
SB
1202 new_rate = clk_recalc(core, parent_rate);
1203
1204 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1205 if (core->notifier_count)
1206 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
1207
1208 if (ret & NOTIFY_STOP_MASK) {
1209 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1210 __func__, core->name, ret);
1211 goto out;
1212 }
1213
1214 hlist_for_each_entry(child, &core->children, child_node) {
1215 ret = __clk_speculate_rates(child, new_rate);
1216 if (ret & NOTIFY_STOP_MASK)
1217 break;
1218 }
b2476490 1219
4dff95dc 1220out:
b2476490
MT
1221 return ret;
1222}
b2476490 1223
4dff95dc
SB
1224static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
1225 struct clk_core *new_parent, u8 p_index)
b2476490 1226{
4dff95dc 1227 struct clk_core *child;
b2476490 1228
4dff95dc
SB
1229 core->new_rate = new_rate;
1230 core->new_parent = new_parent;
1231 core->new_parent_index = p_index;
1232 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1233 core->new_child = NULL;
1234 if (new_parent && new_parent != core->parent)
1235 new_parent->new_child = core;
496eadf8 1236
4dff95dc
SB
1237 hlist_for_each_entry(child, &core->children, child_node) {
1238 child->new_rate = clk_recalc(child, new_rate);
1239 clk_calc_subtree(child, child->new_rate, NULL, 0);
1240 }
1241}
b2476490 1242
4dff95dc
SB
1243/*
1244 * calculate the new rates returning the topmost clock that has to be
1245 * changed.
1246 */
1247static struct clk_core *clk_calc_new_rates(struct clk_core *core,
1248 unsigned long rate)
1249{
1250 struct clk_core *top = core;
1251 struct clk_core *old_parent, *parent;
1252 struct clk_hw *parent_hw;
1253 unsigned long best_parent_rate = 0;
1254 unsigned long new_rate;
1255 unsigned long min_rate;
1256 unsigned long max_rate;
1257 int p_index = 0;
1258 long ret;
1259
1260 /* sanity */
1261 if (IS_ERR_OR_NULL(core))
1262 return NULL;
1263
1264 /* save parent rate, if it exists */
1265 parent = old_parent = core->parent;
71472c0c 1266 if (parent)
4dff95dc 1267 best_parent_rate = parent->rate;
71472c0c 1268
4dff95dc
SB
1269 clk_core_get_boundaries(core, &min_rate, &max_rate);
1270
1271 /* find the closest rate and parent clk/rate */
d6968fca 1272 if (core->ops->determine_rate) {
646cafc6 1273 parent_hw = parent ? parent->hw : NULL;
4dff95dc
SB
1274 ret = core->ops->determine_rate(core->hw, rate,
1275 min_rate,
1276 max_rate,
1277 &best_parent_rate,
1278 &parent_hw);
1279 if (ret < 0)
1280 return NULL;
1c8e6004 1281
4dff95dc
SB
1282 new_rate = ret;
1283 parent = parent_hw ? parent_hw->core : NULL;
1284 } else if (core->ops->round_rate) {
1285 ret = core->ops->round_rate(core->hw, rate,
1286 &best_parent_rate);
1287 if (ret < 0)
1288 return NULL;
035a61c3 1289
4dff95dc
SB
1290 new_rate = ret;
1291 if (new_rate < min_rate || new_rate > max_rate)
1292 return NULL;
1293 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
1294 /* pass-through clock without adjustable parent */
1295 core->new_rate = core->rate;
1296 return NULL;
1297 } else {
1298 /* pass-through clock with adjustable parent */
1299 top = clk_calc_new_rates(parent, rate);
1300 new_rate = parent->new_rate;
1301 goto out;
1302 }
1c8e6004 1303
4dff95dc
SB
1304 /* some clocks must be gated to change parent */
1305 if (parent != old_parent &&
1306 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1307 pr_debug("%s: %s not gated but wants to reparent\n",
1308 __func__, core->name);
1309 return NULL;
1310 }
b2476490 1311
4dff95dc
SB
1312 /* try finding the new parent index */
1313 if (parent && core->num_parents > 1) {
1314 p_index = clk_fetch_parent_index(core, parent);
1315 if (p_index < 0) {
1316 pr_debug("%s: clk %s can not be parent of clk %s\n",
1317 __func__, parent->name, core->name);
1318 return NULL;
1319 }
1320 }
b2476490 1321
4dff95dc
SB
1322 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
1323 best_parent_rate != parent->rate)
1324 top = clk_calc_new_rates(parent, best_parent_rate);
035a61c3 1325
4dff95dc
SB
1326out:
1327 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490 1328
4dff95dc 1329 return top;
b2476490 1330}
b2476490 1331
4dff95dc
SB
1332/*
1333 * Notify about rate changes in a subtree. Always walk down the whole tree
1334 * so that in case of an error we can walk down the whole tree again and
1335 * abort the change.
b2476490 1336 */
4dff95dc
SB
1337static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
1338 unsigned long event)
b2476490 1339{
4dff95dc 1340 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1341 int ret = NOTIFY_DONE;
1342
4dff95dc
SB
1343 if (core->rate == core->new_rate)
1344 return NULL;
b2476490 1345
4dff95dc
SB
1346 if (core->notifier_count) {
1347 ret = __clk_notify(core, event, core->rate, core->new_rate);
1348 if (ret & NOTIFY_STOP_MASK)
1349 fail_clk = core;
b2476490
MT
1350 }
1351
4dff95dc
SB
1352 hlist_for_each_entry(child, &core->children, child_node) {
1353 /* Skip children who will be reparented to another clock */
1354 if (child->new_parent && child->new_parent != core)
1355 continue;
1356 tmp_clk = clk_propagate_rate_change(child, event);
1357 if (tmp_clk)
1358 fail_clk = tmp_clk;
1359 }
5279fc40 1360
4dff95dc
SB
1361 /* handle the new child who might not be in core->children yet */
1362 if (core->new_child) {
1363 tmp_clk = clk_propagate_rate_change(core->new_child, event);
1364 if (tmp_clk)
1365 fail_clk = tmp_clk;
1366 }
5279fc40 1367
4dff95dc 1368 return fail_clk;
5279fc40
BB
1369}
1370
4dff95dc
SB
1371/*
1372 * walk down a subtree and set the new rates notifying the rate
1373 * change on the way
1374 */
1375static void clk_change_rate(struct clk_core *core)
035a61c3 1376{
4dff95dc
SB
1377 struct clk_core *child;
1378 struct hlist_node *tmp;
1379 unsigned long old_rate;
1380 unsigned long best_parent_rate = 0;
1381 bool skip_set_rate = false;
1382 struct clk_core *old_parent;
035a61c3 1383
4dff95dc 1384 old_rate = core->rate;
035a61c3 1385
4dff95dc
SB
1386 if (core->new_parent)
1387 best_parent_rate = core->new_parent->rate;
1388 else if (core->parent)
1389 best_parent_rate = core->parent->rate;
035a61c3 1390
4dff95dc
SB
1391 if (core->new_parent && core->new_parent != core->parent) {
1392 old_parent = __clk_set_parent_before(core, core->new_parent);
1393 trace_clk_set_parent(core, core->new_parent);
5279fc40 1394
4dff95dc
SB
1395 if (core->ops->set_rate_and_parent) {
1396 skip_set_rate = true;
1397 core->ops->set_rate_and_parent(core->hw, core->new_rate,
1398 best_parent_rate,
1399 core->new_parent_index);
1400 } else if (core->ops->set_parent) {
1401 core->ops->set_parent(core->hw, core->new_parent_index);
1402 }
5279fc40 1403
4dff95dc
SB
1404 trace_clk_set_parent_complete(core, core->new_parent);
1405 __clk_set_parent_after(core, core->new_parent, old_parent);
1406 }
8f2c2db1 1407
4dff95dc 1408 trace_clk_set_rate(core, core->new_rate);
b2476490 1409
4dff95dc
SB
1410 if (!skip_set_rate && core->ops->set_rate)
1411 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
496eadf8 1412
4dff95dc 1413 trace_clk_set_rate_complete(core, core->new_rate);
b2476490 1414
4dff95dc 1415 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1416
4dff95dc
SB
1417 if (core->notifier_count && old_rate != core->rate)
1418 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1419
85e88fab
MT
1420 if (core->flags & CLK_RECALC_NEW_RATES)
1421 (void)clk_calc_new_rates(core, core->new_rate);
d8d91987 1422
b2476490 1423 /*
4dff95dc
SB
1424 * Use safe iteration, as change_rate can actually swap parents
1425 * for certain clock types.
b2476490 1426 */
4dff95dc
SB
1427 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
1428 /* Skip children who will be reparented to another clock */
1429 if (child->new_parent && child->new_parent != core)
1430 continue;
1431 clk_change_rate(child);
1432 }
b2476490 1433
4dff95dc
SB
1434 /* handle the new child who might not be in core->children yet */
1435 if (core->new_child)
1436 clk_change_rate(core->new_child);
b2476490
MT
1437}
1438
4dff95dc
SB
1439static int clk_core_set_rate_nolock(struct clk_core *core,
1440 unsigned long req_rate)
a093bde2 1441{
4dff95dc
SB
1442 struct clk_core *top, *fail_clk;
1443 unsigned long rate = req_rate;
1444 int ret = 0;
a093bde2 1445
4dff95dc
SB
1446 if (!core)
1447 return 0;
a093bde2 1448
4dff95dc
SB
1449 /* bail early if nothing to do */
1450 if (rate == clk_core_get_rate_nolock(core))
1451 return 0;
a093bde2 1452
4dff95dc
SB
1453 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1454 return -EBUSY;
a093bde2 1455
4dff95dc
SB
1456 /* calculate new rates and get the topmost changed clock */
1457 top = clk_calc_new_rates(core, rate);
1458 if (!top)
1459 return -EINVAL;
1460
1461 /* notify that we are about to change rates */
1462 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1463 if (fail_clk) {
1464 pr_debug("%s: failed to set %s rate\n", __func__,
1465 fail_clk->name);
1466 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1467 return -EBUSY;
1468 }
1469
1470 /* change the rates */
1471 clk_change_rate(top);
1472
1473 core->req_rate = req_rate;
1474
1475 return ret;
a093bde2 1476}
035a61c3
TV
1477
1478/**
4dff95dc
SB
1479 * clk_set_rate - specify a new rate for clk
1480 * @clk: the clk whose rate is being changed
1481 * @rate: the new rate for clk
035a61c3 1482 *
4dff95dc
SB
1483 * In the simplest case clk_set_rate will only adjust the rate of clk.
1484 *
1485 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1486 * propagate up to clk's parent; whether or not this happens depends on the
1487 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1488 * after calling .round_rate then upstream parent propagation is ignored. If
1489 * *parent_rate comes back with a new rate for clk's parent then we propagate
1490 * up to clk's parent and set its rate. Upward propagation will continue
1491 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1492 * .round_rate stops requesting changes to clk's parent_rate.
1493 *
1494 * Rate changes are accomplished via tree traversal that also recalculates the
1495 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
1496 *
1497 * Returns 0 on success, -EERROR otherwise.
035a61c3 1498 */
4dff95dc 1499int clk_set_rate(struct clk *clk, unsigned long rate)
035a61c3 1500{
4dff95dc
SB
1501 int ret;
1502
035a61c3
TV
1503 if (!clk)
1504 return 0;
1505
4dff95dc
SB
1506 /* prevent racing with updates to the clock topology */
1507 clk_prepare_lock();
da0f0b2c 1508
4dff95dc 1509 ret = clk_core_set_rate_nolock(clk->core, rate);
da0f0b2c 1510
4dff95dc 1511 clk_prepare_unlock();
4935b22c 1512
4dff95dc 1513 return ret;
4935b22c 1514}
4dff95dc 1515EXPORT_SYMBOL_GPL(clk_set_rate);
4935b22c 1516
4dff95dc
SB
1517/**
1518 * clk_set_rate_range - set a rate range for a clock source
1519 * @clk: clock source
1520 * @min: desired minimum clock rate in Hz, inclusive
1521 * @max: desired maximum clock rate in Hz, inclusive
1522 *
1523 * Returns success (0) or negative errno.
1524 */
1525int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
4935b22c 1526{
4dff95dc 1527 int ret = 0;
4935b22c 1528
4dff95dc
SB
1529 if (!clk)
1530 return 0;
903efc55 1531
4dff95dc
SB
1532 if (min > max) {
1533 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1534 __func__, clk->core->name, clk->dev_id, clk->con_id,
1535 min, max);
1536 return -EINVAL;
903efc55 1537 }
4935b22c 1538
4dff95dc 1539 clk_prepare_lock();
4935b22c 1540
4dff95dc
SB
1541 if (min != clk->min_rate || max != clk->max_rate) {
1542 clk->min_rate = min;
1543 clk->max_rate = max;
1544 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
4935b22c
JH
1545 }
1546
4dff95dc 1547 clk_prepare_unlock();
4935b22c 1548
4dff95dc 1549 return ret;
3fa2252b 1550}
4dff95dc 1551EXPORT_SYMBOL_GPL(clk_set_rate_range);
3fa2252b 1552
4dff95dc
SB
1553/**
1554 * clk_set_min_rate - set a minimum clock rate for a clock source
1555 * @clk: clock source
1556 * @rate: desired minimum clock rate in Hz, inclusive
1557 *
1558 * Returns success (0) or negative errno.
1559 */
1560int clk_set_min_rate(struct clk *clk, unsigned long rate)
3fa2252b 1561{
4dff95dc
SB
1562 if (!clk)
1563 return 0;
1564
1565 return clk_set_rate_range(clk, rate, clk->max_rate);
3fa2252b 1566}
4dff95dc 1567EXPORT_SYMBOL_GPL(clk_set_min_rate);
3fa2252b 1568
4dff95dc
SB
1569/**
1570 * clk_set_max_rate - set a maximum clock rate for a clock source
1571 * @clk: clock source
1572 * @rate: desired maximum clock rate in Hz, inclusive
1573 *
1574 * Returns success (0) or negative errno.
1575 */
1576int clk_set_max_rate(struct clk *clk, unsigned long rate)
3fa2252b 1577{
4dff95dc
SB
1578 if (!clk)
1579 return 0;
4935b22c 1580
4dff95dc 1581 return clk_set_rate_range(clk, clk->min_rate, rate);
4935b22c 1582}
4dff95dc 1583EXPORT_SYMBOL_GPL(clk_set_max_rate);
4935b22c 1584
b2476490 1585/**
4dff95dc
SB
1586 * clk_get_parent - return the parent of a clk
1587 * @clk: the clk whose parent gets returned
b2476490 1588 *
4dff95dc 1589 * Simply returns clk->parent. Returns NULL if clk is NULL.
b2476490 1590 */
4dff95dc 1591struct clk *clk_get_parent(struct clk *clk)
b2476490 1592{
4dff95dc 1593 struct clk *parent;
b2476490 1594
4dff95dc
SB
1595 clk_prepare_lock();
1596 parent = __clk_get_parent(clk);
1597 clk_prepare_unlock();
496eadf8 1598
4dff95dc
SB
1599 return parent;
1600}
1601EXPORT_SYMBOL_GPL(clk_get_parent);
b2476490 1602
4dff95dc
SB
1603/*
1604 * .get_parent is mandatory for clocks with multiple possible parents. It is
1605 * optional for single-parent clocks. Always call .get_parent if it is
1606 * available and WARN if it is missing for multi-parent clocks.
1607 *
1608 * For single-parent clocks without .get_parent, first check to see if the
1609 * .parents array exists, and if so use it to avoid an expensive tree
1610 * traversal. If .parents does not exist then walk the tree.
1611 */
1612static struct clk_core *__clk_init_parent(struct clk_core *core)
1613{
1614 struct clk_core *ret = NULL;
1615 u8 index;
b2476490 1616
4dff95dc
SB
1617 /* handle the trivial cases */
1618
1619 if (!core->num_parents)
b2476490
MT
1620 goto out;
1621
4dff95dc
SB
1622 if (core->num_parents == 1) {
1623 if (IS_ERR_OR_NULL(core->parent))
1624 core->parent = clk_core_lookup(core->parent_names[0]);
1625 ret = core->parent;
1626 goto out;
b2476490
MT
1627 }
1628
4dff95dc
SB
1629 if (!core->ops->get_parent) {
1630 WARN(!core->ops->get_parent,
1631 "%s: multi-parent clocks must implement .get_parent\n",
1632 __func__);
1633 goto out;
1634 };
1635
1636 /*
1637 * Do our best to cache parent clocks in core->parents. This prevents
1638 * unnecessary and expensive lookups. We don't set core->parent here;
1639 * that is done by the calling function.
1640 */
1641
1642 index = core->ops->get_parent(core->hw);
1643
1644 if (!core->parents)
1645 core->parents =
1646 kcalloc(core->num_parents, sizeof(struct clk *),
1647 GFP_KERNEL);
1648
1649 ret = clk_core_get_parent_by_index(core, index);
1650
b2476490
MT
1651out:
1652 return ret;
1653}
1654
4dff95dc
SB
1655static void clk_core_reparent(struct clk_core *core,
1656 struct clk_core *new_parent)
b2476490 1657{
4dff95dc
SB
1658 clk_reparent(core, new_parent);
1659 __clk_recalc_accuracies(core);
1660 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
1661}
1662
42c86547
TV
1663void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
1664{
1665 if (!hw)
1666 return;
1667
1668 clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
1669}
1670
4dff95dc
SB
1671/**
1672 * clk_has_parent - check if a clock is a possible parent for another
1673 * @clk: clock source
1674 * @parent: parent clock source
1675 *
1676 * This function can be used in drivers that need to check that a clock can be
1677 * the parent of another without actually changing the parent.
1678 *
1679 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 1680 */
4dff95dc 1681bool clk_has_parent(struct clk *clk, struct clk *parent)
b2476490 1682{
4dff95dc
SB
1683 struct clk_core *core, *parent_core;
1684 unsigned int i;
b2476490 1685
4dff95dc
SB
1686 /* NULL clocks should be nops, so return success if either is NULL. */
1687 if (!clk || !parent)
1688 return true;
7452b219 1689
4dff95dc
SB
1690 core = clk->core;
1691 parent_core = parent->core;
71472c0c 1692
4dff95dc
SB
1693 /* Optimize for the case where the parent is already the parent. */
1694 if (core->parent == parent_core)
1695 return true;
1c8e6004 1696
4dff95dc
SB
1697 for (i = 0; i < core->num_parents; i++)
1698 if (strcmp(core->parent_names[i], parent_core->name) == 0)
1699 return true;
03bc10ab 1700
4dff95dc
SB
1701 return false;
1702}
1703EXPORT_SYMBOL_GPL(clk_has_parent);
03bc10ab 1704
4dff95dc
SB
1705static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1706{
1707 int ret = 0;
1708 int p_index = 0;
1709 unsigned long p_rate = 0;
1710
1711 if (!core)
1712 return 0;
1713
1714 /* prevent racing with updates to the clock topology */
1715 clk_prepare_lock();
1716
1717 if (core->parent == parent)
1718 goto out;
1719
1720 /* verify ops for for multi-parent clks */
1721 if ((core->num_parents > 1) && (!core->ops->set_parent)) {
1722 ret = -ENOSYS;
63f5c3b2 1723 goto out;
7452b219
MT
1724 }
1725
4dff95dc
SB
1726 /* check that we are allowed to re-parent if the clock is in use */
1727 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1728 ret = -EBUSY;
1729 goto out;
b2476490
MT
1730 }
1731
71472c0c 1732 /* try finding the new parent index */
4dff95dc 1733 if (parent) {
d6968fca 1734 p_index = clk_fetch_parent_index(core, parent);
4dff95dc 1735 p_rate = parent->rate;
f1c8b2ed 1736 if (p_index < 0) {
71472c0c 1737 pr_debug("%s: clk %s can not be parent of clk %s\n",
4dff95dc
SB
1738 __func__, parent->name, core->name);
1739 ret = p_index;
1740 goto out;
71472c0c 1741 }
b2476490
MT
1742 }
1743
4dff95dc
SB
1744 /* propagate PRE_RATE_CHANGE notifications */
1745 ret = __clk_speculate_rates(core, p_rate);
b2476490 1746
4dff95dc
SB
1747 /* abort if a driver objects */
1748 if (ret & NOTIFY_STOP_MASK)
1749 goto out;
b2476490 1750
4dff95dc
SB
1751 /* do the re-parent */
1752 ret = __clk_set_parent(core, parent, p_index);
b2476490 1753
4dff95dc
SB
1754 /* propagate rate an accuracy recalculation accordingly */
1755 if (ret) {
1756 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
1757 } else {
1758 __clk_recalc_rates(core, POST_RATE_CHANGE);
1759 __clk_recalc_accuracies(core);
b2476490
MT
1760 }
1761
4dff95dc
SB
1762out:
1763 clk_prepare_unlock();
71472c0c 1764
4dff95dc
SB
1765 return ret;
1766}
b2476490 1767
4dff95dc
SB
1768/**
1769 * clk_set_parent - switch the parent of a mux clk
1770 * @clk: the mux clk whose input we are switching
1771 * @parent: the new input to clk
1772 *
1773 * Re-parent clk to use parent as its new input source. If clk is in
1774 * prepared state, the clk will get enabled for the duration of this call. If
1775 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1776 * that, the reparenting is glitchy in hardware, etc), use the
1777 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1778 *
1779 * After successfully changing clk's parent clk_set_parent will update the
1780 * clk topology, sysfs topology and propagate rate recalculation via
1781 * __clk_recalc_rates.
1782 *
1783 * Returns 0 on success, -EERROR otherwise.
1784 */
1785int clk_set_parent(struct clk *clk, struct clk *parent)
1786{
1787 if (!clk)
1788 return 0;
1789
1790 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
b2476490 1791}
4dff95dc 1792EXPORT_SYMBOL_GPL(clk_set_parent);
b2476490 1793
4dff95dc
SB
1794/**
1795 * clk_set_phase - adjust the phase shift of a clock signal
1796 * @clk: clock signal source
1797 * @degrees: number of degrees the signal is shifted
1798 *
1799 * Shifts the phase of a clock signal by the specified
1800 * degrees. Returns 0 on success, -EERROR otherwise.
1801 *
1802 * This function makes no distinction about the input or reference
1803 * signal that we adjust the clock signal phase against. For example
1804 * phase locked-loop clock signal generators we may shift phase with
1805 * respect to feedback clock signal input, but for other cases the
1806 * clock phase may be shifted with respect to some other, unspecified
1807 * signal.
1808 *
1809 * Additionally the concept of phase shift does not propagate through
1810 * the clock tree hierarchy, which sets it apart from clock rates and
1811 * clock accuracy. A parent clock phase attribute does not have an
1812 * impact on the phase attribute of a child clock.
b2476490 1813 */
4dff95dc 1814int clk_set_phase(struct clk *clk, int degrees)
b2476490 1815{
4dff95dc 1816 int ret = -EINVAL;
b2476490 1817
4dff95dc
SB
1818 if (!clk)
1819 return 0;
b2476490 1820
4dff95dc
SB
1821 /* sanity check degrees */
1822 degrees %= 360;
1823 if (degrees < 0)
1824 degrees += 360;
bf47b4fd 1825
4dff95dc 1826 clk_prepare_lock();
3fa2252b 1827
4dff95dc 1828 trace_clk_set_phase(clk->core, degrees);
3fa2252b 1829
4dff95dc
SB
1830 if (clk->core->ops->set_phase)
1831 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
3fa2252b 1832
4dff95dc 1833 trace_clk_set_phase_complete(clk->core, degrees);
dfc202ea 1834
4dff95dc
SB
1835 if (!ret)
1836 clk->core->phase = degrees;
b2476490 1837
4dff95dc 1838 clk_prepare_unlock();
dfc202ea 1839
4dff95dc
SB
1840 return ret;
1841}
1842EXPORT_SYMBOL_GPL(clk_set_phase);
b2476490 1843
4dff95dc
SB
1844static int clk_core_get_phase(struct clk_core *core)
1845{
1846 int ret;
b2476490 1847
4dff95dc
SB
1848 clk_prepare_lock();
1849 ret = core->phase;
1850 clk_prepare_unlock();
71472c0c 1851
4dff95dc 1852 return ret;
b2476490
MT
1853}
1854
4dff95dc
SB
1855/**
1856 * clk_get_phase - return the phase shift of a clock signal
1857 * @clk: clock signal source
1858 *
1859 * Returns the phase shift of a clock node in degrees, otherwise returns
1860 * -EERROR.
1861 */
1862int clk_get_phase(struct clk *clk)
1c8e6004 1863{
4dff95dc 1864 if (!clk)
1c8e6004
TV
1865 return 0;
1866
4dff95dc
SB
1867 return clk_core_get_phase(clk->core);
1868}
1869EXPORT_SYMBOL_GPL(clk_get_phase);
1c8e6004 1870
4dff95dc
SB
1871/**
1872 * clk_is_match - check if two clk's point to the same hardware clock
1873 * @p: clk compared against q
1874 * @q: clk compared against p
1875 *
1876 * Returns true if the two struct clk pointers both point to the same hardware
1877 * clock node. Put differently, returns true if struct clk *p and struct clk *q
1878 * share the same struct clk_core object.
1879 *
1880 * Returns false otherwise. Note that two NULL clks are treated as matching.
1881 */
1882bool clk_is_match(const struct clk *p, const struct clk *q)
1883{
1884 /* trivial case: identical struct clk's or both NULL */
1885 if (p == q)
1886 return true;
1c8e6004 1887
4dff95dc
SB
1888 /* true if clk->core pointers match. Avoid derefing garbage */
1889 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
1890 if (p->core == q->core)
1891 return true;
1c8e6004 1892
4dff95dc
SB
1893 return false;
1894}
1895EXPORT_SYMBOL_GPL(clk_is_match);
1c8e6004 1896
4dff95dc 1897/*** debugfs support ***/
1c8e6004 1898
4dff95dc
SB
1899#ifdef CONFIG_DEBUG_FS
1900#include <linux/debugfs.h>
1c8e6004 1901
4dff95dc
SB
1902static struct dentry *rootdir;
1903static int inited = 0;
1904static DEFINE_MUTEX(clk_debug_lock);
1905static HLIST_HEAD(clk_debug_list);
1c8e6004 1906
4dff95dc
SB
1907static struct hlist_head *all_lists[] = {
1908 &clk_root_list,
1909 &clk_orphan_list,
1910 NULL,
1911};
1912
1913static struct hlist_head *orphan_list[] = {
1914 &clk_orphan_list,
1915 NULL,
1916};
1917
1918static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
1919 int level)
b2476490 1920{
4dff95dc
SB
1921 if (!c)
1922 return;
b2476490 1923
4dff95dc
SB
1924 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
1925 level * 3 + 1, "",
1926 30 - level * 3, c->name,
1927 c->enable_count, c->prepare_count, clk_core_get_rate(c),
1928 clk_core_get_accuracy(c), clk_core_get_phase(c));
1929}
89ac8d7a 1930
4dff95dc
SB
1931static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
1932 int level)
1933{
1934 struct clk_core *child;
b2476490 1935
4dff95dc
SB
1936 if (!c)
1937 return;
b2476490 1938
4dff95dc 1939 clk_summary_show_one(s, c, level);
0e1c0301 1940
4dff95dc
SB
1941 hlist_for_each_entry(child, &c->children, child_node)
1942 clk_summary_show_subtree(s, child, level + 1);
1c8e6004 1943}
b2476490 1944
4dff95dc 1945static int clk_summary_show(struct seq_file *s, void *data)
1c8e6004 1946{
4dff95dc
SB
1947 struct clk_core *c;
1948 struct hlist_head **lists = (struct hlist_head **)s->private;
1c8e6004 1949
4dff95dc
SB
1950 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
1951 seq_puts(s, "----------------------------------------------------------------------------------------\n");
b2476490 1952
1c8e6004
TV
1953 clk_prepare_lock();
1954
4dff95dc
SB
1955 for (; *lists; lists++)
1956 hlist_for_each_entry(c, *lists, child_node)
1957 clk_summary_show_subtree(s, c, 0);
b2476490 1958
eab89f69 1959 clk_prepare_unlock();
b2476490 1960
4dff95dc 1961 return 0;
b2476490 1962}
1c8e6004 1963
1c8e6004 1964
4dff95dc 1965static int clk_summary_open(struct inode *inode, struct file *file)
1c8e6004 1966{
4dff95dc 1967 return single_open(file, clk_summary_show, inode->i_private);
1c8e6004 1968}
b2476490 1969
4dff95dc
SB
1970static const struct file_operations clk_summary_fops = {
1971 .open = clk_summary_open,
1972 .read = seq_read,
1973 .llseek = seq_lseek,
1974 .release = single_release,
1975};
b2476490 1976
4dff95dc
SB
1977static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
1978{
1979 if (!c)
1980 return;
b2476490 1981
7cb81136 1982 /* This should be JSON format, i.e. elements separated with a comma */
4dff95dc
SB
1983 seq_printf(s, "\"%s\": { ", c->name);
1984 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
1985 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
7cb81136
SW
1986 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
1987 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
4dff95dc 1988 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
b2476490 1989}
b2476490 1990
4dff95dc 1991static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
b2476490 1992{
4dff95dc 1993 struct clk_core *child;
b2476490 1994
4dff95dc
SB
1995 if (!c)
1996 return;
b2476490 1997
4dff95dc 1998 clk_dump_one(s, c, level);
b2476490 1999
4dff95dc
SB
2000 hlist_for_each_entry(child, &c->children, child_node) {
2001 seq_printf(s, ",");
2002 clk_dump_subtree(s, child, level + 1);
b2476490
MT
2003 }
2004
4dff95dc 2005 seq_printf(s, "}");
b2476490
MT
2006}
2007
4dff95dc 2008static int clk_dump(struct seq_file *s, void *data)
4e88f3de 2009{
4dff95dc
SB
2010 struct clk_core *c;
2011 bool first_node = true;
2012 struct hlist_head **lists = (struct hlist_head **)s->private;
4e88f3de 2013
4dff95dc 2014 seq_printf(s, "{");
4e88f3de 2015
4dff95dc 2016 clk_prepare_lock();
035a61c3 2017
4dff95dc
SB
2018 for (; *lists; lists++) {
2019 hlist_for_each_entry(c, *lists, child_node) {
2020 if (!first_node)
2021 seq_puts(s, ",");
2022 first_node = false;
2023 clk_dump_subtree(s, c, 0);
2024 }
2025 }
4e88f3de 2026
4dff95dc 2027 clk_prepare_unlock();
4e88f3de 2028
70e9f4dd 2029 seq_puts(s, "}\n");
4dff95dc 2030 return 0;
4e88f3de 2031}
4e88f3de 2032
4dff95dc
SB
2033
2034static int clk_dump_open(struct inode *inode, struct file *file)
b2476490 2035{
4dff95dc
SB
2036 return single_open(file, clk_dump, inode->i_private);
2037}
b2476490 2038
4dff95dc
SB
2039static const struct file_operations clk_dump_fops = {
2040 .open = clk_dump_open,
2041 .read = seq_read,
2042 .llseek = seq_lseek,
2043 .release = single_release,
2044};
89ac8d7a 2045
4dff95dc
SB
2046static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2047{
2048 struct dentry *d;
2049 int ret = -ENOMEM;
b2476490 2050
4dff95dc
SB
2051 if (!core || !pdentry) {
2052 ret = -EINVAL;
b2476490 2053 goto out;
4dff95dc 2054 }
b2476490 2055
4dff95dc
SB
2056 d = debugfs_create_dir(core->name, pdentry);
2057 if (!d)
b61c43c0 2058 goto out;
b61c43c0 2059
4dff95dc
SB
2060 core->dentry = d;
2061
2062 d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
2063 (u32 *)&core->rate);
2064 if (!d)
2065 goto err_out;
2066
2067 d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
2068 (u32 *)&core->accuracy);
2069 if (!d)
2070 goto err_out;
2071
2072 d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
2073 (u32 *)&core->phase);
2074 if (!d)
2075 goto err_out;
031dcc9b 2076
4dff95dc
SB
2077 d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
2078 (u32 *)&core->flags);
2079 if (!d)
2080 goto err_out;
031dcc9b 2081
4dff95dc
SB
2082 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
2083 (u32 *)&core->prepare_count);
2084 if (!d)
2085 goto err_out;
b2476490 2086
4dff95dc
SB
2087 d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
2088 (u32 *)&core->enable_count);
2089 if (!d)
2090 goto err_out;
b2476490 2091
4dff95dc
SB
2092 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
2093 (u32 *)&core->notifier_count);
2094 if (!d)
2095 goto err_out;
b2476490 2096
4dff95dc
SB
2097 if (core->ops->debug_init) {
2098 ret = core->ops->debug_init(core->hw, core->dentry);
2099 if (ret)
2100 goto err_out;
5279fc40 2101 }
b2476490 2102
4dff95dc
SB
2103 ret = 0;
2104 goto out;
b2476490 2105
4dff95dc
SB
2106err_out:
2107 debugfs_remove_recursive(core->dentry);
2108 core->dentry = NULL;
2109out:
b2476490
MT
2110 return ret;
2111}
035a61c3
TV
2112
2113/**
6e5ab41b
SB
2114 * clk_debug_register - add a clk node to the debugfs clk directory
2115 * @core: the clk being added to the debugfs clk directory
035a61c3 2116 *
6e5ab41b
SB
2117 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2118 * initialized. Otherwise it bails out early since the debugfs clk directory
4dff95dc 2119 * will be created lazily by clk_debug_init as part of a late_initcall.
035a61c3 2120 */
4dff95dc 2121static int clk_debug_register(struct clk_core *core)
035a61c3 2122{
4dff95dc 2123 int ret = 0;
035a61c3 2124
4dff95dc
SB
2125 mutex_lock(&clk_debug_lock);
2126 hlist_add_head(&core->debug_node, &clk_debug_list);
2127
2128 if (!inited)
2129 goto unlock;
2130
2131 ret = clk_debug_create_one(core, rootdir);
2132unlock:
2133 mutex_unlock(&clk_debug_lock);
2134
2135 return ret;
035a61c3 2136}
b2476490 2137
4dff95dc 2138 /**
6e5ab41b
SB
2139 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2140 * @core: the clk being removed from the debugfs clk directory
e59c5371 2141 *
6e5ab41b
SB
2142 * Dynamically removes a clk and all its child nodes from the
2143 * debugfs clk directory if clk->dentry points to debugfs created by
4dff95dc 2144 * clk_debug_register in __clk_init.
e59c5371 2145 */
4dff95dc 2146static void clk_debug_unregister(struct clk_core *core)
e59c5371 2147{
4dff95dc
SB
2148 mutex_lock(&clk_debug_lock);
2149 hlist_del_init(&core->debug_node);
2150 debugfs_remove_recursive(core->dentry);
2151 core->dentry = NULL;
2152 mutex_unlock(&clk_debug_lock);
2153}
e59c5371 2154
4dff95dc
SB
2155struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
2156 void *data, const struct file_operations *fops)
2157{
2158 struct dentry *d = NULL;
e59c5371 2159
4dff95dc
SB
2160 if (hw->core->dentry)
2161 d = debugfs_create_file(name, mode, hw->core->dentry, data,
2162 fops);
e59c5371 2163
4dff95dc
SB
2164 return d;
2165}
2166EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
e59c5371 2167
4dff95dc 2168/**
6e5ab41b 2169 * clk_debug_init - lazily populate the debugfs clk directory
4dff95dc 2170 *
6e5ab41b
SB
2171 * clks are often initialized very early during boot before memory can be
2172 * dynamically allocated and well before debugfs is setup. This function
2173 * populates the debugfs clk directory once at boot-time when we know that
2174 * debugfs is setup. It should only be called once at boot-time, all other clks
2175 * added dynamically will be done so with clk_debug_register.
4dff95dc
SB
2176 */
2177static int __init clk_debug_init(void)
2178{
2179 struct clk_core *core;
2180 struct dentry *d;
dfc202ea 2181
4dff95dc 2182 rootdir = debugfs_create_dir("clk", NULL);
e59c5371 2183
4dff95dc
SB
2184 if (!rootdir)
2185 return -ENOMEM;
dfc202ea 2186
4dff95dc
SB
2187 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
2188 &clk_summary_fops);
2189 if (!d)
2190 return -ENOMEM;
e59c5371 2191
4dff95dc
SB
2192 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
2193 &clk_dump_fops);
2194 if (!d)
2195 return -ENOMEM;
e59c5371 2196
4dff95dc
SB
2197 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
2198 &orphan_list, &clk_summary_fops);
2199 if (!d)
2200 return -ENOMEM;
e59c5371 2201
4dff95dc
SB
2202 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
2203 &orphan_list, &clk_dump_fops);
2204 if (!d)
2205 return -ENOMEM;
e59c5371 2206
4dff95dc
SB
2207 mutex_lock(&clk_debug_lock);
2208 hlist_for_each_entry(core, &clk_debug_list, debug_node)
2209 clk_debug_create_one(core, rootdir);
e59c5371 2210
4dff95dc
SB
2211 inited = 1;
2212 mutex_unlock(&clk_debug_lock);
e59c5371 2213
4dff95dc
SB
2214 return 0;
2215}
2216late_initcall(clk_debug_init);
2217#else
2218static inline int clk_debug_register(struct clk_core *core) { return 0; }
2219static inline void clk_debug_reparent(struct clk_core *core,
2220 struct clk_core *new_parent)
035a61c3 2221{
035a61c3 2222}
4dff95dc 2223static inline void clk_debug_unregister(struct clk_core *core)
3d3801ef 2224{
3d3801ef 2225}
4dff95dc 2226#endif
3d3801ef 2227
b2476490
MT
2228/**
2229 * __clk_init - initialize the data structures in a struct clk
2230 * @dev: device initializing this clk, placeholder for now
2231 * @clk: clk being initialized
2232 *
035a61c3 2233 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2234 * parent and rate and sets them both.
b2476490 2235 */
b09d6d99 2236static int __clk_init(struct device *dev, struct clk *clk_user)
b2476490 2237{
d1302a36 2238 int i, ret = 0;
035a61c3 2239 struct clk_core *orphan;
b67bfe0d 2240 struct hlist_node *tmp2;
d6968fca 2241 struct clk_core *core;
1c8e6004 2242 unsigned long rate;
b2476490 2243
035a61c3 2244 if (!clk_user)
d1302a36 2245 return -EINVAL;
b2476490 2246
d6968fca 2247 core = clk_user->core;
035a61c3 2248
eab89f69 2249 clk_prepare_lock();
b2476490
MT
2250
2251 /* check to see if a clock with this name is already registered */
d6968fca 2252 if (clk_core_lookup(core->name)) {
d1302a36 2253 pr_debug("%s: clk %s already initialized\n",
d6968fca 2254 __func__, core->name);
d1302a36 2255 ret = -EEXIST;
b2476490 2256 goto out;
d1302a36 2257 }
b2476490 2258
d4d7e3dd 2259 /* check that clk_ops are sane. See Documentation/clk.txt */
d6968fca
SB
2260 if (core->ops->set_rate &&
2261 !((core->ops->round_rate || core->ops->determine_rate) &&
2262 core->ops->recalc_rate)) {
71472c0c 2263 pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
d6968fca 2264 __func__, core->name);
d1302a36 2265 ret = -EINVAL;
d4d7e3dd
MT
2266 goto out;
2267 }
2268
d6968fca 2269 if (core->ops->set_parent && !core->ops->get_parent) {
d4d7e3dd 2270 pr_warning("%s: %s must implement .get_parent & .set_parent\n",
d6968fca 2271 __func__, core->name);
d1302a36 2272 ret = -EINVAL;
d4d7e3dd
MT
2273 goto out;
2274 }
2275
d6968fca
SB
2276 if (core->ops->set_rate_and_parent &&
2277 !(core->ops->set_parent && core->ops->set_rate)) {
3fa2252b 2278 pr_warn("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 2279 __func__, core->name);
3fa2252b
SB
2280 ret = -EINVAL;
2281 goto out;
2282 }
2283
b2476490 2284 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
2285 for (i = 0; i < core->num_parents; i++)
2286 WARN(!core->parent_names[i],
b2476490 2287 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 2288 __func__, core->name);
b2476490
MT
2289
2290 /*
2291 * Allocate an array of struct clk *'s to avoid unnecessary string
2292 * look-ups of clk's possible parents. This can fail for clocks passed
d6968fca 2293 * in to clk_init during early boot; thus any access to core->parents[]
b2476490
MT
2294 * must always check for a NULL pointer and try to populate it if
2295 * necessary.
2296 *
d6968fca
SB
2297 * If core->parents is not NULL we skip this entire block. This allows
2298 * for clock drivers to statically initialize core->parents.
b2476490 2299 */
d6968fca
SB
2300 if (core->num_parents > 1 && !core->parents) {
2301 core->parents = kcalloc(core->num_parents, sizeof(struct clk *),
96a7ed90 2302 GFP_KERNEL);
b2476490 2303 /*
035a61c3 2304 * clk_core_lookup returns NULL for parents that have not been
b2476490
MT
2305 * clk_init'd; thus any access to clk->parents[] must check
2306 * for a NULL pointer. We can always perform lazy lookups for
2307 * missing parents later on.
2308 */
d6968fca
SB
2309 if (core->parents)
2310 for (i = 0; i < core->num_parents; i++)
2311 core->parents[i] =
2312 clk_core_lookup(core->parent_names[i]);
b2476490
MT
2313 }
2314
d6968fca 2315 core->parent = __clk_init_parent(core);
b2476490
MT
2316
2317 /*
d6968fca 2318 * Populate core->parent if parent has already been __clk_init'd. If
b2476490
MT
2319 * parent has not yet been __clk_init'd then place clk in the orphan
2320 * list. If clk has set the CLK_IS_ROOT flag then place it in the root
2321 * clk list.
2322 *
2323 * Every time a new clk is clk_init'd then we walk the list of orphan
2324 * clocks and re-parent any that are children of the clock currently
2325 * being clk_init'd.
2326 */
d6968fca
SB
2327 if (core->parent)
2328 hlist_add_head(&core->child_node,
2329 &core->parent->children);
2330 else if (core->flags & CLK_IS_ROOT)
2331 hlist_add_head(&core->child_node, &clk_root_list);
b2476490 2332 else
d6968fca 2333 hlist_add_head(&core->child_node, &clk_orphan_list);
b2476490 2334
5279fc40
BB
2335 /*
2336 * Set clk's accuracy. The preferred method is to use
2337 * .recalc_accuracy. For simple clocks and lazy developers the default
2338 * fallback is to use the parent's accuracy. If a clock doesn't have a
2339 * parent (or is orphaned) then accuracy is set to zero (perfect
2340 * clock).
2341 */
d6968fca
SB
2342 if (core->ops->recalc_accuracy)
2343 core->accuracy = core->ops->recalc_accuracy(core->hw,
2344 __clk_get_accuracy(core->parent));
2345 else if (core->parent)
2346 core->accuracy = core->parent->accuracy;
5279fc40 2347 else
d6968fca 2348 core->accuracy = 0;
5279fc40 2349
9824cf73
MR
2350 /*
2351 * Set clk's phase.
2352 * Since a phase is by definition relative to its parent, just
2353 * query the current clock phase, or just assume it's in phase.
2354 */
d6968fca
SB
2355 if (core->ops->get_phase)
2356 core->phase = core->ops->get_phase(core->hw);
9824cf73 2357 else
d6968fca 2358 core->phase = 0;
9824cf73 2359
b2476490
MT
2360 /*
2361 * Set clk's rate. The preferred method is to use .recalc_rate. For
2362 * simple clocks and lazy developers the default fallback is to use the
2363 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2364 * then rate is set to zero.
2365 */
d6968fca
SB
2366 if (core->ops->recalc_rate)
2367 rate = core->ops->recalc_rate(core->hw,
2368 clk_core_get_rate_nolock(core->parent));
2369 else if (core->parent)
2370 rate = core->parent->rate;
b2476490 2371 else
1c8e6004 2372 rate = 0;
d6968fca 2373 core->rate = core->req_rate = rate;
b2476490
MT
2374
2375 /*
2376 * walk the list of orphan clocks and reparent any that are children of
2377 * this clock
2378 */
b67bfe0d 2379 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
12d29886 2380 if (orphan->num_parents && orphan->ops->get_parent) {
1f61e5f1 2381 i = orphan->ops->get_parent(orphan->hw);
d6968fca
SB
2382 if (!strcmp(core->name, orphan->parent_names[i]))
2383 clk_core_reparent(orphan, core);
1f61e5f1
MF
2384 continue;
2385 }
2386
b2476490 2387 for (i = 0; i < orphan->num_parents; i++)
d6968fca
SB
2388 if (!strcmp(core->name, orphan->parent_names[i])) {
2389 clk_core_reparent(orphan, core);
b2476490
MT
2390 break;
2391 }
1f61e5f1 2392 }
b2476490
MT
2393
2394 /*
2395 * optional platform-specific magic
2396 *
2397 * The .init callback is not used by any of the basic clock types, but
2398 * exists for weird hardware that must perform initialization magic.
2399 * Please consider other ways of solving initialization problems before
24ee1a08 2400 * using this callback, as its use is discouraged.
b2476490 2401 */
d6968fca
SB
2402 if (core->ops->init)
2403 core->ops->init(core->hw);
b2476490 2404
d6968fca 2405 kref_init(&core->ref);
b2476490 2406out:
eab89f69 2407 clk_prepare_unlock();
b2476490 2408
89f7e9de 2409 if (!ret)
d6968fca 2410 clk_debug_register(core);
89f7e9de 2411
d1302a36 2412 return ret;
b2476490
MT
2413}
2414
035a61c3
TV
2415struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2416 const char *con_id)
0197b3ea 2417{
0197b3ea
SK
2418 struct clk *clk;
2419
035a61c3
TV
2420 /* This is to allow this function to be chained to others */
2421 if (!hw || IS_ERR(hw))
2422 return (struct clk *) hw;
0197b3ea 2423
035a61c3
TV
2424 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2425 if (!clk)
2426 return ERR_PTR(-ENOMEM);
2427
2428 clk->core = hw->core;
2429 clk->dev_id = dev_id;
2430 clk->con_id = con_id;
1c8e6004
TV
2431 clk->max_rate = ULONG_MAX;
2432
2433 clk_prepare_lock();
50595f8b 2434 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2435 clk_prepare_unlock();
0197b3ea
SK
2436
2437 return clk;
2438}
035a61c3 2439
73e0e496 2440void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2441{
2442 clk_prepare_lock();
50595f8b 2443 hlist_del(&clk->clks_node);
1c8e6004
TV
2444 clk_prepare_unlock();
2445
2446 kfree(clk);
2447}
0197b3ea 2448
293ba3b4
SB
2449/**
2450 * clk_register - allocate a new clock, register it and return an opaque cookie
2451 * @dev: device that is registering this clock
2452 * @hw: link to hardware-specific clock data
2453 *
2454 * clk_register is the primary interface for populating the clock tree with new
2455 * clock nodes. It returns a pointer to the newly allocated struct clk which
a59a5163 2456 * cannot be dereferenced by driver code but may be used in conjunction with the
293ba3b4
SB
2457 * rest of the clock API. In the event of an error clk_register will return an
2458 * error code; drivers must test for an error code after calling clk_register.
2459 */
2460struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2461{
d1302a36 2462 int i, ret;
d6968fca 2463 struct clk_core *core;
293ba3b4 2464
d6968fca
SB
2465 core = kzalloc(sizeof(*core), GFP_KERNEL);
2466 if (!core) {
293ba3b4
SB
2467 ret = -ENOMEM;
2468 goto fail_out;
2469 }
b2476490 2470
d6968fca
SB
2471 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
2472 if (!core->name) {
0197b3ea
SK
2473 ret = -ENOMEM;
2474 goto fail_name;
2475 }
d6968fca 2476 core->ops = hw->init->ops;
ac2df527 2477 if (dev && dev->driver)
d6968fca
SB
2478 core->owner = dev->driver->owner;
2479 core->hw = hw;
2480 core->flags = hw->init->flags;
2481 core->num_parents = hw->init->num_parents;
2482 hw->core = core;
b2476490 2483
d1302a36 2484 /* allocate local copy in case parent_names is __initdata */
d6968fca 2485 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 2486 GFP_KERNEL);
d1302a36 2487
d6968fca 2488 if (!core->parent_names) {
d1302a36
MT
2489 ret = -ENOMEM;
2490 goto fail_parent_names;
2491 }
2492
2493
2494 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
2495 for (i = 0; i < core->num_parents; i++) {
2496 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2497 GFP_KERNEL);
d6968fca 2498 if (!core->parent_names[i]) {
d1302a36
MT
2499 ret = -ENOMEM;
2500 goto fail_parent_names_copy;
2501 }
2502 }
2503
d6968fca 2504 INIT_HLIST_HEAD(&core->clks);
1c8e6004 2505
035a61c3
TV
2506 hw->clk = __clk_create_clk(hw, NULL, NULL);
2507 if (IS_ERR(hw->clk)) {
035a61c3
TV
2508 ret = PTR_ERR(hw->clk);
2509 goto fail_parent_names_copy;
2510 }
2511
2512 ret = __clk_init(dev, hw->clk);
d1302a36 2513 if (!ret)
035a61c3 2514 return hw->clk;
b2476490 2515
1c8e6004 2516 __clk_free_clk(hw->clk);
035a61c3 2517 hw->clk = NULL;
b2476490 2518
d1302a36
MT
2519fail_parent_names_copy:
2520 while (--i >= 0)
d6968fca
SB
2521 kfree_const(core->parent_names[i]);
2522 kfree(core->parent_names);
d1302a36 2523fail_parent_names:
d6968fca 2524 kfree_const(core->name);
0197b3ea 2525fail_name:
d6968fca 2526 kfree(core);
d1302a36
MT
2527fail_out:
2528 return ERR_PTR(ret);
b2476490
MT
2529}
2530EXPORT_SYMBOL_GPL(clk_register);
2531
6e5ab41b 2532/* Free memory allocated for a clock. */
fcb0ee6a
SN
2533static void __clk_release(struct kref *ref)
2534{
d6968fca
SB
2535 struct clk_core *core = container_of(ref, struct clk_core, ref);
2536 int i = core->num_parents;
fcb0ee6a 2537
496eadf8
KK
2538 lockdep_assert_held(&prepare_lock);
2539
d6968fca 2540 kfree(core->parents);
fcb0ee6a 2541 while (--i >= 0)
d6968fca 2542 kfree_const(core->parent_names[i]);
fcb0ee6a 2543
d6968fca
SB
2544 kfree(core->parent_names);
2545 kfree_const(core->name);
2546 kfree(core);
fcb0ee6a
SN
2547}
2548
2549/*
2550 * Empty clk_ops for unregistered clocks. These are used temporarily
2551 * after clk_unregister() was called on a clock and until last clock
2552 * consumer calls clk_put() and the struct clk object is freed.
2553 */
2554static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2555{
2556 return -ENXIO;
2557}
2558
2559static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2560{
2561 WARN_ON_ONCE(1);
2562}
2563
2564static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2565 unsigned long parent_rate)
2566{
2567 return -ENXIO;
2568}
2569
2570static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2571{
2572 return -ENXIO;
2573}
2574
2575static const struct clk_ops clk_nodrv_ops = {
2576 .enable = clk_nodrv_prepare_enable,
2577 .disable = clk_nodrv_disable_unprepare,
2578 .prepare = clk_nodrv_prepare_enable,
2579 .unprepare = clk_nodrv_disable_unprepare,
2580 .set_rate = clk_nodrv_set_rate,
2581 .set_parent = clk_nodrv_set_parent,
2582};
2583
1df5c939
MB
2584/**
2585 * clk_unregister - unregister a currently registered clock
2586 * @clk: clock to unregister
1df5c939 2587 */
fcb0ee6a
SN
2588void clk_unregister(struct clk *clk)
2589{
2590 unsigned long flags;
2591
6314b679
SB
2592 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2593 return;
2594
035a61c3 2595 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2596
2597 clk_prepare_lock();
2598
035a61c3
TV
2599 if (clk->core->ops == &clk_nodrv_ops) {
2600 pr_err("%s: unregistered clock: %s\n", __func__,
2601 clk->core->name);
6314b679 2602 return;
fcb0ee6a
SN
2603 }
2604 /*
2605 * Assign empty clock ops for consumers that might still hold
2606 * a reference to this clock.
2607 */
2608 flags = clk_enable_lock();
035a61c3 2609 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2610 clk_enable_unlock(flags);
2611
035a61c3
TV
2612 if (!hlist_empty(&clk->core->children)) {
2613 struct clk_core *child;
874f224c 2614 struct hlist_node *t;
fcb0ee6a
SN
2615
2616 /* Reparent all children to the orphan list. */
035a61c3
TV
2617 hlist_for_each_entry_safe(child, t, &clk->core->children,
2618 child_node)
2619 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2620 }
2621
035a61c3 2622 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2623
035a61c3 2624 if (clk->core->prepare_count)
fcb0ee6a 2625 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2626 __func__, clk->core->name);
2627 kref_put(&clk->core->ref, __clk_release);
6314b679 2628
fcb0ee6a
SN
2629 clk_prepare_unlock();
2630}
1df5c939
MB
2631EXPORT_SYMBOL_GPL(clk_unregister);
2632
46c8773a
SB
2633static void devm_clk_release(struct device *dev, void *res)
2634{
293ba3b4 2635 clk_unregister(*(struct clk **)res);
46c8773a
SB
2636}
2637
2638/**
2639 * devm_clk_register - resource managed clk_register()
2640 * @dev: device that is registering this clock
2641 * @hw: link to hardware-specific clock data
2642 *
2643 * Managed clk_register(). Clocks returned from this function are
2644 * automatically clk_unregister()ed on driver detach. See clk_register() for
2645 * more information.
2646 */
2647struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2648{
2649 struct clk *clk;
293ba3b4 2650 struct clk **clkp;
46c8773a 2651
293ba3b4
SB
2652 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2653 if (!clkp)
46c8773a
SB
2654 return ERR_PTR(-ENOMEM);
2655
293ba3b4
SB
2656 clk = clk_register(dev, hw);
2657 if (!IS_ERR(clk)) {
2658 *clkp = clk;
2659 devres_add(dev, clkp);
46c8773a 2660 } else {
293ba3b4 2661 devres_free(clkp);
46c8773a
SB
2662 }
2663
2664 return clk;
2665}
2666EXPORT_SYMBOL_GPL(devm_clk_register);
2667
2668static int devm_clk_match(struct device *dev, void *res, void *data)
2669{
2670 struct clk *c = res;
2671 if (WARN_ON(!c))
2672 return 0;
2673 return c == data;
2674}
2675
2676/**
2677 * devm_clk_unregister - resource managed clk_unregister()
2678 * @clk: clock to unregister
2679 *
2680 * Deallocate a clock allocated with devm_clk_register(). Normally
2681 * this function will not need to be called and the resource management
2682 * code will ensure that the resource is freed.
2683 */
2684void devm_clk_unregister(struct device *dev, struct clk *clk)
2685{
2686 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2687}
2688EXPORT_SYMBOL_GPL(devm_clk_unregister);
2689
ac2df527
SN
2690/*
2691 * clkdev helpers
2692 */
2693int __clk_get(struct clk *clk)
2694{
035a61c3
TV
2695 struct clk_core *core = !clk ? NULL : clk->core;
2696
2697 if (core) {
2698 if (!try_module_get(core->owner))
00efcb1c 2699 return 0;
ac2df527 2700
035a61c3 2701 kref_get(&core->ref);
00efcb1c 2702 }
ac2df527
SN
2703 return 1;
2704}
2705
2706void __clk_put(struct clk *clk)
2707{
10cdfe54
TV
2708 struct module *owner;
2709
00efcb1c 2710 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2711 return;
2712
fcb0ee6a 2713 clk_prepare_lock();
1c8e6004 2714
50595f8b 2715 hlist_del(&clk->clks_node);
ec02ace8
TV
2716 if (clk->min_rate > clk->core->req_rate ||
2717 clk->max_rate < clk->core->req_rate)
2718 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2719
1c8e6004
TV
2720 owner = clk->core->owner;
2721 kref_put(&clk->core->ref, __clk_release);
2722
fcb0ee6a
SN
2723 clk_prepare_unlock();
2724
10cdfe54 2725 module_put(owner);
035a61c3 2726
035a61c3 2727 kfree(clk);
ac2df527
SN
2728}
2729
b2476490
MT
2730/*** clk rate change notifiers ***/
2731
2732/**
2733 * clk_notifier_register - add a clk rate change notifier
2734 * @clk: struct clk * to watch
2735 * @nb: struct notifier_block * with callback info
2736 *
2737 * Request notification when clk's rate changes. This uses an SRCU
2738 * notifier because we want it to block and notifier unregistrations are
2739 * uncommon. The callbacks associated with the notifier must not
2740 * re-enter into the clk framework by calling any top-level clk APIs;
2741 * this will cause a nested prepare_lock mutex.
2742 *
5324fda7
SB
2743 * In all notification cases cases (pre, post and abort rate change) the
2744 * original clock rate is passed to the callback via struct
2745 * clk_notifier_data.old_rate and the new frequency is passed via struct
b2476490
MT
2746 * clk_notifier_data.new_rate.
2747 *
b2476490
MT
2748 * clk_notifier_register() must be called from non-atomic context.
2749 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2750 * allocation failure; otherwise, passes along the return value of
2751 * srcu_notifier_chain_register().
2752 */
2753int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2754{
2755 struct clk_notifier *cn;
2756 int ret = -ENOMEM;
2757
2758 if (!clk || !nb)
2759 return -EINVAL;
2760
eab89f69 2761 clk_prepare_lock();
b2476490
MT
2762
2763 /* search the list of notifiers for this clk */
2764 list_for_each_entry(cn, &clk_notifier_list, node)
2765 if (cn->clk == clk)
2766 break;
2767
2768 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2769 if (cn->clk != clk) {
2770 cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2771 if (!cn)
2772 goto out;
2773
2774 cn->clk = clk;
2775 srcu_init_notifier_head(&cn->notifier_head);
2776
2777 list_add(&cn->node, &clk_notifier_list);
2778 }
2779
2780 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2781
035a61c3 2782 clk->core->notifier_count++;
b2476490
MT
2783
2784out:
eab89f69 2785 clk_prepare_unlock();
b2476490
MT
2786
2787 return ret;
2788}
2789EXPORT_SYMBOL_GPL(clk_notifier_register);
2790
2791/**
2792 * clk_notifier_unregister - remove a clk rate change notifier
2793 * @clk: struct clk *
2794 * @nb: struct notifier_block * with callback info
2795 *
2796 * Request no further notification for changes to 'clk' and frees memory
2797 * allocated in clk_notifier_register.
2798 *
2799 * Returns -EINVAL if called with null arguments; otherwise, passes
2800 * along the return value of srcu_notifier_chain_unregister().
2801 */
2802int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2803{
2804 struct clk_notifier *cn = NULL;
2805 int ret = -EINVAL;
2806
2807 if (!clk || !nb)
2808 return -EINVAL;
2809
eab89f69 2810 clk_prepare_lock();
b2476490
MT
2811
2812 list_for_each_entry(cn, &clk_notifier_list, node)
2813 if (cn->clk == clk)
2814 break;
2815
2816 if (cn->clk == clk) {
2817 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2818
035a61c3 2819 clk->core->notifier_count--;
b2476490
MT
2820
2821 /* XXX the notifier code should handle this better */
2822 if (!cn->notifier_head.head) {
2823 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 2824 list_del(&cn->node);
b2476490
MT
2825 kfree(cn);
2826 }
2827
2828 } else {
2829 ret = -ENOENT;
2830 }
2831
eab89f69 2832 clk_prepare_unlock();
b2476490
MT
2833
2834 return ret;
2835}
2836EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
2837
2838#ifdef CONFIG_OF
2839/**
2840 * struct of_clk_provider - Clock provider registration structure
2841 * @link: Entry in global list of clock providers
2842 * @node: Pointer to device tree node of clock provider
2843 * @get: Get clock callback. Returns NULL or a struct clk for the
2844 * given clock specifier
2845 * @data: context pointer to be passed into @get callback
2846 */
2847struct of_clk_provider {
2848 struct list_head link;
2849
2850 struct device_node *node;
2851 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
2852 void *data;
2853};
2854
f2f6c255
PG
2855static const struct of_device_id __clk_of_table_sentinel
2856 __used __section(__clk_of_table_end);
2857
766e6a4e 2858static LIST_HEAD(of_clk_providers);
d6782c26
SN
2859static DEFINE_MUTEX(of_clk_mutex);
2860
766e6a4e
GL
2861struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2862 void *data)
2863{
2864 return data;
2865}
2866EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
2867
494bfec9
SG
2868struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
2869{
2870 struct clk_onecell_data *clk_data = data;
2871 unsigned int idx = clkspec->args[0];
2872
2873 if (idx >= clk_data->clk_num) {
2874 pr_err("%s: invalid clock index %d\n", __func__, idx);
2875 return ERR_PTR(-EINVAL);
2876 }
2877
2878 return clk_data->clks[idx];
2879}
2880EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
2881
766e6a4e
GL
2882/**
2883 * of_clk_add_provider() - Register a clock provider for a node
2884 * @np: Device node pointer associated with clock provider
2885 * @clk_src_get: callback for decoding clock
2886 * @data: context pointer for @clk_src_get callback.
2887 */
2888int of_clk_add_provider(struct device_node *np,
2889 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
2890 void *data),
2891 void *data)
2892{
2893 struct of_clk_provider *cp;
86be408b 2894 int ret;
766e6a4e
GL
2895
2896 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
2897 if (!cp)
2898 return -ENOMEM;
2899
2900 cp->node = of_node_get(np);
2901 cp->data = data;
2902 cp->get = clk_src_get;
2903
d6782c26 2904 mutex_lock(&of_clk_mutex);
766e6a4e 2905 list_add(&cp->link, &of_clk_providers);
d6782c26 2906 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2907 pr_debug("Added clock from %s\n", np->full_name);
2908
86be408b
SN
2909 ret = of_clk_set_defaults(np, true);
2910 if (ret < 0)
2911 of_clk_del_provider(np);
2912
2913 return ret;
766e6a4e
GL
2914}
2915EXPORT_SYMBOL_GPL(of_clk_add_provider);
2916
2917/**
2918 * of_clk_del_provider() - Remove a previously registered clock provider
2919 * @np: Device node pointer associated with clock provider
2920 */
2921void of_clk_del_provider(struct device_node *np)
2922{
2923 struct of_clk_provider *cp;
2924
d6782c26 2925 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2926 list_for_each_entry(cp, &of_clk_providers, link) {
2927 if (cp->node == np) {
2928 list_del(&cp->link);
2929 of_node_put(cp->node);
2930 kfree(cp);
2931 break;
2932 }
2933 }
d6782c26 2934 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2935}
2936EXPORT_SYMBOL_GPL(of_clk_del_provider);
2937
73e0e496
SB
2938struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
2939 const char *dev_id, const char *con_id)
766e6a4e
GL
2940{
2941 struct of_clk_provider *provider;
a34cd466 2942 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
766e6a4e 2943
306c342f
SB
2944 if (!clkspec)
2945 return ERR_PTR(-EINVAL);
2946
766e6a4e 2947 /* Check if we have such a provider in our array */
306c342f 2948 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2949 list_for_each_entry(provider, &of_clk_providers, link) {
2950 if (provider->node == clkspec->np)
2951 clk = provider->get(clkspec, provider->data);
73e0e496
SB
2952 if (!IS_ERR(clk)) {
2953 clk = __clk_create_clk(__clk_get_hw(clk), dev_id,
2954 con_id);
2955
2956 if (!IS_ERR(clk) && !__clk_get(clk)) {
2957 __clk_free_clk(clk);
2958 clk = ERR_PTR(-ENOENT);
2959 }
2960
766e6a4e 2961 break;
73e0e496 2962 }
766e6a4e 2963 }
306c342f 2964 mutex_unlock(&of_clk_mutex);
d6782c26
SN
2965
2966 return clk;
2967}
2968
306c342f
SB
2969/**
2970 * of_clk_get_from_provider() - Lookup a clock from a clock provider
2971 * @clkspec: pointer to a clock specifier data structure
2972 *
2973 * This function looks up a struct clk from the registered list of clock
2974 * providers, an input is a clock specifier data structure as returned
2975 * from the of_parse_phandle_with_args() function call.
2976 */
d6782c26
SN
2977struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
2978{
306c342f 2979 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e
GL
2980}
2981
f6102742
MT
2982int of_clk_get_parent_count(struct device_node *np)
2983{
2984 return of_count_phandle_with_args(np, "clocks", "#clock-cells");
2985}
2986EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
2987
766e6a4e
GL
2988const char *of_clk_get_parent_name(struct device_node *np, int index)
2989{
2990 struct of_phandle_args clkspec;
7a0fc1a3 2991 struct property *prop;
766e6a4e 2992 const char *clk_name;
7a0fc1a3
BD
2993 const __be32 *vp;
2994 u32 pv;
766e6a4e 2995 int rc;
7a0fc1a3 2996 int count;
766e6a4e
GL
2997
2998 if (index < 0)
2999 return NULL;
3000
3001 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3002 &clkspec);
3003 if (rc)
3004 return NULL;
3005
7a0fc1a3
BD
3006 index = clkspec.args_count ? clkspec.args[0] : 0;
3007 count = 0;
3008
3009 /* if there is an indices property, use it to transfer the index
3010 * specified into an array offset for the clock-output-names property.
3011 */
3012 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3013 if (index == pv) {
3014 index = count;
3015 break;
3016 }
3017 count++;
3018 }
3019
766e6a4e 3020 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3021 index,
766e6a4e
GL
3022 &clk_name) < 0)
3023 clk_name = clkspec.np->name;
3024
3025 of_node_put(clkspec.np);
3026 return clk_name;
3027}
3028EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3029
2e61dfb3
DN
3030/**
3031 * of_clk_parent_fill() - Fill @parents with names of @np's parents and return
3032 * number of parents
3033 * @np: Device node pointer associated with clock provider
3034 * @parents: pointer to char array that hold the parents' names
3035 * @size: size of the @parents array
3036 *
3037 * Return: number of parents for the clock node.
3038 */
3039int of_clk_parent_fill(struct device_node *np, const char **parents,
3040 unsigned int size)
3041{
3042 unsigned int i = 0;
3043
3044 while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
3045 i++;
3046
3047 return i;
3048}
3049EXPORT_SYMBOL_GPL(of_clk_parent_fill);
3050
1771b10d
GC
3051struct clock_provider {
3052 of_clk_init_cb_t clk_init_cb;
3053 struct device_node *np;
3054 struct list_head node;
3055};
3056
3057static LIST_HEAD(clk_provider_list);
3058
3059/*
3060 * This function looks for a parent clock. If there is one, then it
3061 * checks that the provider for this parent clock was initialized, in
3062 * this case the parent clock will be ready.
3063 */
3064static int parent_ready(struct device_node *np)
3065{
3066 int i = 0;
3067
3068 while (true) {
3069 struct clk *clk = of_clk_get(np, i);
3070
3071 /* this parent is ready we can check the next one */
3072 if (!IS_ERR(clk)) {
3073 clk_put(clk);
3074 i++;
3075 continue;
3076 }
3077
3078 /* at least one parent is not ready, we exit now */
3079 if (PTR_ERR(clk) == -EPROBE_DEFER)
3080 return 0;
3081
3082 /*
3083 * Here we make assumption that the device tree is
3084 * written correctly. So an error means that there is
3085 * no more parent. As we didn't exit yet, then the
3086 * previous parent are ready. If there is no clock
3087 * parent, no need to wait for them, then we can
3088 * consider their absence as being ready
3089 */
3090 return 1;
3091 }
3092}
3093
766e6a4e
GL
3094/**
3095 * of_clk_init() - Scan and init clock providers from the DT
3096 * @matches: array of compatible values and init functions for providers.
3097 *
1771b10d 3098 * This function scans the device tree for matching clock providers
e5ca8fb4 3099 * and calls their initialization functions. It also does it by trying
1771b10d 3100 * to follow the dependencies.
766e6a4e
GL
3101 */
3102void __init of_clk_init(const struct of_device_id *matches)
3103{
7f7ed584 3104 const struct of_device_id *match;
766e6a4e 3105 struct device_node *np;
1771b10d
GC
3106 struct clock_provider *clk_provider, *next;
3107 bool is_init_done;
3108 bool force = false;
766e6a4e 3109
f2f6c255 3110 if (!matches)
819b4861 3111 matches = &__clk_of_table;
f2f6c255 3112
1771b10d 3113 /* First prepare the list of the clocks providers */
7f7ed584 3114 for_each_matching_node_and_match(np, matches, &match) {
1771b10d
GC
3115 struct clock_provider *parent =
3116 kzalloc(sizeof(struct clock_provider), GFP_KERNEL);
3117
3118 parent->clk_init_cb = match->data;
3119 parent->np = np;
3f6d439f 3120 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3121 }
3122
3123 while (!list_empty(&clk_provider_list)) {
3124 is_init_done = false;
3125 list_for_each_entry_safe(clk_provider, next,
3126 &clk_provider_list, node) {
3127 if (force || parent_ready(clk_provider->np)) {
86be408b 3128
1771b10d 3129 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3130 of_clk_set_defaults(clk_provider->np, true);
3131
1771b10d
GC
3132 list_del(&clk_provider->node);
3133 kfree(clk_provider);
3134 is_init_done = true;
3135 }
3136 }
3137
3138 /*
e5ca8fb4 3139 * We didn't manage to initialize any of the
1771b10d
GC
3140 * remaining providers during the last loop, so now we
3141 * initialize all the remaining ones unconditionally
3142 * in case the clock parent was not mandatory
3143 */
3144 if (!is_init_done)
3145 force = true;
766e6a4e
GL
3146 }
3147}
3148#endif
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