Merge tag 'pwm/for-4.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry...
[deliverable/linux.git] / drivers / clk / clk.c
CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
3c373117 12#include <linux/clk.h>
b09d6d99 13#include <linux/clk-provider.h>
86be408b 14#include <linux/clk/clk-conf.h>
b2476490
MT
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/spinlock.h>
18#include <linux/err.h>
19#include <linux/list.h>
20#include <linux/slab.h>
766e6a4e 21#include <linux/of.h>
46c8773a 22#include <linux/device.h>
f2f6c255 23#include <linux/init.h>
533ddeb1 24#include <linux/sched.h>
562ef0b0 25#include <linux/clkdev.h>
b2476490 26
d6782c26
SN
27#include "clk.h"
28
b2476490
MT
29static DEFINE_SPINLOCK(enable_lock);
30static DEFINE_MUTEX(prepare_lock);
31
533ddeb1
MT
32static struct task_struct *prepare_owner;
33static struct task_struct *enable_owner;
34
35static int prepare_refcnt;
36static int enable_refcnt;
37
b2476490
MT
38static HLIST_HEAD(clk_root_list);
39static HLIST_HEAD(clk_orphan_list);
40static LIST_HEAD(clk_notifier_list);
41
b09d6d99
MT
42/*** private data structures ***/
43
44struct clk_core {
45 const char *name;
46 const struct clk_ops *ops;
47 struct clk_hw *hw;
48 struct module *owner;
49 struct clk_core *parent;
50 const char **parent_names;
51 struct clk_core **parents;
52 u8 num_parents;
53 u8 new_parent_index;
54 unsigned long rate;
1c8e6004 55 unsigned long req_rate;
b09d6d99
MT
56 unsigned long new_rate;
57 struct clk_core *new_parent;
58 struct clk_core *new_child;
59 unsigned long flags;
e6500344 60 bool orphan;
b09d6d99
MT
61 unsigned int enable_count;
62 unsigned int prepare_count;
9783c0d9
SB
63 unsigned long min_rate;
64 unsigned long max_rate;
b09d6d99
MT
65 unsigned long accuracy;
66 int phase;
67 struct hlist_head children;
68 struct hlist_node child_node;
1c8e6004 69 struct hlist_head clks;
b09d6d99
MT
70 unsigned int notifier_count;
71#ifdef CONFIG_DEBUG_FS
72 struct dentry *dentry;
8c9a8a8f 73 struct hlist_node debug_node;
b09d6d99
MT
74#endif
75 struct kref ref;
76};
77
dfc202ea
SB
78#define CREATE_TRACE_POINTS
79#include <trace/events/clk.h>
80
b09d6d99
MT
81struct clk {
82 struct clk_core *core;
83 const char *dev_id;
84 const char *con_id;
1c8e6004
TV
85 unsigned long min_rate;
86 unsigned long max_rate;
50595f8b 87 struct hlist_node clks_node;
b09d6d99
MT
88};
89
eab89f69
MT
90/*** locking ***/
91static void clk_prepare_lock(void)
92{
533ddeb1
MT
93 if (!mutex_trylock(&prepare_lock)) {
94 if (prepare_owner == current) {
95 prepare_refcnt++;
96 return;
97 }
98 mutex_lock(&prepare_lock);
99 }
100 WARN_ON_ONCE(prepare_owner != NULL);
101 WARN_ON_ONCE(prepare_refcnt != 0);
102 prepare_owner = current;
103 prepare_refcnt = 1;
eab89f69
MT
104}
105
106static void clk_prepare_unlock(void)
107{
533ddeb1
MT
108 WARN_ON_ONCE(prepare_owner != current);
109 WARN_ON_ONCE(prepare_refcnt == 0);
110
111 if (--prepare_refcnt)
112 return;
113 prepare_owner = NULL;
eab89f69
MT
114 mutex_unlock(&prepare_lock);
115}
116
117static unsigned long clk_enable_lock(void)
a57aa185 118 __acquires(enable_lock)
eab89f69
MT
119{
120 unsigned long flags;
533ddeb1
MT
121
122 if (!spin_trylock_irqsave(&enable_lock, flags)) {
123 if (enable_owner == current) {
124 enable_refcnt++;
a57aa185 125 __acquire(enable_lock);
533ddeb1
MT
126 return flags;
127 }
128 spin_lock_irqsave(&enable_lock, flags);
129 }
130 WARN_ON_ONCE(enable_owner != NULL);
131 WARN_ON_ONCE(enable_refcnt != 0);
132 enable_owner = current;
133 enable_refcnt = 1;
eab89f69
MT
134 return flags;
135}
136
137static void clk_enable_unlock(unsigned long flags)
a57aa185 138 __releases(enable_lock)
eab89f69 139{
533ddeb1
MT
140 WARN_ON_ONCE(enable_owner != current);
141 WARN_ON_ONCE(enable_refcnt == 0);
142
a57aa185
SB
143 if (--enable_refcnt) {
144 __release(enable_lock);
533ddeb1 145 return;
a57aa185 146 }
533ddeb1 147 enable_owner = NULL;
eab89f69
MT
148 spin_unlock_irqrestore(&enable_lock, flags);
149}
150
4dff95dc
SB
151static bool clk_core_is_prepared(struct clk_core *core)
152{
153 /*
154 * .is_prepared is optional for clocks that can prepare
155 * fall back to software usage counter if it is missing
156 */
157 if (!core->ops->is_prepared)
158 return core->prepare_count;
b2476490 159
4dff95dc
SB
160 return core->ops->is_prepared(core->hw);
161}
b2476490 162
4dff95dc
SB
163static bool clk_core_is_enabled(struct clk_core *core)
164{
165 /*
166 * .is_enabled is only mandatory for clocks that gate
167 * fall back to software usage counter if .is_enabled is missing
168 */
169 if (!core->ops->is_enabled)
170 return core->enable_count;
6b44c854 171
4dff95dc
SB
172 return core->ops->is_enabled(core->hw);
173}
6b44c854 174
4dff95dc 175static void clk_unprepare_unused_subtree(struct clk_core *core)
1af599df 176{
4dff95dc
SB
177 struct clk_core *child;
178
179 lockdep_assert_held(&prepare_lock);
180
181 hlist_for_each_entry(child, &core->children, child_node)
182 clk_unprepare_unused_subtree(child);
183
184 if (core->prepare_count)
1af599df
PG
185 return;
186
4dff95dc
SB
187 if (core->flags & CLK_IGNORE_UNUSED)
188 return;
189
190 if (clk_core_is_prepared(core)) {
191 trace_clk_unprepare(core);
192 if (core->ops->unprepare_unused)
193 core->ops->unprepare_unused(core->hw);
194 else if (core->ops->unprepare)
195 core->ops->unprepare(core->hw);
196 trace_clk_unprepare_complete(core);
197 }
1af599df
PG
198}
199
4dff95dc 200static void clk_disable_unused_subtree(struct clk_core *core)
1af599df 201{
035a61c3 202 struct clk_core *child;
4dff95dc 203 unsigned long flags;
1af599df 204
4dff95dc 205 lockdep_assert_held(&prepare_lock);
1af599df 206
4dff95dc
SB
207 hlist_for_each_entry(child, &core->children, child_node)
208 clk_disable_unused_subtree(child);
1af599df 209
4dff95dc
SB
210 flags = clk_enable_lock();
211
212 if (core->enable_count)
213 goto unlock_out;
214
215 if (core->flags & CLK_IGNORE_UNUSED)
216 goto unlock_out;
217
218 /*
219 * some gate clocks have special needs during the disable-unused
220 * sequence. call .disable_unused if available, otherwise fall
221 * back to .disable
222 */
223 if (clk_core_is_enabled(core)) {
224 trace_clk_disable(core);
225 if (core->ops->disable_unused)
226 core->ops->disable_unused(core->hw);
227 else if (core->ops->disable)
228 core->ops->disable(core->hw);
229 trace_clk_disable_complete(core);
230 }
231
232unlock_out:
233 clk_enable_unlock(flags);
1af599df
PG
234}
235
4dff95dc
SB
236static bool clk_ignore_unused;
237static int __init clk_ignore_unused_setup(char *__unused)
1af599df 238{
4dff95dc
SB
239 clk_ignore_unused = true;
240 return 1;
241}
242__setup("clk_ignore_unused", clk_ignore_unused_setup);
1af599df 243
4dff95dc
SB
244static int clk_disable_unused(void)
245{
246 struct clk_core *core;
247
248 if (clk_ignore_unused) {
249 pr_warn("clk: Not disabling unused clocks\n");
250 return 0;
251 }
1af599df 252
eab89f69 253 clk_prepare_lock();
1af599df 254
4dff95dc
SB
255 hlist_for_each_entry(core, &clk_root_list, child_node)
256 clk_disable_unused_subtree(core);
257
258 hlist_for_each_entry(core, &clk_orphan_list, child_node)
259 clk_disable_unused_subtree(core);
260
261 hlist_for_each_entry(core, &clk_root_list, child_node)
262 clk_unprepare_unused_subtree(core);
263
264 hlist_for_each_entry(core, &clk_orphan_list, child_node)
265 clk_unprepare_unused_subtree(core);
1af599df 266
eab89f69 267 clk_prepare_unlock();
1af599df
PG
268
269 return 0;
270}
4dff95dc 271late_initcall_sync(clk_disable_unused);
1af599df 272
4dff95dc 273/*** helper functions ***/
1af599df 274
b76281cb 275const char *__clk_get_name(const struct clk *clk)
1af599df 276{
4dff95dc 277 return !clk ? NULL : clk->core->name;
1af599df 278}
4dff95dc 279EXPORT_SYMBOL_GPL(__clk_get_name);
1af599df 280
e7df6f6e 281const char *clk_hw_get_name(const struct clk_hw *hw)
1a9c069c
SB
282{
283 return hw->core->name;
284}
285EXPORT_SYMBOL_GPL(clk_hw_get_name);
286
4dff95dc
SB
287struct clk_hw *__clk_get_hw(struct clk *clk)
288{
289 return !clk ? NULL : clk->core->hw;
290}
291EXPORT_SYMBOL_GPL(__clk_get_hw);
1af599df 292
e7df6f6e 293unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
1a9c069c
SB
294{
295 return hw->core->num_parents;
296}
297EXPORT_SYMBOL_GPL(clk_hw_get_num_parents);
298
e7df6f6e 299struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
1a9c069c
SB
300{
301 return hw->core->parent ? hw->core->parent->hw : NULL;
302}
303EXPORT_SYMBOL_GPL(clk_hw_get_parent);
304
4dff95dc
SB
305static struct clk_core *__clk_lookup_subtree(const char *name,
306 struct clk_core *core)
bddca894 307{
035a61c3 308 struct clk_core *child;
4dff95dc 309 struct clk_core *ret;
bddca894 310
4dff95dc
SB
311 if (!strcmp(core->name, name))
312 return core;
bddca894 313
4dff95dc
SB
314 hlist_for_each_entry(child, &core->children, child_node) {
315 ret = __clk_lookup_subtree(name, child);
316 if (ret)
317 return ret;
bddca894
PG
318 }
319
4dff95dc 320 return NULL;
bddca894
PG
321}
322
4dff95dc 323static struct clk_core *clk_core_lookup(const char *name)
bddca894 324{
4dff95dc
SB
325 struct clk_core *root_clk;
326 struct clk_core *ret;
bddca894 327
4dff95dc
SB
328 if (!name)
329 return NULL;
bddca894 330
4dff95dc
SB
331 /* search the 'proper' clk tree first */
332 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
333 ret = __clk_lookup_subtree(name, root_clk);
334 if (ret)
335 return ret;
bddca894
PG
336 }
337
4dff95dc
SB
338 /* if not found, then search the orphan tree */
339 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
340 ret = __clk_lookup_subtree(name, root_clk);
341 if (ret)
342 return ret;
343 }
bddca894 344
4dff95dc 345 return NULL;
bddca894
PG
346}
347
4dff95dc
SB
348static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
349 u8 index)
bddca894 350{
4dff95dc
SB
351 if (!core || index >= core->num_parents)
352 return NULL;
88cfbef2
MY
353
354 if (!core->parents[index])
355 core->parents[index] =
356 clk_core_lookup(core->parent_names[index]);
357
358 return core->parents[index];
bddca894
PG
359}
360
e7df6f6e
SB
361struct clk_hw *
362clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
1a9c069c
SB
363{
364 struct clk_core *parent;
365
366 parent = clk_core_get_parent_by_index(hw->core, index);
367
368 return !parent ? NULL : parent->hw;
369}
370EXPORT_SYMBOL_GPL(clk_hw_get_parent_by_index);
371
4dff95dc
SB
372unsigned int __clk_get_enable_count(struct clk *clk)
373{
374 return !clk ? 0 : clk->core->enable_count;
375}
b2476490 376
4dff95dc
SB
377static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
378{
379 unsigned long ret;
b2476490 380
4dff95dc
SB
381 if (!core) {
382 ret = 0;
383 goto out;
384 }
b2476490 385
4dff95dc 386 ret = core->rate;
b2476490 387
47b0eeb3 388 if (!core->num_parents)
4dff95dc 389 goto out;
c646cbf1 390
4dff95dc
SB
391 if (!core->parent)
392 ret = 0;
b2476490 393
b2476490
MT
394out:
395 return ret;
396}
397
e7df6f6e 398unsigned long clk_hw_get_rate(const struct clk_hw *hw)
1a9c069c
SB
399{
400 return clk_core_get_rate_nolock(hw->core);
401}
402EXPORT_SYMBOL_GPL(clk_hw_get_rate);
403
4dff95dc
SB
404static unsigned long __clk_get_accuracy(struct clk_core *core)
405{
406 if (!core)
407 return 0;
b2476490 408
4dff95dc 409 return core->accuracy;
b2476490
MT
410}
411
4dff95dc 412unsigned long __clk_get_flags(struct clk *clk)
fcb0ee6a 413{
4dff95dc 414 return !clk ? 0 : clk->core->flags;
fcb0ee6a 415}
4dff95dc 416EXPORT_SYMBOL_GPL(__clk_get_flags);
fcb0ee6a 417
e7df6f6e 418unsigned long clk_hw_get_flags(const struct clk_hw *hw)
1a9c069c
SB
419{
420 return hw->core->flags;
421}
422EXPORT_SYMBOL_GPL(clk_hw_get_flags);
423
e7df6f6e 424bool clk_hw_is_prepared(const struct clk_hw *hw)
1a9c069c
SB
425{
426 return clk_core_is_prepared(hw->core);
427}
428
be68bf88
JE
429bool clk_hw_is_enabled(const struct clk_hw *hw)
430{
431 return clk_core_is_enabled(hw->core);
432}
433
4dff95dc 434bool __clk_is_enabled(struct clk *clk)
b2476490 435{
4dff95dc
SB
436 if (!clk)
437 return false;
b2476490 438
4dff95dc
SB
439 return clk_core_is_enabled(clk->core);
440}
441EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 442
4dff95dc
SB
443static bool mux_is_better_rate(unsigned long rate, unsigned long now,
444 unsigned long best, unsigned long flags)
445{
446 if (flags & CLK_MUX_ROUND_CLOSEST)
447 return abs(now - rate) < abs(best - rate);
1af599df 448
4dff95dc
SB
449 return now <= rate && now > best;
450}
bddca894 451
0817b62c
BB
452static int
453clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
4dff95dc
SB
454 unsigned long flags)
455{
456 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
0817b62c
BB
457 int i, num_parents, ret;
458 unsigned long best = 0;
459 struct clk_rate_request parent_req = *req;
b2476490 460
4dff95dc
SB
461 /* if NO_REPARENT flag set, pass through to current parent */
462 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
463 parent = core->parent;
0817b62c
BB
464 if (core->flags & CLK_SET_RATE_PARENT) {
465 ret = __clk_determine_rate(parent ? parent->hw : NULL,
466 &parent_req);
467 if (ret)
468 return ret;
469
470 best = parent_req.rate;
471 } else if (parent) {
4dff95dc 472 best = clk_core_get_rate_nolock(parent);
0817b62c 473 } else {
4dff95dc 474 best = clk_core_get_rate_nolock(core);
0817b62c
BB
475 }
476
4dff95dc
SB
477 goto out;
478 }
b2476490 479
4dff95dc
SB
480 /* find the parent that can provide the fastest rate <= rate */
481 num_parents = core->num_parents;
482 for (i = 0; i < num_parents; i++) {
483 parent = clk_core_get_parent_by_index(core, i);
484 if (!parent)
485 continue;
0817b62c
BB
486
487 if (core->flags & CLK_SET_RATE_PARENT) {
488 parent_req = *req;
489 ret = __clk_determine_rate(parent->hw, &parent_req);
490 if (ret)
491 continue;
492 } else {
493 parent_req.rate = clk_core_get_rate_nolock(parent);
494 }
495
496 if (mux_is_better_rate(req->rate, parent_req.rate,
497 best, flags)) {
4dff95dc 498 best_parent = parent;
0817b62c 499 best = parent_req.rate;
4dff95dc
SB
500 }
501 }
b2476490 502
57d866e6
BB
503 if (!best_parent)
504 return -EINVAL;
505
4dff95dc
SB
506out:
507 if (best_parent)
0817b62c
BB
508 req->best_parent_hw = best_parent->hw;
509 req->best_parent_rate = best;
510 req->rate = best;
b2476490 511
0817b62c 512 return 0;
b33d212f 513}
4dff95dc
SB
514
515struct clk *__clk_lookup(const char *name)
fcb0ee6a 516{
4dff95dc
SB
517 struct clk_core *core = clk_core_lookup(name);
518
519 return !core ? NULL : core->hw->clk;
fcb0ee6a 520}
b2476490 521
4dff95dc
SB
522static void clk_core_get_boundaries(struct clk_core *core,
523 unsigned long *min_rate,
524 unsigned long *max_rate)
1c155b3d 525{
4dff95dc 526 struct clk *clk_user;
1c155b3d 527
9783c0d9
SB
528 *min_rate = core->min_rate;
529 *max_rate = core->max_rate;
496eadf8 530
4dff95dc
SB
531 hlist_for_each_entry(clk_user, &core->clks, clks_node)
532 *min_rate = max(*min_rate, clk_user->min_rate);
1c155b3d 533
4dff95dc
SB
534 hlist_for_each_entry(clk_user, &core->clks, clks_node)
535 *max_rate = min(*max_rate, clk_user->max_rate);
536}
1c155b3d 537
9783c0d9
SB
538void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
539 unsigned long max_rate)
540{
541 hw->core->min_rate = min_rate;
542 hw->core->max_rate = max_rate;
543}
544EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
545
4dff95dc
SB
546/*
547 * Helper for finding best parent to provide a given frequency. This can be used
548 * directly as a determine_rate callback (e.g. for a mux), or from a more
549 * complex clock that may combine a mux with other operations.
550 */
0817b62c
BB
551int __clk_mux_determine_rate(struct clk_hw *hw,
552 struct clk_rate_request *req)
4dff95dc 553{
0817b62c 554 return clk_mux_determine_rate_flags(hw, req, 0);
1c155b3d 555}
4dff95dc 556EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
1c155b3d 557
0817b62c
BB
558int __clk_mux_determine_rate_closest(struct clk_hw *hw,
559 struct clk_rate_request *req)
b2476490 560{
0817b62c 561 return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
4dff95dc
SB
562}
563EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
b2476490 564
4dff95dc 565/*** clk api ***/
496eadf8 566
4dff95dc
SB
567static void clk_core_unprepare(struct clk_core *core)
568{
a6334725
SB
569 lockdep_assert_held(&prepare_lock);
570
4dff95dc
SB
571 if (!core)
572 return;
b2476490 573
4dff95dc
SB
574 if (WARN_ON(core->prepare_count == 0))
575 return;
b2476490 576
4dff95dc
SB
577 if (--core->prepare_count > 0)
578 return;
b2476490 579
4dff95dc 580 WARN_ON(core->enable_count > 0);
b2476490 581
4dff95dc 582 trace_clk_unprepare(core);
b2476490 583
4dff95dc
SB
584 if (core->ops->unprepare)
585 core->ops->unprepare(core->hw);
586
587 trace_clk_unprepare_complete(core);
588 clk_core_unprepare(core->parent);
b2476490
MT
589}
590
4dff95dc
SB
591/**
592 * clk_unprepare - undo preparation of a clock source
593 * @clk: the clk being unprepared
594 *
595 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
596 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
597 * if the operation may sleep. One example is a clk which is accessed over
598 * I2c. In the complex case a clk gate operation may require a fast and a slow
599 * part. It is this reason that clk_unprepare and clk_disable are not mutually
600 * exclusive. In fact clk_disable must be called before clk_unprepare.
601 */
602void clk_unprepare(struct clk *clk)
1e435256 603{
4dff95dc
SB
604 if (IS_ERR_OR_NULL(clk))
605 return;
606
607 clk_prepare_lock();
608 clk_core_unprepare(clk->core);
609 clk_prepare_unlock();
1e435256 610}
4dff95dc 611EXPORT_SYMBOL_GPL(clk_unprepare);
1e435256 612
4dff95dc 613static int clk_core_prepare(struct clk_core *core)
b2476490 614{
4dff95dc 615 int ret = 0;
b2476490 616
a6334725
SB
617 lockdep_assert_held(&prepare_lock);
618
4dff95dc 619 if (!core)
1e435256 620 return 0;
1e435256 621
4dff95dc
SB
622 if (core->prepare_count == 0) {
623 ret = clk_core_prepare(core->parent);
624 if (ret)
625 return ret;
b2476490 626
4dff95dc 627 trace_clk_prepare(core);
b2476490 628
4dff95dc
SB
629 if (core->ops->prepare)
630 ret = core->ops->prepare(core->hw);
b2476490 631
4dff95dc 632 trace_clk_prepare_complete(core);
1c155b3d 633
4dff95dc
SB
634 if (ret) {
635 clk_core_unprepare(core->parent);
636 return ret;
637 }
638 }
1c155b3d 639
4dff95dc 640 core->prepare_count++;
b2476490
MT
641
642 return 0;
643}
b2476490 644
4dff95dc
SB
645/**
646 * clk_prepare - prepare a clock source
647 * @clk: the clk being prepared
648 *
649 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
650 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
651 * operation may sleep. One example is a clk which is accessed over I2c. In
652 * the complex case a clk ungate operation may require a fast and a slow part.
653 * It is this reason that clk_prepare and clk_enable are not mutually
654 * exclusive. In fact clk_prepare must be called before clk_enable.
655 * Returns 0 on success, -EERROR otherwise.
656 */
657int clk_prepare(struct clk *clk)
b2476490 658{
4dff95dc 659 int ret;
b2476490 660
4dff95dc
SB
661 if (!clk)
662 return 0;
b2476490 663
4dff95dc
SB
664 clk_prepare_lock();
665 ret = clk_core_prepare(clk->core);
666 clk_prepare_unlock();
667
668 return ret;
b2476490 669}
4dff95dc 670EXPORT_SYMBOL_GPL(clk_prepare);
b2476490 671
4dff95dc 672static void clk_core_disable(struct clk_core *core)
b2476490 673{
a6334725
SB
674 lockdep_assert_held(&enable_lock);
675
4dff95dc
SB
676 if (!core)
677 return;
035a61c3 678
4dff95dc
SB
679 if (WARN_ON(core->enable_count == 0))
680 return;
b2476490 681
4dff95dc
SB
682 if (--core->enable_count > 0)
683 return;
035a61c3 684
4dff95dc 685 trace_clk_disable(core);
035a61c3 686
4dff95dc
SB
687 if (core->ops->disable)
688 core->ops->disable(core->hw);
035a61c3 689
4dff95dc 690 trace_clk_disable_complete(core);
035a61c3 691
4dff95dc 692 clk_core_disable(core->parent);
035a61c3 693}
7ef3dcc8 694
4dff95dc
SB
695/**
696 * clk_disable - gate a clock
697 * @clk: the clk being gated
698 *
699 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
700 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
701 * clk if the operation is fast and will never sleep. One example is a
702 * SoC-internal clk which is controlled via simple register writes. In the
703 * complex case a clk gate operation may require a fast and a slow part. It is
704 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
705 * In fact clk_disable must be called before clk_unprepare.
706 */
707void clk_disable(struct clk *clk)
b2476490 708{
4dff95dc
SB
709 unsigned long flags;
710
711 if (IS_ERR_OR_NULL(clk))
712 return;
713
714 flags = clk_enable_lock();
715 clk_core_disable(clk->core);
716 clk_enable_unlock(flags);
b2476490 717}
4dff95dc 718EXPORT_SYMBOL_GPL(clk_disable);
b2476490 719
4dff95dc 720static int clk_core_enable(struct clk_core *core)
b2476490 721{
4dff95dc 722 int ret = 0;
b2476490 723
a6334725
SB
724 lockdep_assert_held(&enable_lock);
725
4dff95dc
SB
726 if (!core)
727 return 0;
b2476490 728
4dff95dc
SB
729 if (WARN_ON(core->prepare_count == 0))
730 return -ESHUTDOWN;
b2476490 731
4dff95dc
SB
732 if (core->enable_count == 0) {
733 ret = clk_core_enable(core->parent);
b2476490 734
4dff95dc
SB
735 if (ret)
736 return ret;
b2476490 737
4dff95dc 738 trace_clk_enable(core);
035a61c3 739
4dff95dc
SB
740 if (core->ops->enable)
741 ret = core->ops->enable(core->hw);
035a61c3 742
4dff95dc
SB
743 trace_clk_enable_complete(core);
744
745 if (ret) {
746 clk_core_disable(core->parent);
747 return ret;
748 }
749 }
750
751 core->enable_count++;
752 return 0;
035a61c3 753}
b2476490 754
4dff95dc
SB
755/**
756 * clk_enable - ungate a clock
757 * @clk: the clk being ungated
758 *
759 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
760 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
761 * if the operation will never sleep. One example is a SoC-internal clk which
762 * is controlled via simple register writes. In the complex case a clk ungate
763 * operation may require a fast and a slow part. It is this reason that
764 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
765 * must be called before clk_enable. Returns 0 on success, -EERROR
766 * otherwise.
767 */
768int clk_enable(struct clk *clk)
5279fc40 769{
4dff95dc
SB
770 unsigned long flags;
771 int ret;
772
773 if (!clk)
5279fc40
BB
774 return 0;
775
4dff95dc
SB
776 flags = clk_enable_lock();
777 ret = clk_core_enable(clk->core);
778 clk_enable_unlock(flags);
5279fc40 779
4dff95dc 780 return ret;
b2476490 781}
4dff95dc 782EXPORT_SYMBOL_GPL(clk_enable);
b2476490 783
0817b62c
BB
784static int clk_core_round_rate_nolock(struct clk_core *core,
785 struct clk_rate_request *req)
3d6ee287 786{
4dff95dc 787 struct clk_core *parent;
0817b62c 788 long rate;
4dff95dc
SB
789
790 lockdep_assert_held(&prepare_lock);
3d6ee287 791
d6968fca 792 if (!core)
4dff95dc 793 return 0;
3d6ee287 794
4dff95dc 795 parent = core->parent;
0817b62c
BB
796 if (parent) {
797 req->best_parent_hw = parent->hw;
798 req->best_parent_rate = parent->rate;
799 } else {
800 req->best_parent_hw = NULL;
801 req->best_parent_rate = 0;
802 }
3d6ee287 803
4dff95dc 804 if (core->ops->determine_rate) {
0817b62c
BB
805 return core->ops->determine_rate(core->hw, req);
806 } else if (core->ops->round_rate) {
807 rate = core->ops->round_rate(core->hw, req->rate,
808 &req->best_parent_rate);
809 if (rate < 0)
810 return rate;
811
812 req->rate = rate;
813 } else if (core->flags & CLK_SET_RATE_PARENT) {
814 return clk_core_round_rate_nolock(parent, req);
815 } else {
816 req->rate = core->rate;
817 }
818
819 return 0;
3d6ee287
UH
820}
821
4dff95dc
SB
822/**
823 * __clk_determine_rate - get the closest rate actually supported by a clock
824 * @hw: determine the rate of this clock
825 * @rate: target rate
826 * @min_rate: returned rate must be greater than this rate
827 * @max_rate: returned rate must be less than this rate
828 *
6e5ab41b 829 * Useful for clk_ops such as .set_rate and .determine_rate.
4dff95dc 830 */
0817b62c 831int __clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
035a61c3 832{
0817b62c
BB
833 if (!hw) {
834 req->rate = 0;
4dff95dc 835 return 0;
0817b62c 836 }
035a61c3 837
0817b62c 838 return clk_core_round_rate_nolock(hw->core, req);
035a61c3 839}
4dff95dc 840EXPORT_SYMBOL_GPL(__clk_determine_rate);
035a61c3 841
1a9c069c
SB
842unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
843{
844 int ret;
845 struct clk_rate_request req;
846
847 clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);
848 req.rate = rate;
849
850 ret = clk_core_round_rate_nolock(hw->core, &req);
851 if (ret)
852 return 0;
853
854 return req.rate;
855}
856EXPORT_SYMBOL_GPL(clk_hw_round_rate);
857
4dff95dc
SB
858/**
859 * clk_round_rate - round the given rate for a clk
860 * @clk: the clk for which we are rounding a rate
861 * @rate: the rate which is to be rounded
862 *
863 * Takes in a rate as input and rounds it to a rate that the clk can actually
864 * use which is then returned. If clk doesn't support round_rate operation
865 * then the parent rate is returned.
866 */
867long clk_round_rate(struct clk *clk, unsigned long rate)
035a61c3 868{
fc4a05d4
SB
869 struct clk_rate_request req;
870 int ret;
4dff95dc 871
035a61c3 872 if (!clk)
4dff95dc 873 return 0;
035a61c3 874
4dff95dc 875 clk_prepare_lock();
fc4a05d4
SB
876
877 clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
878 req.rate = rate;
879
880 ret = clk_core_round_rate_nolock(clk->core, &req);
4dff95dc
SB
881 clk_prepare_unlock();
882
fc4a05d4
SB
883 if (ret)
884 return ret;
885
886 return req.rate;
035a61c3 887}
4dff95dc 888EXPORT_SYMBOL_GPL(clk_round_rate);
b2476490 889
4dff95dc
SB
890/**
891 * __clk_notify - call clk notifier chain
892 * @core: clk that is changing rate
893 * @msg: clk notifier type (see include/linux/clk.h)
894 * @old_rate: old clk rate
895 * @new_rate: new clk rate
896 *
897 * Triggers a notifier call chain on the clk rate-change notification
898 * for 'clk'. Passes a pointer to the struct clk and the previous
899 * and current rates to the notifier callback. Intended to be called by
900 * internal clock code only. Returns NOTIFY_DONE from the last driver
901 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
902 * a driver returns that.
903 */
904static int __clk_notify(struct clk_core *core, unsigned long msg,
905 unsigned long old_rate, unsigned long new_rate)
b2476490 906{
4dff95dc
SB
907 struct clk_notifier *cn;
908 struct clk_notifier_data cnd;
909 int ret = NOTIFY_DONE;
b2476490 910
4dff95dc
SB
911 cnd.old_rate = old_rate;
912 cnd.new_rate = new_rate;
b2476490 913
4dff95dc
SB
914 list_for_each_entry(cn, &clk_notifier_list, node) {
915 if (cn->clk->core == core) {
916 cnd.clk = cn->clk;
917 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
918 &cnd);
919 }
b2476490
MT
920 }
921
4dff95dc 922 return ret;
b2476490
MT
923}
924
4dff95dc
SB
925/**
926 * __clk_recalc_accuracies
927 * @core: first clk in the subtree
928 *
929 * Walks the subtree of clks starting with clk and recalculates accuracies as
930 * it goes. Note that if a clk does not implement the .recalc_accuracy
6e5ab41b 931 * callback then it is assumed that the clock will take on the accuracy of its
4dff95dc 932 * parent.
4dff95dc
SB
933 */
934static void __clk_recalc_accuracies(struct clk_core *core)
b2476490 935{
4dff95dc
SB
936 unsigned long parent_accuracy = 0;
937 struct clk_core *child;
b2476490 938
4dff95dc 939 lockdep_assert_held(&prepare_lock);
b2476490 940
4dff95dc
SB
941 if (core->parent)
942 parent_accuracy = core->parent->accuracy;
b2476490 943
4dff95dc
SB
944 if (core->ops->recalc_accuracy)
945 core->accuracy = core->ops->recalc_accuracy(core->hw,
946 parent_accuracy);
947 else
948 core->accuracy = parent_accuracy;
b2476490 949
4dff95dc
SB
950 hlist_for_each_entry(child, &core->children, child_node)
951 __clk_recalc_accuracies(child);
b2476490
MT
952}
953
4dff95dc 954static long clk_core_get_accuracy(struct clk_core *core)
e366fdd7 955{
4dff95dc 956 unsigned long accuracy;
15a02c1f 957
4dff95dc
SB
958 clk_prepare_lock();
959 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
960 __clk_recalc_accuracies(core);
15a02c1f 961
4dff95dc
SB
962 accuracy = __clk_get_accuracy(core);
963 clk_prepare_unlock();
e366fdd7 964
4dff95dc 965 return accuracy;
e366fdd7 966}
15a02c1f 967
4dff95dc
SB
968/**
969 * clk_get_accuracy - return the accuracy of clk
970 * @clk: the clk whose accuracy is being returned
971 *
972 * Simply returns the cached accuracy of the clk, unless
973 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
974 * issued.
975 * If clk is NULL then returns 0.
976 */
977long clk_get_accuracy(struct clk *clk)
035a61c3 978{
4dff95dc
SB
979 if (!clk)
980 return 0;
035a61c3 981
4dff95dc 982 return clk_core_get_accuracy(clk->core);
035a61c3 983}
4dff95dc 984EXPORT_SYMBOL_GPL(clk_get_accuracy);
035a61c3 985
4dff95dc
SB
986static unsigned long clk_recalc(struct clk_core *core,
987 unsigned long parent_rate)
1c8e6004 988{
4dff95dc
SB
989 if (core->ops->recalc_rate)
990 return core->ops->recalc_rate(core->hw, parent_rate);
991 return parent_rate;
1c8e6004
TV
992}
993
4dff95dc
SB
994/**
995 * __clk_recalc_rates
996 * @core: first clk in the subtree
997 * @msg: notification type (see include/linux/clk.h)
998 *
999 * Walks the subtree of clks starting with clk and recalculates rates as it
1000 * goes. Note that if a clk does not implement the .recalc_rate callback then
1001 * it is assumed that the clock will take on the rate of its parent.
1002 *
1003 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1004 * if necessary.
15a02c1f 1005 */
4dff95dc 1006static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
15a02c1f 1007{
4dff95dc
SB
1008 unsigned long old_rate;
1009 unsigned long parent_rate = 0;
1010 struct clk_core *child;
e366fdd7 1011
4dff95dc 1012 lockdep_assert_held(&prepare_lock);
15a02c1f 1013
4dff95dc 1014 old_rate = core->rate;
b2476490 1015
4dff95dc
SB
1016 if (core->parent)
1017 parent_rate = core->parent->rate;
b2476490 1018
4dff95dc 1019 core->rate = clk_recalc(core, parent_rate);
b2476490 1020
4dff95dc
SB
1021 /*
1022 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1023 * & ABORT_RATE_CHANGE notifiers
1024 */
1025 if (core->notifier_count && msg)
1026 __clk_notify(core, msg, old_rate, core->rate);
b2476490 1027
4dff95dc
SB
1028 hlist_for_each_entry(child, &core->children, child_node)
1029 __clk_recalc_rates(child, msg);
1030}
b2476490 1031
4dff95dc
SB
1032static unsigned long clk_core_get_rate(struct clk_core *core)
1033{
1034 unsigned long rate;
dfc202ea 1035
4dff95dc 1036 clk_prepare_lock();
b2476490 1037
4dff95dc
SB
1038 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1039 __clk_recalc_rates(core, 0);
1040
1041 rate = clk_core_get_rate_nolock(core);
1042 clk_prepare_unlock();
1043
1044 return rate;
b2476490
MT
1045}
1046
1047/**
4dff95dc
SB
1048 * clk_get_rate - return the rate of clk
1049 * @clk: the clk whose rate is being returned
b2476490 1050 *
4dff95dc
SB
1051 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1052 * is set, which means a recalc_rate will be issued.
1053 * If clk is NULL then returns 0.
b2476490 1054 */
4dff95dc 1055unsigned long clk_get_rate(struct clk *clk)
b2476490 1056{
4dff95dc
SB
1057 if (!clk)
1058 return 0;
63589e92 1059
4dff95dc 1060 return clk_core_get_rate(clk->core);
b2476490 1061}
4dff95dc 1062EXPORT_SYMBOL_GPL(clk_get_rate);
b2476490 1063
4dff95dc
SB
1064static int clk_fetch_parent_index(struct clk_core *core,
1065 struct clk_core *parent)
b2476490 1066{
4dff95dc 1067 int i;
b2476490 1068
508f884a
MY
1069 if (!parent)
1070 return -EINVAL;
1071
470b5e2f
MY
1072 for (i = 0; i < core->num_parents; i++)
1073 if (clk_core_get_parent_by_index(core, i) == parent)
4dff95dc 1074 return i;
b2476490 1075
4dff95dc 1076 return -EINVAL;
b2476490
MT
1077}
1078
e6500344
HS
1079/*
1080 * Update the orphan status of @core and all its children.
1081 */
1082static void clk_core_update_orphan_status(struct clk_core *core, bool is_orphan)
1083{
1084 struct clk_core *child;
1085
1086 core->orphan = is_orphan;
1087
1088 hlist_for_each_entry(child, &core->children, child_node)
1089 clk_core_update_orphan_status(child, is_orphan);
1090}
1091
4dff95dc 1092static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
b2476490 1093{
e6500344
HS
1094 bool was_orphan = core->orphan;
1095
4dff95dc 1096 hlist_del(&core->child_node);
035a61c3 1097
4dff95dc 1098 if (new_parent) {
e6500344
HS
1099 bool becomes_orphan = new_parent->orphan;
1100
4dff95dc
SB
1101 /* avoid duplicate POST_RATE_CHANGE notifications */
1102 if (new_parent->new_child == core)
1103 new_parent->new_child = NULL;
b2476490 1104
4dff95dc 1105 hlist_add_head(&core->child_node, &new_parent->children);
e6500344
HS
1106
1107 if (was_orphan != becomes_orphan)
1108 clk_core_update_orphan_status(core, becomes_orphan);
4dff95dc
SB
1109 } else {
1110 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
1111 if (!was_orphan)
1112 clk_core_update_orphan_status(core, true);
4dff95dc 1113 }
dfc202ea 1114
4dff95dc 1115 core->parent = new_parent;
035a61c3
TV
1116}
1117
4dff95dc
SB
1118static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1119 struct clk_core *parent)
b2476490
MT
1120{
1121 unsigned long flags;
4dff95dc 1122 struct clk_core *old_parent = core->parent;
b2476490 1123
4dff95dc
SB
1124 /*
1125 * Migrate prepare state between parents and prevent race with
1126 * clk_enable().
1127 *
1128 * If the clock is not prepared, then a race with
1129 * clk_enable/disable() is impossible since we already have the
1130 * prepare lock (future calls to clk_enable() need to be preceded by
1131 * a clk_prepare()).
1132 *
1133 * If the clock is prepared, migrate the prepared state to the new
1134 * parent and also protect against a race with clk_enable() by
1135 * forcing the clock and the new parent on. This ensures that all
1136 * future calls to clk_enable() are practically NOPs with respect to
1137 * hardware and software states.
1138 *
1139 * See also: Comment for clk_set_parent() below.
1140 */
1141 if (core->prepare_count) {
1142 clk_core_prepare(parent);
d2a5d46b 1143 flags = clk_enable_lock();
4dff95dc
SB
1144 clk_core_enable(parent);
1145 clk_core_enable(core);
d2a5d46b 1146 clk_enable_unlock(flags);
4dff95dc 1147 }
63589e92 1148
4dff95dc 1149 /* update the clk tree topology */
eab89f69 1150 flags = clk_enable_lock();
4dff95dc 1151 clk_reparent(core, parent);
eab89f69 1152 clk_enable_unlock(flags);
4dff95dc
SB
1153
1154 return old_parent;
b2476490 1155}
b2476490 1156
4dff95dc
SB
1157static void __clk_set_parent_after(struct clk_core *core,
1158 struct clk_core *parent,
1159 struct clk_core *old_parent)
b2476490 1160{
d2a5d46b
DA
1161 unsigned long flags;
1162
4dff95dc
SB
1163 /*
1164 * Finish the migration of prepare state and undo the changes done
1165 * for preventing a race with clk_enable().
1166 */
1167 if (core->prepare_count) {
d2a5d46b 1168 flags = clk_enable_lock();
4dff95dc
SB
1169 clk_core_disable(core);
1170 clk_core_disable(old_parent);
d2a5d46b 1171 clk_enable_unlock(flags);
4dff95dc
SB
1172 clk_core_unprepare(old_parent);
1173 }
1174}
b2476490 1175
4dff95dc
SB
1176static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
1177 u8 p_index)
1178{
1179 unsigned long flags;
1180 int ret = 0;
1181 struct clk_core *old_parent;
b2476490 1182
4dff95dc 1183 old_parent = __clk_set_parent_before(core, parent);
b2476490 1184
4dff95dc 1185 trace_clk_set_parent(core, parent);
b2476490 1186
4dff95dc
SB
1187 /* change clock input source */
1188 if (parent && core->ops->set_parent)
1189 ret = core->ops->set_parent(core->hw, p_index);
dfc202ea 1190
4dff95dc 1191 trace_clk_set_parent_complete(core, parent);
dfc202ea 1192
4dff95dc
SB
1193 if (ret) {
1194 flags = clk_enable_lock();
1195 clk_reparent(core, old_parent);
1196 clk_enable_unlock(flags);
c660b2eb 1197 __clk_set_parent_after(core, old_parent, parent);
dfc202ea 1198
4dff95dc 1199 return ret;
b2476490
MT
1200 }
1201
4dff95dc
SB
1202 __clk_set_parent_after(core, parent, old_parent);
1203
b2476490
MT
1204 return 0;
1205}
1206
1207/**
4dff95dc
SB
1208 * __clk_speculate_rates
1209 * @core: first clk in the subtree
1210 * @parent_rate: the "future" rate of clk's parent
b2476490 1211 *
4dff95dc
SB
1212 * Walks the subtree of clks starting with clk, speculating rates as it
1213 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1214 *
1215 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1216 * pre-rate change notifications and returns early if no clks in the
1217 * subtree have subscribed to the notifications. Note that if a clk does not
1218 * implement the .recalc_rate callback then it is assumed that the clock will
1219 * take on the rate of its parent.
b2476490 1220 */
4dff95dc
SB
1221static int __clk_speculate_rates(struct clk_core *core,
1222 unsigned long parent_rate)
b2476490 1223{
4dff95dc
SB
1224 struct clk_core *child;
1225 unsigned long new_rate;
1226 int ret = NOTIFY_DONE;
b2476490 1227
4dff95dc 1228 lockdep_assert_held(&prepare_lock);
864e160a 1229
4dff95dc
SB
1230 new_rate = clk_recalc(core, parent_rate);
1231
1232 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1233 if (core->notifier_count)
1234 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
1235
1236 if (ret & NOTIFY_STOP_MASK) {
1237 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1238 __func__, core->name, ret);
1239 goto out;
1240 }
1241
1242 hlist_for_each_entry(child, &core->children, child_node) {
1243 ret = __clk_speculate_rates(child, new_rate);
1244 if (ret & NOTIFY_STOP_MASK)
1245 break;
1246 }
b2476490 1247
4dff95dc 1248out:
b2476490
MT
1249 return ret;
1250}
b2476490 1251
4dff95dc
SB
1252static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
1253 struct clk_core *new_parent, u8 p_index)
b2476490 1254{
4dff95dc 1255 struct clk_core *child;
b2476490 1256
4dff95dc
SB
1257 core->new_rate = new_rate;
1258 core->new_parent = new_parent;
1259 core->new_parent_index = p_index;
1260 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1261 core->new_child = NULL;
1262 if (new_parent && new_parent != core->parent)
1263 new_parent->new_child = core;
496eadf8 1264
4dff95dc
SB
1265 hlist_for_each_entry(child, &core->children, child_node) {
1266 child->new_rate = clk_recalc(child, new_rate);
1267 clk_calc_subtree(child, child->new_rate, NULL, 0);
1268 }
1269}
b2476490 1270
4dff95dc
SB
1271/*
1272 * calculate the new rates returning the topmost clock that has to be
1273 * changed.
1274 */
1275static struct clk_core *clk_calc_new_rates(struct clk_core *core,
1276 unsigned long rate)
1277{
1278 struct clk_core *top = core;
1279 struct clk_core *old_parent, *parent;
4dff95dc
SB
1280 unsigned long best_parent_rate = 0;
1281 unsigned long new_rate;
1282 unsigned long min_rate;
1283 unsigned long max_rate;
1284 int p_index = 0;
1285 long ret;
1286
1287 /* sanity */
1288 if (IS_ERR_OR_NULL(core))
1289 return NULL;
1290
1291 /* save parent rate, if it exists */
1292 parent = old_parent = core->parent;
71472c0c 1293 if (parent)
4dff95dc 1294 best_parent_rate = parent->rate;
71472c0c 1295
4dff95dc
SB
1296 clk_core_get_boundaries(core, &min_rate, &max_rate);
1297
1298 /* find the closest rate and parent clk/rate */
d6968fca 1299 if (core->ops->determine_rate) {
0817b62c
BB
1300 struct clk_rate_request req;
1301
1302 req.rate = rate;
1303 req.min_rate = min_rate;
1304 req.max_rate = max_rate;
1305 if (parent) {
1306 req.best_parent_hw = parent->hw;
1307 req.best_parent_rate = parent->rate;
1308 } else {
1309 req.best_parent_hw = NULL;
1310 req.best_parent_rate = 0;
1311 }
1312
1313 ret = core->ops->determine_rate(core->hw, &req);
4dff95dc
SB
1314 if (ret < 0)
1315 return NULL;
1c8e6004 1316
0817b62c
BB
1317 best_parent_rate = req.best_parent_rate;
1318 new_rate = req.rate;
1319 parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
4dff95dc
SB
1320 } else if (core->ops->round_rate) {
1321 ret = core->ops->round_rate(core->hw, rate,
0817b62c 1322 &best_parent_rate);
4dff95dc
SB
1323 if (ret < 0)
1324 return NULL;
035a61c3 1325
4dff95dc
SB
1326 new_rate = ret;
1327 if (new_rate < min_rate || new_rate > max_rate)
1328 return NULL;
1329 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
1330 /* pass-through clock without adjustable parent */
1331 core->new_rate = core->rate;
1332 return NULL;
1333 } else {
1334 /* pass-through clock with adjustable parent */
1335 top = clk_calc_new_rates(parent, rate);
1336 new_rate = parent->new_rate;
1337 goto out;
1338 }
1c8e6004 1339
4dff95dc
SB
1340 /* some clocks must be gated to change parent */
1341 if (parent != old_parent &&
1342 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1343 pr_debug("%s: %s not gated but wants to reparent\n",
1344 __func__, core->name);
1345 return NULL;
1346 }
b2476490 1347
4dff95dc
SB
1348 /* try finding the new parent index */
1349 if (parent && core->num_parents > 1) {
1350 p_index = clk_fetch_parent_index(core, parent);
1351 if (p_index < 0) {
1352 pr_debug("%s: clk %s can not be parent of clk %s\n",
1353 __func__, parent->name, core->name);
1354 return NULL;
1355 }
1356 }
b2476490 1357
4dff95dc
SB
1358 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
1359 best_parent_rate != parent->rate)
1360 top = clk_calc_new_rates(parent, best_parent_rate);
035a61c3 1361
4dff95dc
SB
1362out:
1363 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490 1364
4dff95dc 1365 return top;
b2476490 1366}
b2476490 1367
4dff95dc
SB
1368/*
1369 * Notify about rate changes in a subtree. Always walk down the whole tree
1370 * so that in case of an error we can walk down the whole tree again and
1371 * abort the change.
b2476490 1372 */
4dff95dc
SB
1373static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
1374 unsigned long event)
b2476490 1375{
4dff95dc 1376 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1377 int ret = NOTIFY_DONE;
1378
4dff95dc
SB
1379 if (core->rate == core->new_rate)
1380 return NULL;
b2476490 1381
4dff95dc
SB
1382 if (core->notifier_count) {
1383 ret = __clk_notify(core, event, core->rate, core->new_rate);
1384 if (ret & NOTIFY_STOP_MASK)
1385 fail_clk = core;
b2476490
MT
1386 }
1387
4dff95dc
SB
1388 hlist_for_each_entry(child, &core->children, child_node) {
1389 /* Skip children who will be reparented to another clock */
1390 if (child->new_parent && child->new_parent != core)
1391 continue;
1392 tmp_clk = clk_propagate_rate_change(child, event);
1393 if (tmp_clk)
1394 fail_clk = tmp_clk;
1395 }
5279fc40 1396
4dff95dc
SB
1397 /* handle the new child who might not be in core->children yet */
1398 if (core->new_child) {
1399 tmp_clk = clk_propagate_rate_change(core->new_child, event);
1400 if (tmp_clk)
1401 fail_clk = tmp_clk;
1402 }
5279fc40 1403
4dff95dc 1404 return fail_clk;
5279fc40
BB
1405}
1406
4dff95dc
SB
1407/*
1408 * walk down a subtree and set the new rates notifying the rate
1409 * change on the way
1410 */
1411static void clk_change_rate(struct clk_core *core)
035a61c3 1412{
4dff95dc
SB
1413 struct clk_core *child;
1414 struct hlist_node *tmp;
1415 unsigned long old_rate;
1416 unsigned long best_parent_rate = 0;
1417 bool skip_set_rate = false;
1418 struct clk_core *old_parent;
035a61c3 1419
4dff95dc 1420 old_rate = core->rate;
035a61c3 1421
4dff95dc
SB
1422 if (core->new_parent)
1423 best_parent_rate = core->new_parent->rate;
1424 else if (core->parent)
1425 best_parent_rate = core->parent->rate;
035a61c3 1426
2eb8c710
HS
1427 if (core->flags & CLK_SET_RATE_UNGATE) {
1428 unsigned long flags;
1429
1430 clk_core_prepare(core);
1431 flags = clk_enable_lock();
1432 clk_core_enable(core);
1433 clk_enable_unlock(flags);
1434 }
1435
4dff95dc
SB
1436 if (core->new_parent && core->new_parent != core->parent) {
1437 old_parent = __clk_set_parent_before(core, core->new_parent);
1438 trace_clk_set_parent(core, core->new_parent);
5279fc40 1439
4dff95dc
SB
1440 if (core->ops->set_rate_and_parent) {
1441 skip_set_rate = true;
1442 core->ops->set_rate_and_parent(core->hw, core->new_rate,
1443 best_parent_rate,
1444 core->new_parent_index);
1445 } else if (core->ops->set_parent) {
1446 core->ops->set_parent(core->hw, core->new_parent_index);
1447 }
5279fc40 1448
4dff95dc
SB
1449 trace_clk_set_parent_complete(core, core->new_parent);
1450 __clk_set_parent_after(core, core->new_parent, old_parent);
1451 }
8f2c2db1 1452
4dff95dc 1453 trace_clk_set_rate(core, core->new_rate);
b2476490 1454
4dff95dc
SB
1455 if (!skip_set_rate && core->ops->set_rate)
1456 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
496eadf8 1457
4dff95dc 1458 trace_clk_set_rate_complete(core, core->new_rate);
b2476490 1459
4dff95dc 1460 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1461
2eb8c710
HS
1462 if (core->flags & CLK_SET_RATE_UNGATE) {
1463 unsigned long flags;
1464
1465 flags = clk_enable_lock();
1466 clk_core_disable(core);
1467 clk_enable_unlock(flags);
1468 clk_core_unprepare(core);
1469 }
1470
4dff95dc
SB
1471 if (core->notifier_count && old_rate != core->rate)
1472 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1473
85e88fab
MT
1474 if (core->flags & CLK_RECALC_NEW_RATES)
1475 (void)clk_calc_new_rates(core, core->new_rate);
d8d91987 1476
b2476490 1477 /*
4dff95dc
SB
1478 * Use safe iteration, as change_rate can actually swap parents
1479 * for certain clock types.
b2476490 1480 */
4dff95dc
SB
1481 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
1482 /* Skip children who will be reparented to another clock */
1483 if (child->new_parent && child->new_parent != core)
1484 continue;
1485 clk_change_rate(child);
1486 }
b2476490 1487
4dff95dc
SB
1488 /* handle the new child who might not be in core->children yet */
1489 if (core->new_child)
1490 clk_change_rate(core->new_child);
b2476490
MT
1491}
1492
4dff95dc
SB
1493static int clk_core_set_rate_nolock(struct clk_core *core,
1494 unsigned long req_rate)
a093bde2 1495{
4dff95dc
SB
1496 struct clk_core *top, *fail_clk;
1497 unsigned long rate = req_rate;
1498 int ret = 0;
a093bde2 1499
4dff95dc
SB
1500 if (!core)
1501 return 0;
a093bde2 1502
4dff95dc
SB
1503 /* bail early if nothing to do */
1504 if (rate == clk_core_get_rate_nolock(core))
1505 return 0;
a093bde2 1506
4dff95dc
SB
1507 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1508 return -EBUSY;
a093bde2 1509
4dff95dc
SB
1510 /* calculate new rates and get the topmost changed clock */
1511 top = clk_calc_new_rates(core, rate);
1512 if (!top)
1513 return -EINVAL;
1514
1515 /* notify that we are about to change rates */
1516 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1517 if (fail_clk) {
1518 pr_debug("%s: failed to set %s rate\n", __func__,
1519 fail_clk->name);
1520 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1521 return -EBUSY;
1522 }
1523
1524 /* change the rates */
1525 clk_change_rate(top);
1526
1527 core->req_rate = req_rate;
1528
1529 return ret;
a093bde2 1530}
035a61c3
TV
1531
1532/**
4dff95dc
SB
1533 * clk_set_rate - specify a new rate for clk
1534 * @clk: the clk whose rate is being changed
1535 * @rate: the new rate for clk
035a61c3 1536 *
4dff95dc
SB
1537 * In the simplest case clk_set_rate will only adjust the rate of clk.
1538 *
1539 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1540 * propagate up to clk's parent; whether or not this happens depends on the
1541 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1542 * after calling .round_rate then upstream parent propagation is ignored. If
1543 * *parent_rate comes back with a new rate for clk's parent then we propagate
1544 * up to clk's parent and set its rate. Upward propagation will continue
1545 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1546 * .round_rate stops requesting changes to clk's parent_rate.
1547 *
1548 * Rate changes are accomplished via tree traversal that also recalculates the
1549 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
1550 *
1551 * Returns 0 on success, -EERROR otherwise.
035a61c3 1552 */
4dff95dc 1553int clk_set_rate(struct clk *clk, unsigned long rate)
035a61c3 1554{
4dff95dc
SB
1555 int ret;
1556
035a61c3
TV
1557 if (!clk)
1558 return 0;
1559
4dff95dc
SB
1560 /* prevent racing with updates to the clock topology */
1561 clk_prepare_lock();
da0f0b2c 1562
4dff95dc 1563 ret = clk_core_set_rate_nolock(clk->core, rate);
da0f0b2c 1564
4dff95dc 1565 clk_prepare_unlock();
4935b22c 1566
4dff95dc 1567 return ret;
4935b22c 1568}
4dff95dc 1569EXPORT_SYMBOL_GPL(clk_set_rate);
4935b22c 1570
4dff95dc
SB
1571/**
1572 * clk_set_rate_range - set a rate range for a clock source
1573 * @clk: clock source
1574 * @min: desired minimum clock rate in Hz, inclusive
1575 * @max: desired maximum clock rate in Hz, inclusive
1576 *
1577 * Returns success (0) or negative errno.
1578 */
1579int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
4935b22c 1580{
4dff95dc 1581 int ret = 0;
4935b22c 1582
4dff95dc
SB
1583 if (!clk)
1584 return 0;
903efc55 1585
4dff95dc
SB
1586 if (min > max) {
1587 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1588 __func__, clk->core->name, clk->dev_id, clk->con_id,
1589 min, max);
1590 return -EINVAL;
903efc55 1591 }
4935b22c 1592
4dff95dc 1593 clk_prepare_lock();
4935b22c 1594
4dff95dc
SB
1595 if (min != clk->min_rate || max != clk->max_rate) {
1596 clk->min_rate = min;
1597 clk->max_rate = max;
1598 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
4935b22c
JH
1599 }
1600
4dff95dc 1601 clk_prepare_unlock();
4935b22c 1602
4dff95dc 1603 return ret;
3fa2252b 1604}
4dff95dc 1605EXPORT_SYMBOL_GPL(clk_set_rate_range);
3fa2252b 1606
4dff95dc
SB
1607/**
1608 * clk_set_min_rate - set a minimum clock rate for a clock source
1609 * @clk: clock source
1610 * @rate: desired minimum clock rate in Hz, inclusive
1611 *
1612 * Returns success (0) or negative errno.
1613 */
1614int clk_set_min_rate(struct clk *clk, unsigned long rate)
3fa2252b 1615{
4dff95dc
SB
1616 if (!clk)
1617 return 0;
1618
1619 return clk_set_rate_range(clk, rate, clk->max_rate);
3fa2252b 1620}
4dff95dc 1621EXPORT_SYMBOL_GPL(clk_set_min_rate);
3fa2252b 1622
4dff95dc
SB
1623/**
1624 * clk_set_max_rate - set a maximum clock rate for a clock source
1625 * @clk: clock source
1626 * @rate: desired maximum clock rate in Hz, inclusive
1627 *
1628 * Returns success (0) or negative errno.
1629 */
1630int clk_set_max_rate(struct clk *clk, unsigned long rate)
3fa2252b 1631{
4dff95dc
SB
1632 if (!clk)
1633 return 0;
4935b22c 1634
4dff95dc 1635 return clk_set_rate_range(clk, clk->min_rate, rate);
4935b22c 1636}
4dff95dc 1637EXPORT_SYMBOL_GPL(clk_set_max_rate);
4935b22c 1638
b2476490 1639/**
4dff95dc
SB
1640 * clk_get_parent - return the parent of a clk
1641 * @clk: the clk whose parent gets returned
b2476490 1642 *
4dff95dc 1643 * Simply returns clk->parent. Returns NULL if clk is NULL.
b2476490 1644 */
4dff95dc 1645struct clk *clk_get_parent(struct clk *clk)
b2476490 1646{
4dff95dc 1647 struct clk *parent;
b2476490 1648
fc4a05d4
SB
1649 if (!clk)
1650 return NULL;
1651
4dff95dc 1652 clk_prepare_lock();
fc4a05d4
SB
1653 /* TODO: Create a per-user clk and change callers to call clk_put */
1654 parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
4dff95dc 1655 clk_prepare_unlock();
496eadf8 1656
4dff95dc
SB
1657 return parent;
1658}
1659EXPORT_SYMBOL_GPL(clk_get_parent);
b2476490 1660
4dff95dc
SB
1661static struct clk_core *__clk_init_parent(struct clk_core *core)
1662{
5146e0b0 1663 u8 index = 0;
4dff95dc 1664
2430a94d 1665 if (core->num_parents > 1 && core->ops->get_parent)
5146e0b0 1666 index = core->ops->get_parent(core->hw);
b2476490 1667
5146e0b0 1668 return clk_core_get_parent_by_index(core, index);
b2476490
MT
1669}
1670
4dff95dc
SB
1671static void clk_core_reparent(struct clk_core *core,
1672 struct clk_core *new_parent)
b2476490 1673{
4dff95dc
SB
1674 clk_reparent(core, new_parent);
1675 __clk_recalc_accuracies(core);
1676 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
1677}
1678
42c86547
TV
1679void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
1680{
1681 if (!hw)
1682 return;
1683
1684 clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
1685}
1686
4dff95dc
SB
1687/**
1688 * clk_has_parent - check if a clock is a possible parent for another
1689 * @clk: clock source
1690 * @parent: parent clock source
1691 *
1692 * This function can be used in drivers that need to check that a clock can be
1693 * the parent of another without actually changing the parent.
1694 *
1695 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 1696 */
4dff95dc 1697bool clk_has_parent(struct clk *clk, struct clk *parent)
b2476490 1698{
4dff95dc
SB
1699 struct clk_core *core, *parent_core;
1700 unsigned int i;
b2476490 1701
4dff95dc
SB
1702 /* NULL clocks should be nops, so return success if either is NULL. */
1703 if (!clk || !parent)
1704 return true;
7452b219 1705
4dff95dc
SB
1706 core = clk->core;
1707 parent_core = parent->core;
71472c0c 1708
4dff95dc
SB
1709 /* Optimize for the case where the parent is already the parent. */
1710 if (core->parent == parent_core)
1711 return true;
1c8e6004 1712
4dff95dc
SB
1713 for (i = 0; i < core->num_parents; i++)
1714 if (strcmp(core->parent_names[i], parent_core->name) == 0)
1715 return true;
03bc10ab 1716
4dff95dc
SB
1717 return false;
1718}
1719EXPORT_SYMBOL_GPL(clk_has_parent);
03bc10ab 1720
4dff95dc
SB
1721static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1722{
1723 int ret = 0;
1724 int p_index = 0;
1725 unsigned long p_rate = 0;
1726
1727 if (!core)
1728 return 0;
1729
1730 /* prevent racing with updates to the clock topology */
1731 clk_prepare_lock();
1732
1733 if (core->parent == parent)
1734 goto out;
1735
1736 /* verify ops for for multi-parent clks */
1737 if ((core->num_parents > 1) && (!core->ops->set_parent)) {
1738 ret = -ENOSYS;
63f5c3b2 1739 goto out;
7452b219
MT
1740 }
1741
4dff95dc
SB
1742 /* check that we are allowed to re-parent if the clock is in use */
1743 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1744 ret = -EBUSY;
1745 goto out;
b2476490
MT
1746 }
1747
71472c0c 1748 /* try finding the new parent index */
4dff95dc 1749 if (parent) {
d6968fca 1750 p_index = clk_fetch_parent_index(core, parent);
f1c8b2ed 1751 if (p_index < 0) {
71472c0c 1752 pr_debug("%s: clk %s can not be parent of clk %s\n",
4dff95dc
SB
1753 __func__, parent->name, core->name);
1754 ret = p_index;
1755 goto out;
71472c0c 1756 }
e8f0e68e 1757 p_rate = parent->rate;
b2476490
MT
1758 }
1759
4dff95dc
SB
1760 /* propagate PRE_RATE_CHANGE notifications */
1761 ret = __clk_speculate_rates(core, p_rate);
b2476490 1762
4dff95dc
SB
1763 /* abort if a driver objects */
1764 if (ret & NOTIFY_STOP_MASK)
1765 goto out;
b2476490 1766
4dff95dc
SB
1767 /* do the re-parent */
1768 ret = __clk_set_parent(core, parent, p_index);
b2476490 1769
4dff95dc
SB
1770 /* propagate rate an accuracy recalculation accordingly */
1771 if (ret) {
1772 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
1773 } else {
1774 __clk_recalc_rates(core, POST_RATE_CHANGE);
1775 __clk_recalc_accuracies(core);
b2476490
MT
1776 }
1777
4dff95dc
SB
1778out:
1779 clk_prepare_unlock();
71472c0c 1780
4dff95dc
SB
1781 return ret;
1782}
b2476490 1783
4dff95dc
SB
1784/**
1785 * clk_set_parent - switch the parent of a mux clk
1786 * @clk: the mux clk whose input we are switching
1787 * @parent: the new input to clk
1788 *
1789 * Re-parent clk to use parent as its new input source. If clk is in
1790 * prepared state, the clk will get enabled for the duration of this call. If
1791 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1792 * that, the reparenting is glitchy in hardware, etc), use the
1793 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1794 *
1795 * After successfully changing clk's parent clk_set_parent will update the
1796 * clk topology, sysfs topology and propagate rate recalculation via
1797 * __clk_recalc_rates.
1798 *
1799 * Returns 0 on success, -EERROR otherwise.
1800 */
1801int clk_set_parent(struct clk *clk, struct clk *parent)
1802{
1803 if (!clk)
1804 return 0;
1805
1806 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
b2476490 1807}
4dff95dc 1808EXPORT_SYMBOL_GPL(clk_set_parent);
b2476490 1809
4dff95dc
SB
1810/**
1811 * clk_set_phase - adjust the phase shift of a clock signal
1812 * @clk: clock signal source
1813 * @degrees: number of degrees the signal is shifted
1814 *
1815 * Shifts the phase of a clock signal by the specified
1816 * degrees. Returns 0 on success, -EERROR otherwise.
1817 *
1818 * This function makes no distinction about the input or reference
1819 * signal that we adjust the clock signal phase against. For example
1820 * phase locked-loop clock signal generators we may shift phase with
1821 * respect to feedback clock signal input, but for other cases the
1822 * clock phase may be shifted with respect to some other, unspecified
1823 * signal.
1824 *
1825 * Additionally the concept of phase shift does not propagate through
1826 * the clock tree hierarchy, which sets it apart from clock rates and
1827 * clock accuracy. A parent clock phase attribute does not have an
1828 * impact on the phase attribute of a child clock.
b2476490 1829 */
4dff95dc 1830int clk_set_phase(struct clk *clk, int degrees)
b2476490 1831{
4dff95dc 1832 int ret = -EINVAL;
b2476490 1833
4dff95dc
SB
1834 if (!clk)
1835 return 0;
b2476490 1836
4dff95dc
SB
1837 /* sanity check degrees */
1838 degrees %= 360;
1839 if (degrees < 0)
1840 degrees += 360;
bf47b4fd 1841
4dff95dc 1842 clk_prepare_lock();
3fa2252b 1843
023bd716
SL
1844 /* bail early if nothing to do */
1845 if (degrees == clk->core->phase)
1846 goto out;
1847
4dff95dc 1848 trace_clk_set_phase(clk->core, degrees);
3fa2252b 1849
4dff95dc
SB
1850 if (clk->core->ops->set_phase)
1851 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
3fa2252b 1852
4dff95dc 1853 trace_clk_set_phase_complete(clk->core, degrees);
dfc202ea 1854
4dff95dc
SB
1855 if (!ret)
1856 clk->core->phase = degrees;
b2476490 1857
023bd716 1858out:
4dff95dc 1859 clk_prepare_unlock();
dfc202ea 1860
4dff95dc
SB
1861 return ret;
1862}
1863EXPORT_SYMBOL_GPL(clk_set_phase);
b2476490 1864
4dff95dc
SB
1865static int clk_core_get_phase(struct clk_core *core)
1866{
1867 int ret;
b2476490 1868
4dff95dc
SB
1869 clk_prepare_lock();
1870 ret = core->phase;
1871 clk_prepare_unlock();
71472c0c 1872
4dff95dc 1873 return ret;
b2476490
MT
1874}
1875
4dff95dc
SB
1876/**
1877 * clk_get_phase - return the phase shift of a clock signal
1878 * @clk: clock signal source
1879 *
1880 * Returns the phase shift of a clock node in degrees, otherwise returns
1881 * -EERROR.
1882 */
1883int clk_get_phase(struct clk *clk)
1c8e6004 1884{
4dff95dc 1885 if (!clk)
1c8e6004
TV
1886 return 0;
1887
4dff95dc
SB
1888 return clk_core_get_phase(clk->core);
1889}
1890EXPORT_SYMBOL_GPL(clk_get_phase);
1c8e6004 1891
4dff95dc
SB
1892/**
1893 * clk_is_match - check if two clk's point to the same hardware clock
1894 * @p: clk compared against q
1895 * @q: clk compared against p
1896 *
1897 * Returns true if the two struct clk pointers both point to the same hardware
1898 * clock node. Put differently, returns true if struct clk *p and struct clk *q
1899 * share the same struct clk_core object.
1900 *
1901 * Returns false otherwise. Note that two NULL clks are treated as matching.
1902 */
1903bool clk_is_match(const struct clk *p, const struct clk *q)
1904{
1905 /* trivial case: identical struct clk's or both NULL */
1906 if (p == q)
1907 return true;
1c8e6004 1908
3fe003f9 1909 /* true if clk->core pointers match. Avoid dereferencing garbage */
4dff95dc
SB
1910 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
1911 if (p->core == q->core)
1912 return true;
1c8e6004 1913
4dff95dc
SB
1914 return false;
1915}
1916EXPORT_SYMBOL_GPL(clk_is_match);
1c8e6004 1917
4dff95dc 1918/*** debugfs support ***/
1c8e6004 1919
4dff95dc
SB
1920#ifdef CONFIG_DEBUG_FS
1921#include <linux/debugfs.h>
1c8e6004 1922
4dff95dc
SB
1923static struct dentry *rootdir;
1924static int inited = 0;
1925static DEFINE_MUTEX(clk_debug_lock);
1926static HLIST_HEAD(clk_debug_list);
1c8e6004 1927
4dff95dc
SB
1928static struct hlist_head *all_lists[] = {
1929 &clk_root_list,
1930 &clk_orphan_list,
1931 NULL,
1932};
1933
1934static struct hlist_head *orphan_list[] = {
1935 &clk_orphan_list,
1936 NULL,
1937};
1938
1939static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
1940 int level)
b2476490 1941{
4dff95dc
SB
1942 if (!c)
1943 return;
b2476490 1944
4dff95dc
SB
1945 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
1946 level * 3 + 1, "",
1947 30 - level * 3, c->name,
1948 c->enable_count, c->prepare_count, clk_core_get_rate(c),
1949 clk_core_get_accuracy(c), clk_core_get_phase(c));
1950}
89ac8d7a 1951
4dff95dc
SB
1952static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
1953 int level)
1954{
1955 struct clk_core *child;
b2476490 1956
4dff95dc
SB
1957 if (!c)
1958 return;
b2476490 1959
4dff95dc 1960 clk_summary_show_one(s, c, level);
0e1c0301 1961
4dff95dc
SB
1962 hlist_for_each_entry(child, &c->children, child_node)
1963 clk_summary_show_subtree(s, child, level + 1);
1c8e6004 1964}
b2476490 1965
4dff95dc 1966static int clk_summary_show(struct seq_file *s, void *data)
1c8e6004 1967{
4dff95dc
SB
1968 struct clk_core *c;
1969 struct hlist_head **lists = (struct hlist_head **)s->private;
1c8e6004 1970
4dff95dc
SB
1971 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
1972 seq_puts(s, "----------------------------------------------------------------------------------------\n");
b2476490 1973
1c8e6004
TV
1974 clk_prepare_lock();
1975
4dff95dc
SB
1976 for (; *lists; lists++)
1977 hlist_for_each_entry(c, *lists, child_node)
1978 clk_summary_show_subtree(s, c, 0);
b2476490 1979
eab89f69 1980 clk_prepare_unlock();
b2476490 1981
4dff95dc 1982 return 0;
b2476490 1983}
1c8e6004 1984
1c8e6004 1985
4dff95dc 1986static int clk_summary_open(struct inode *inode, struct file *file)
1c8e6004 1987{
4dff95dc 1988 return single_open(file, clk_summary_show, inode->i_private);
1c8e6004 1989}
b2476490 1990
4dff95dc
SB
1991static const struct file_operations clk_summary_fops = {
1992 .open = clk_summary_open,
1993 .read = seq_read,
1994 .llseek = seq_lseek,
1995 .release = single_release,
1996};
b2476490 1997
4dff95dc
SB
1998static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
1999{
2000 if (!c)
2001 return;
b2476490 2002
7cb81136 2003 /* This should be JSON format, i.e. elements separated with a comma */
4dff95dc
SB
2004 seq_printf(s, "\"%s\": { ", c->name);
2005 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
2006 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
7cb81136
SW
2007 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2008 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
4dff95dc 2009 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
b2476490 2010}
b2476490 2011
4dff95dc 2012static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
b2476490 2013{
4dff95dc 2014 struct clk_core *child;
b2476490 2015
4dff95dc
SB
2016 if (!c)
2017 return;
b2476490 2018
4dff95dc 2019 clk_dump_one(s, c, level);
b2476490 2020
4dff95dc
SB
2021 hlist_for_each_entry(child, &c->children, child_node) {
2022 seq_printf(s, ",");
2023 clk_dump_subtree(s, child, level + 1);
b2476490
MT
2024 }
2025
4dff95dc 2026 seq_printf(s, "}");
b2476490
MT
2027}
2028
4dff95dc 2029static int clk_dump(struct seq_file *s, void *data)
4e88f3de 2030{
4dff95dc
SB
2031 struct clk_core *c;
2032 bool first_node = true;
2033 struct hlist_head **lists = (struct hlist_head **)s->private;
4e88f3de 2034
4dff95dc 2035 seq_printf(s, "{");
4e88f3de 2036
4dff95dc 2037 clk_prepare_lock();
035a61c3 2038
4dff95dc
SB
2039 for (; *lists; lists++) {
2040 hlist_for_each_entry(c, *lists, child_node) {
2041 if (!first_node)
2042 seq_puts(s, ",");
2043 first_node = false;
2044 clk_dump_subtree(s, c, 0);
2045 }
2046 }
4e88f3de 2047
4dff95dc 2048 clk_prepare_unlock();
4e88f3de 2049
70e9f4dd 2050 seq_puts(s, "}\n");
4dff95dc 2051 return 0;
4e88f3de 2052}
4e88f3de 2053
4dff95dc
SB
2054
2055static int clk_dump_open(struct inode *inode, struct file *file)
b2476490 2056{
4dff95dc
SB
2057 return single_open(file, clk_dump, inode->i_private);
2058}
b2476490 2059
4dff95dc
SB
2060static const struct file_operations clk_dump_fops = {
2061 .open = clk_dump_open,
2062 .read = seq_read,
2063 .llseek = seq_lseek,
2064 .release = single_release,
2065};
89ac8d7a 2066
4dff95dc
SB
2067static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2068{
2069 struct dentry *d;
2070 int ret = -ENOMEM;
b2476490 2071
4dff95dc
SB
2072 if (!core || !pdentry) {
2073 ret = -EINVAL;
b2476490 2074 goto out;
4dff95dc 2075 }
b2476490 2076
4dff95dc
SB
2077 d = debugfs_create_dir(core->name, pdentry);
2078 if (!d)
b61c43c0 2079 goto out;
b61c43c0 2080
4dff95dc
SB
2081 core->dentry = d;
2082
2083 d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
2084 (u32 *)&core->rate);
2085 if (!d)
2086 goto err_out;
2087
2088 d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
2089 (u32 *)&core->accuracy);
2090 if (!d)
2091 goto err_out;
2092
2093 d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
2094 (u32 *)&core->phase);
2095 if (!d)
2096 goto err_out;
031dcc9b 2097
4dff95dc
SB
2098 d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
2099 (u32 *)&core->flags);
2100 if (!d)
2101 goto err_out;
031dcc9b 2102
4dff95dc
SB
2103 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
2104 (u32 *)&core->prepare_count);
2105 if (!d)
2106 goto err_out;
b2476490 2107
4dff95dc
SB
2108 d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
2109 (u32 *)&core->enable_count);
2110 if (!d)
2111 goto err_out;
b2476490 2112
4dff95dc
SB
2113 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
2114 (u32 *)&core->notifier_count);
2115 if (!d)
2116 goto err_out;
b2476490 2117
4dff95dc
SB
2118 if (core->ops->debug_init) {
2119 ret = core->ops->debug_init(core->hw, core->dentry);
2120 if (ret)
2121 goto err_out;
5279fc40 2122 }
b2476490 2123
4dff95dc
SB
2124 ret = 0;
2125 goto out;
b2476490 2126
4dff95dc
SB
2127err_out:
2128 debugfs_remove_recursive(core->dentry);
2129 core->dentry = NULL;
2130out:
b2476490
MT
2131 return ret;
2132}
035a61c3
TV
2133
2134/**
6e5ab41b
SB
2135 * clk_debug_register - add a clk node to the debugfs clk directory
2136 * @core: the clk being added to the debugfs clk directory
035a61c3 2137 *
6e5ab41b
SB
2138 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2139 * initialized. Otherwise it bails out early since the debugfs clk directory
4dff95dc 2140 * will be created lazily by clk_debug_init as part of a late_initcall.
035a61c3 2141 */
4dff95dc 2142static int clk_debug_register(struct clk_core *core)
035a61c3 2143{
4dff95dc 2144 int ret = 0;
035a61c3 2145
4dff95dc
SB
2146 mutex_lock(&clk_debug_lock);
2147 hlist_add_head(&core->debug_node, &clk_debug_list);
2148
2149 if (!inited)
2150 goto unlock;
2151
2152 ret = clk_debug_create_one(core, rootdir);
2153unlock:
2154 mutex_unlock(&clk_debug_lock);
2155
2156 return ret;
035a61c3 2157}
b2476490 2158
4dff95dc 2159 /**
6e5ab41b
SB
2160 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2161 * @core: the clk being removed from the debugfs clk directory
e59c5371 2162 *
6e5ab41b
SB
2163 * Dynamically removes a clk and all its child nodes from the
2164 * debugfs clk directory if clk->dentry points to debugfs created by
706d5c73 2165 * clk_debug_register in __clk_core_init.
e59c5371 2166 */
4dff95dc 2167static void clk_debug_unregister(struct clk_core *core)
e59c5371 2168{
4dff95dc
SB
2169 mutex_lock(&clk_debug_lock);
2170 hlist_del_init(&core->debug_node);
2171 debugfs_remove_recursive(core->dentry);
2172 core->dentry = NULL;
2173 mutex_unlock(&clk_debug_lock);
2174}
e59c5371 2175
4dff95dc
SB
2176struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
2177 void *data, const struct file_operations *fops)
2178{
2179 struct dentry *d = NULL;
e59c5371 2180
4dff95dc
SB
2181 if (hw->core->dentry)
2182 d = debugfs_create_file(name, mode, hw->core->dentry, data,
2183 fops);
e59c5371 2184
4dff95dc
SB
2185 return d;
2186}
2187EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
e59c5371 2188
4dff95dc 2189/**
6e5ab41b 2190 * clk_debug_init - lazily populate the debugfs clk directory
4dff95dc 2191 *
6e5ab41b
SB
2192 * clks are often initialized very early during boot before memory can be
2193 * dynamically allocated and well before debugfs is setup. This function
2194 * populates the debugfs clk directory once at boot-time when we know that
2195 * debugfs is setup. It should only be called once at boot-time, all other clks
2196 * added dynamically will be done so with clk_debug_register.
4dff95dc
SB
2197 */
2198static int __init clk_debug_init(void)
2199{
2200 struct clk_core *core;
2201 struct dentry *d;
dfc202ea 2202
4dff95dc 2203 rootdir = debugfs_create_dir("clk", NULL);
e59c5371 2204
4dff95dc
SB
2205 if (!rootdir)
2206 return -ENOMEM;
dfc202ea 2207
4dff95dc
SB
2208 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
2209 &clk_summary_fops);
2210 if (!d)
2211 return -ENOMEM;
e59c5371 2212
4dff95dc
SB
2213 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
2214 &clk_dump_fops);
2215 if (!d)
2216 return -ENOMEM;
e59c5371 2217
4dff95dc
SB
2218 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
2219 &orphan_list, &clk_summary_fops);
2220 if (!d)
2221 return -ENOMEM;
e59c5371 2222
4dff95dc
SB
2223 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
2224 &orphan_list, &clk_dump_fops);
2225 if (!d)
2226 return -ENOMEM;
e59c5371 2227
4dff95dc
SB
2228 mutex_lock(&clk_debug_lock);
2229 hlist_for_each_entry(core, &clk_debug_list, debug_node)
2230 clk_debug_create_one(core, rootdir);
e59c5371 2231
4dff95dc
SB
2232 inited = 1;
2233 mutex_unlock(&clk_debug_lock);
e59c5371 2234
4dff95dc
SB
2235 return 0;
2236}
2237late_initcall(clk_debug_init);
2238#else
2239static inline int clk_debug_register(struct clk_core *core) { return 0; }
2240static inline void clk_debug_reparent(struct clk_core *core,
2241 struct clk_core *new_parent)
035a61c3 2242{
035a61c3 2243}
4dff95dc 2244static inline void clk_debug_unregister(struct clk_core *core)
3d3801ef 2245{
3d3801ef 2246}
4dff95dc 2247#endif
3d3801ef 2248
b2476490 2249/**
be45ebf2 2250 * __clk_core_init - initialize the data structures in a struct clk_core
d35c80c2 2251 * @core: clk_core being initialized
b2476490 2252 *
035a61c3 2253 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2254 * parent and rate and sets them both.
b2476490 2255 */
be45ebf2 2256static int __clk_core_init(struct clk_core *core)
b2476490 2257{
d1302a36 2258 int i, ret = 0;
035a61c3 2259 struct clk_core *orphan;
b67bfe0d 2260 struct hlist_node *tmp2;
1c8e6004 2261 unsigned long rate;
b2476490 2262
d35c80c2 2263 if (!core)
d1302a36 2264 return -EINVAL;
b2476490 2265
eab89f69 2266 clk_prepare_lock();
b2476490
MT
2267
2268 /* check to see if a clock with this name is already registered */
d6968fca 2269 if (clk_core_lookup(core->name)) {
d1302a36 2270 pr_debug("%s: clk %s already initialized\n",
d6968fca 2271 __func__, core->name);
d1302a36 2272 ret = -EEXIST;
b2476490 2273 goto out;
d1302a36 2274 }
b2476490 2275
d4d7e3dd 2276 /* check that clk_ops are sane. See Documentation/clk.txt */
d6968fca
SB
2277 if (core->ops->set_rate &&
2278 !((core->ops->round_rate || core->ops->determine_rate) &&
2279 core->ops->recalc_rate)) {
c44fccb5
MY
2280 pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
2281 __func__, core->name);
d1302a36 2282 ret = -EINVAL;
d4d7e3dd
MT
2283 goto out;
2284 }
2285
d6968fca 2286 if (core->ops->set_parent && !core->ops->get_parent) {
c44fccb5
MY
2287 pr_err("%s: %s must implement .get_parent & .set_parent\n",
2288 __func__, core->name);
d1302a36 2289 ret = -EINVAL;
d4d7e3dd
MT
2290 goto out;
2291 }
2292
3c8e77dd
MY
2293 if (core->num_parents > 1 && !core->ops->get_parent) {
2294 pr_err("%s: %s must implement .get_parent as it has multi parents\n",
2295 __func__, core->name);
2296 ret = -EINVAL;
2297 goto out;
2298 }
2299
d6968fca
SB
2300 if (core->ops->set_rate_and_parent &&
2301 !(core->ops->set_parent && core->ops->set_rate)) {
c44fccb5 2302 pr_err("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 2303 __func__, core->name);
3fa2252b
SB
2304 ret = -EINVAL;
2305 goto out;
2306 }
2307
b2476490 2308 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
2309 for (i = 0; i < core->num_parents; i++)
2310 WARN(!core->parent_names[i],
b2476490 2311 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 2312 __func__, core->name);
b2476490 2313
d6968fca 2314 core->parent = __clk_init_parent(core);
b2476490
MT
2315
2316 /*
706d5c73
SB
2317 * Populate core->parent if parent has already been clk_core_init'd. If
2318 * parent has not yet been clk_core_init'd then place clk in the orphan
47b0eeb3 2319 * list. If clk doesn't have any parents then place it in the root
b2476490
MT
2320 * clk list.
2321 *
2322 * Every time a new clk is clk_init'd then we walk the list of orphan
2323 * clocks and re-parent any that are children of the clock currently
2324 * being clk_init'd.
2325 */
e6500344 2326 if (core->parent) {
d6968fca
SB
2327 hlist_add_head(&core->child_node,
2328 &core->parent->children);
e6500344 2329 core->orphan = core->parent->orphan;
47b0eeb3 2330 } else if (!core->num_parents) {
d6968fca 2331 hlist_add_head(&core->child_node, &clk_root_list);
e6500344
HS
2332 core->orphan = false;
2333 } else {
d6968fca 2334 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
2335 core->orphan = true;
2336 }
b2476490 2337
5279fc40
BB
2338 /*
2339 * Set clk's accuracy. The preferred method is to use
2340 * .recalc_accuracy. For simple clocks and lazy developers the default
2341 * fallback is to use the parent's accuracy. If a clock doesn't have a
2342 * parent (or is orphaned) then accuracy is set to zero (perfect
2343 * clock).
2344 */
d6968fca
SB
2345 if (core->ops->recalc_accuracy)
2346 core->accuracy = core->ops->recalc_accuracy(core->hw,
2347 __clk_get_accuracy(core->parent));
2348 else if (core->parent)
2349 core->accuracy = core->parent->accuracy;
5279fc40 2350 else
d6968fca 2351 core->accuracy = 0;
5279fc40 2352
9824cf73
MR
2353 /*
2354 * Set clk's phase.
2355 * Since a phase is by definition relative to its parent, just
2356 * query the current clock phase, or just assume it's in phase.
2357 */
d6968fca
SB
2358 if (core->ops->get_phase)
2359 core->phase = core->ops->get_phase(core->hw);
9824cf73 2360 else
d6968fca 2361 core->phase = 0;
9824cf73 2362
b2476490
MT
2363 /*
2364 * Set clk's rate. The preferred method is to use .recalc_rate. For
2365 * simple clocks and lazy developers the default fallback is to use the
2366 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2367 * then rate is set to zero.
2368 */
d6968fca
SB
2369 if (core->ops->recalc_rate)
2370 rate = core->ops->recalc_rate(core->hw,
2371 clk_core_get_rate_nolock(core->parent));
2372 else if (core->parent)
2373 rate = core->parent->rate;
b2476490 2374 else
1c8e6004 2375 rate = 0;
d6968fca 2376 core->rate = core->req_rate = rate;
b2476490
MT
2377
2378 /*
0e8f6e49
MY
2379 * walk the list of orphan clocks and reparent any that newly finds a
2380 * parent.
b2476490 2381 */
b67bfe0d 2382 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
0e8f6e49 2383 struct clk_core *parent = __clk_init_parent(orphan);
1f61e5f1 2384
0e8f6e49
MY
2385 if (parent)
2386 clk_core_reparent(orphan, parent);
2387 }
b2476490
MT
2388
2389 /*
2390 * optional platform-specific magic
2391 *
2392 * The .init callback is not used by any of the basic clock types, but
2393 * exists for weird hardware that must perform initialization magic.
2394 * Please consider other ways of solving initialization problems before
24ee1a08 2395 * using this callback, as its use is discouraged.
b2476490 2396 */
d6968fca
SB
2397 if (core->ops->init)
2398 core->ops->init(core->hw);
b2476490 2399
d6968fca 2400 kref_init(&core->ref);
b2476490 2401out:
eab89f69 2402 clk_prepare_unlock();
b2476490 2403
89f7e9de 2404 if (!ret)
d6968fca 2405 clk_debug_register(core);
89f7e9de 2406
d1302a36 2407 return ret;
b2476490
MT
2408}
2409
035a61c3
TV
2410struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2411 const char *con_id)
0197b3ea 2412{
0197b3ea
SK
2413 struct clk *clk;
2414
035a61c3 2415 /* This is to allow this function to be chained to others */
c1de1357 2416 if (IS_ERR_OR_NULL(hw))
035a61c3 2417 return (struct clk *) hw;
0197b3ea 2418
035a61c3
TV
2419 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2420 if (!clk)
2421 return ERR_PTR(-ENOMEM);
2422
2423 clk->core = hw->core;
2424 clk->dev_id = dev_id;
2425 clk->con_id = con_id;
1c8e6004
TV
2426 clk->max_rate = ULONG_MAX;
2427
2428 clk_prepare_lock();
50595f8b 2429 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2430 clk_prepare_unlock();
0197b3ea
SK
2431
2432 return clk;
2433}
035a61c3 2434
73e0e496 2435void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2436{
2437 clk_prepare_lock();
50595f8b 2438 hlist_del(&clk->clks_node);
1c8e6004
TV
2439 clk_prepare_unlock();
2440
2441 kfree(clk);
2442}
0197b3ea 2443
293ba3b4
SB
2444/**
2445 * clk_register - allocate a new clock, register it and return an opaque cookie
2446 * @dev: device that is registering this clock
2447 * @hw: link to hardware-specific clock data
2448 *
2449 * clk_register is the primary interface for populating the clock tree with new
2450 * clock nodes. It returns a pointer to the newly allocated struct clk which
a59a5163 2451 * cannot be dereferenced by driver code but may be used in conjunction with the
293ba3b4
SB
2452 * rest of the clock API. In the event of an error clk_register will return an
2453 * error code; drivers must test for an error code after calling clk_register.
2454 */
2455struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2456{
d1302a36 2457 int i, ret;
d6968fca 2458 struct clk_core *core;
293ba3b4 2459
d6968fca
SB
2460 core = kzalloc(sizeof(*core), GFP_KERNEL);
2461 if (!core) {
293ba3b4
SB
2462 ret = -ENOMEM;
2463 goto fail_out;
2464 }
b2476490 2465
d6968fca
SB
2466 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
2467 if (!core->name) {
0197b3ea
SK
2468 ret = -ENOMEM;
2469 goto fail_name;
2470 }
d6968fca 2471 core->ops = hw->init->ops;
ac2df527 2472 if (dev && dev->driver)
d6968fca
SB
2473 core->owner = dev->driver->owner;
2474 core->hw = hw;
2475 core->flags = hw->init->flags;
2476 core->num_parents = hw->init->num_parents;
9783c0d9
SB
2477 core->min_rate = 0;
2478 core->max_rate = ULONG_MAX;
d6968fca 2479 hw->core = core;
b2476490 2480
d1302a36 2481 /* allocate local copy in case parent_names is __initdata */
d6968fca 2482 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 2483 GFP_KERNEL);
d1302a36 2484
d6968fca 2485 if (!core->parent_names) {
d1302a36
MT
2486 ret = -ENOMEM;
2487 goto fail_parent_names;
2488 }
2489
2490
2491 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
2492 for (i = 0; i < core->num_parents; i++) {
2493 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2494 GFP_KERNEL);
d6968fca 2495 if (!core->parent_names[i]) {
d1302a36
MT
2496 ret = -ENOMEM;
2497 goto fail_parent_names_copy;
2498 }
2499 }
2500
176d1169
MY
2501 /* avoid unnecessary string look-ups of clk_core's possible parents. */
2502 core->parents = kcalloc(core->num_parents, sizeof(*core->parents),
2503 GFP_KERNEL);
2504 if (!core->parents) {
2505 ret = -ENOMEM;
2506 goto fail_parents;
2507 };
2508
d6968fca 2509 INIT_HLIST_HEAD(&core->clks);
1c8e6004 2510
035a61c3
TV
2511 hw->clk = __clk_create_clk(hw, NULL, NULL);
2512 if (IS_ERR(hw->clk)) {
035a61c3 2513 ret = PTR_ERR(hw->clk);
176d1169 2514 goto fail_parents;
035a61c3
TV
2515 }
2516
be45ebf2 2517 ret = __clk_core_init(core);
d1302a36 2518 if (!ret)
035a61c3 2519 return hw->clk;
b2476490 2520
1c8e6004 2521 __clk_free_clk(hw->clk);
035a61c3 2522 hw->clk = NULL;
b2476490 2523
176d1169
MY
2524fail_parents:
2525 kfree(core->parents);
d1302a36
MT
2526fail_parent_names_copy:
2527 while (--i >= 0)
d6968fca
SB
2528 kfree_const(core->parent_names[i]);
2529 kfree(core->parent_names);
d1302a36 2530fail_parent_names:
d6968fca 2531 kfree_const(core->name);
0197b3ea 2532fail_name:
d6968fca 2533 kfree(core);
d1302a36
MT
2534fail_out:
2535 return ERR_PTR(ret);
b2476490
MT
2536}
2537EXPORT_SYMBOL_GPL(clk_register);
2538
6e5ab41b 2539/* Free memory allocated for a clock. */
fcb0ee6a
SN
2540static void __clk_release(struct kref *ref)
2541{
d6968fca
SB
2542 struct clk_core *core = container_of(ref, struct clk_core, ref);
2543 int i = core->num_parents;
fcb0ee6a 2544
496eadf8
KK
2545 lockdep_assert_held(&prepare_lock);
2546
d6968fca 2547 kfree(core->parents);
fcb0ee6a 2548 while (--i >= 0)
d6968fca 2549 kfree_const(core->parent_names[i]);
fcb0ee6a 2550
d6968fca
SB
2551 kfree(core->parent_names);
2552 kfree_const(core->name);
2553 kfree(core);
fcb0ee6a
SN
2554}
2555
2556/*
2557 * Empty clk_ops for unregistered clocks. These are used temporarily
2558 * after clk_unregister() was called on a clock and until last clock
2559 * consumer calls clk_put() and the struct clk object is freed.
2560 */
2561static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2562{
2563 return -ENXIO;
2564}
2565
2566static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2567{
2568 WARN_ON_ONCE(1);
2569}
2570
2571static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2572 unsigned long parent_rate)
2573{
2574 return -ENXIO;
2575}
2576
2577static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2578{
2579 return -ENXIO;
2580}
2581
2582static const struct clk_ops clk_nodrv_ops = {
2583 .enable = clk_nodrv_prepare_enable,
2584 .disable = clk_nodrv_disable_unprepare,
2585 .prepare = clk_nodrv_prepare_enable,
2586 .unprepare = clk_nodrv_disable_unprepare,
2587 .set_rate = clk_nodrv_set_rate,
2588 .set_parent = clk_nodrv_set_parent,
2589};
2590
1df5c939
MB
2591/**
2592 * clk_unregister - unregister a currently registered clock
2593 * @clk: clock to unregister
1df5c939 2594 */
fcb0ee6a
SN
2595void clk_unregister(struct clk *clk)
2596{
2597 unsigned long flags;
2598
6314b679
SB
2599 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2600 return;
2601
035a61c3 2602 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2603
2604 clk_prepare_lock();
2605
035a61c3
TV
2606 if (clk->core->ops == &clk_nodrv_ops) {
2607 pr_err("%s: unregistered clock: %s\n", __func__,
2608 clk->core->name);
4106a3d9 2609 goto unlock;
fcb0ee6a
SN
2610 }
2611 /*
2612 * Assign empty clock ops for consumers that might still hold
2613 * a reference to this clock.
2614 */
2615 flags = clk_enable_lock();
035a61c3 2616 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2617 clk_enable_unlock(flags);
2618
035a61c3
TV
2619 if (!hlist_empty(&clk->core->children)) {
2620 struct clk_core *child;
874f224c 2621 struct hlist_node *t;
fcb0ee6a
SN
2622
2623 /* Reparent all children to the orphan list. */
035a61c3
TV
2624 hlist_for_each_entry_safe(child, t, &clk->core->children,
2625 child_node)
2626 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2627 }
2628
035a61c3 2629 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2630
035a61c3 2631 if (clk->core->prepare_count)
fcb0ee6a 2632 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2633 __func__, clk->core->name);
2634 kref_put(&clk->core->ref, __clk_release);
4106a3d9 2635unlock:
fcb0ee6a
SN
2636 clk_prepare_unlock();
2637}
1df5c939
MB
2638EXPORT_SYMBOL_GPL(clk_unregister);
2639
46c8773a
SB
2640static void devm_clk_release(struct device *dev, void *res)
2641{
293ba3b4 2642 clk_unregister(*(struct clk **)res);
46c8773a
SB
2643}
2644
2645/**
2646 * devm_clk_register - resource managed clk_register()
2647 * @dev: device that is registering this clock
2648 * @hw: link to hardware-specific clock data
2649 *
2650 * Managed clk_register(). Clocks returned from this function are
2651 * automatically clk_unregister()ed on driver detach. See clk_register() for
2652 * more information.
2653 */
2654struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2655{
2656 struct clk *clk;
293ba3b4 2657 struct clk **clkp;
46c8773a 2658
293ba3b4
SB
2659 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2660 if (!clkp)
46c8773a
SB
2661 return ERR_PTR(-ENOMEM);
2662
293ba3b4
SB
2663 clk = clk_register(dev, hw);
2664 if (!IS_ERR(clk)) {
2665 *clkp = clk;
2666 devres_add(dev, clkp);
46c8773a 2667 } else {
293ba3b4 2668 devres_free(clkp);
46c8773a
SB
2669 }
2670
2671 return clk;
2672}
2673EXPORT_SYMBOL_GPL(devm_clk_register);
2674
2675static int devm_clk_match(struct device *dev, void *res, void *data)
2676{
2677 struct clk *c = res;
2678 if (WARN_ON(!c))
2679 return 0;
2680 return c == data;
2681}
2682
2683/**
2684 * devm_clk_unregister - resource managed clk_unregister()
2685 * @clk: clock to unregister
2686 *
2687 * Deallocate a clock allocated with devm_clk_register(). Normally
2688 * this function will not need to be called and the resource management
2689 * code will ensure that the resource is freed.
2690 */
2691void devm_clk_unregister(struct device *dev, struct clk *clk)
2692{
2693 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2694}
2695EXPORT_SYMBOL_GPL(devm_clk_unregister);
2696
ac2df527
SN
2697/*
2698 * clkdev helpers
2699 */
2700int __clk_get(struct clk *clk)
2701{
035a61c3
TV
2702 struct clk_core *core = !clk ? NULL : clk->core;
2703
2704 if (core) {
2705 if (!try_module_get(core->owner))
00efcb1c 2706 return 0;
ac2df527 2707
035a61c3 2708 kref_get(&core->ref);
00efcb1c 2709 }
ac2df527
SN
2710 return 1;
2711}
2712
2713void __clk_put(struct clk *clk)
2714{
10cdfe54
TV
2715 struct module *owner;
2716
00efcb1c 2717 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2718 return;
2719
fcb0ee6a 2720 clk_prepare_lock();
1c8e6004 2721
50595f8b 2722 hlist_del(&clk->clks_node);
ec02ace8
TV
2723 if (clk->min_rate > clk->core->req_rate ||
2724 clk->max_rate < clk->core->req_rate)
2725 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2726
1c8e6004
TV
2727 owner = clk->core->owner;
2728 kref_put(&clk->core->ref, __clk_release);
2729
fcb0ee6a
SN
2730 clk_prepare_unlock();
2731
10cdfe54 2732 module_put(owner);
035a61c3 2733
035a61c3 2734 kfree(clk);
ac2df527
SN
2735}
2736
b2476490
MT
2737/*** clk rate change notifiers ***/
2738
2739/**
2740 * clk_notifier_register - add a clk rate change notifier
2741 * @clk: struct clk * to watch
2742 * @nb: struct notifier_block * with callback info
2743 *
2744 * Request notification when clk's rate changes. This uses an SRCU
2745 * notifier because we want it to block and notifier unregistrations are
2746 * uncommon. The callbacks associated with the notifier must not
2747 * re-enter into the clk framework by calling any top-level clk APIs;
2748 * this will cause a nested prepare_lock mutex.
2749 *
198bb594
MY
2750 * In all notification cases (pre, post and abort rate change) the original
2751 * clock rate is passed to the callback via struct clk_notifier_data.old_rate
2752 * and the new frequency is passed via struct clk_notifier_data.new_rate.
b2476490 2753 *
b2476490
MT
2754 * clk_notifier_register() must be called from non-atomic context.
2755 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2756 * allocation failure; otherwise, passes along the return value of
2757 * srcu_notifier_chain_register().
2758 */
2759int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2760{
2761 struct clk_notifier *cn;
2762 int ret = -ENOMEM;
2763
2764 if (!clk || !nb)
2765 return -EINVAL;
2766
eab89f69 2767 clk_prepare_lock();
b2476490
MT
2768
2769 /* search the list of notifiers for this clk */
2770 list_for_each_entry(cn, &clk_notifier_list, node)
2771 if (cn->clk == clk)
2772 break;
2773
2774 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2775 if (cn->clk != clk) {
2776 cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2777 if (!cn)
2778 goto out;
2779
2780 cn->clk = clk;
2781 srcu_init_notifier_head(&cn->notifier_head);
2782
2783 list_add(&cn->node, &clk_notifier_list);
2784 }
2785
2786 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2787
035a61c3 2788 clk->core->notifier_count++;
b2476490
MT
2789
2790out:
eab89f69 2791 clk_prepare_unlock();
b2476490
MT
2792
2793 return ret;
2794}
2795EXPORT_SYMBOL_GPL(clk_notifier_register);
2796
2797/**
2798 * clk_notifier_unregister - remove a clk rate change notifier
2799 * @clk: struct clk *
2800 * @nb: struct notifier_block * with callback info
2801 *
2802 * Request no further notification for changes to 'clk' and frees memory
2803 * allocated in clk_notifier_register.
2804 *
2805 * Returns -EINVAL if called with null arguments; otherwise, passes
2806 * along the return value of srcu_notifier_chain_unregister().
2807 */
2808int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2809{
2810 struct clk_notifier *cn = NULL;
2811 int ret = -EINVAL;
2812
2813 if (!clk || !nb)
2814 return -EINVAL;
2815
eab89f69 2816 clk_prepare_lock();
b2476490
MT
2817
2818 list_for_each_entry(cn, &clk_notifier_list, node)
2819 if (cn->clk == clk)
2820 break;
2821
2822 if (cn->clk == clk) {
2823 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2824
035a61c3 2825 clk->core->notifier_count--;
b2476490
MT
2826
2827 /* XXX the notifier code should handle this better */
2828 if (!cn->notifier_head.head) {
2829 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 2830 list_del(&cn->node);
b2476490
MT
2831 kfree(cn);
2832 }
2833
2834 } else {
2835 ret = -ENOENT;
2836 }
2837
eab89f69 2838 clk_prepare_unlock();
b2476490
MT
2839
2840 return ret;
2841}
2842EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
2843
2844#ifdef CONFIG_OF
2845/**
2846 * struct of_clk_provider - Clock provider registration structure
2847 * @link: Entry in global list of clock providers
2848 * @node: Pointer to device tree node of clock provider
2849 * @get: Get clock callback. Returns NULL or a struct clk for the
2850 * given clock specifier
2851 * @data: context pointer to be passed into @get callback
2852 */
2853struct of_clk_provider {
2854 struct list_head link;
2855
2856 struct device_node *node;
2857 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
2858 void *data;
2859};
2860
f2f6c255
PG
2861static const struct of_device_id __clk_of_table_sentinel
2862 __used __section(__clk_of_table_end);
2863
766e6a4e 2864static LIST_HEAD(of_clk_providers);
d6782c26
SN
2865static DEFINE_MUTEX(of_clk_mutex);
2866
766e6a4e
GL
2867struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2868 void *data)
2869{
2870 return data;
2871}
2872EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
2873
494bfec9
SG
2874struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
2875{
2876 struct clk_onecell_data *clk_data = data;
2877 unsigned int idx = clkspec->args[0];
2878
2879 if (idx >= clk_data->clk_num) {
7e96353c 2880 pr_err("%s: invalid clock index %u\n", __func__, idx);
494bfec9
SG
2881 return ERR_PTR(-EINVAL);
2882 }
2883
2884 return clk_data->clks[idx];
2885}
2886EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
2887
766e6a4e
GL
2888/**
2889 * of_clk_add_provider() - Register a clock provider for a node
2890 * @np: Device node pointer associated with clock provider
2891 * @clk_src_get: callback for decoding clock
2892 * @data: context pointer for @clk_src_get callback.
2893 */
2894int of_clk_add_provider(struct device_node *np,
2895 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
2896 void *data),
2897 void *data)
2898{
2899 struct of_clk_provider *cp;
86be408b 2900 int ret;
766e6a4e
GL
2901
2902 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
2903 if (!cp)
2904 return -ENOMEM;
2905
2906 cp->node = of_node_get(np);
2907 cp->data = data;
2908 cp->get = clk_src_get;
2909
d6782c26 2910 mutex_lock(&of_clk_mutex);
766e6a4e 2911 list_add(&cp->link, &of_clk_providers);
d6782c26 2912 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2913 pr_debug("Added clock from %s\n", np->full_name);
2914
86be408b
SN
2915 ret = of_clk_set_defaults(np, true);
2916 if (ret < 0)
2917 of_clk_del_provider(np);
2918
2919 return ret;
766e6a4e
GL
2920}
2921EXPORT_SYMBOL_GPL(of_clk_add_provider);
2922
2923/**
2924 * of_clk_del_provider() - Remove a previously registered clock provider
2925 * @np: Device node pointer associated with clock provider
2926 */
2927void of_clk_del_provider(struct device_node *np)
2928{
2929 struct of_clk_provider *cp;
2930
d6782c26 2931 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2932 list_for_each_entry(cp, &of_clk_providers, link) {
2933 if (cp->node == np) {
2934 list_del(&cp->link);
2935 of_node_put(cp->node);
2936 kfree(cp);
2937 break;
2938 }
2939 }
d6782c26 2940 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2941}
2942EXPORT_SYMBOL_GPL(of_clk_del_provider);
2943
73e0e496
SB
2944struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
2945 const char *dev_id, const char *con_id)
766e6a4e
GL
2946{
2947 struct of_clk_provider *provider;
a34cd466 2948 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
766e6a4e 2949
306c342f
SB
2950 if (!clkspec)
2951 return ERR_PTR(-EINVAL);
2952
766e6a4e 2953 /* Check if we have such a provider in our array */
306c342f 2954 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2955 list_for_each_entry(provider, &of_clk_providers, link) {
2956 if (provider->node == clkspec->np)
2957 clk = provider->get(clkspec, provider->data);
73e0e496
SB
2958 if (!IS_ERR(clk)) {
2959 clk = __clk_create_clk(__clk_get_hw(clk), dev_id,
2960 con_id);
2961
2962 if (!IS_ERR(clk) && !__clk_get(clk)) {
2963 __clk_free_clk(clk);
2964 clk = ERR_PTR(-ENOENT);
2965 }
2966
766e6a4e 2967 break;
73e0e496 2968 }
766e6a4e 2969 }
306c342f 2970 mutex_unlock(&of_clk_mutex);
d6782c26
SN
2971
2972 return clk;
2973}
2974
306c342f
SB
2975/**
2976 * of_clk_get_from_provider() - Lookup a clock from a clock provider
2977 * @clkspec: pointer to a clock specifier data structure
2978 *
2979 * This function looks up a struct clk from the registered list of clock
2980 * providers, an input is a clock specifier data structure as returned
2981 * from the of_parse_phandle_with_args() function call.
2982 */
d6782c26
SN
2983struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
2984{
306c342f 2985 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e 2986}
fb4dd222 2987EXPORT_SYMBOL_GPL(of_clk_get_from_provider);
766e6a4e 2988
929e7f3b
SB
2989/**
2990 * of_clk_get_parent_count() - Count the number of clocks a device node has
2991 * @np: device node to count
2992 *
2993 * Returns: The number of clocks that are possible parents of this node
2994 */
2995unsigned int of_clk_get_parent_count(struct device_node *np)
f6102742 2996{
929e7f3b
SB
2997 int count;
2998
2999 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
3000 if (count < 0)
3001 return 0;
3002
3003 return count;
f6102742
MT
3004}
3005EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
3006
766e6a4e
GL
3007const char *of_clk_get_parent_name(struct device_node *np, int index)
3008{
3009 struct of_phandle_args clkspec;
7a0fc1a3 3010 struct property *prop;
766e6a4e 3011 const char *clk_name;
7a0fc1a3
BD
3012 const __be32 *vp;
3013 u32 pv;
766e6a4e 3014 int rc;
7a0fc1a3 3015 int count;
0a4807c2 3016 struct clk *clk;
766e6a4e 3017
766e6a4e
GL
3018 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3019 &clkspec);
3020 if (rc)
3021 return NULL;
3022
7a0fc1a3
BD
3023 index = clkspec.args_count ? clkspec.args[0] : 0;
3024 count = 0;
3025
3026 /* if there is an indices property, use it to transfer the index
3027 * specified into an array offset for the clock-output-names property.
3028 */
3029 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3030 if (index == pv) {
3031 index = count;
3032 break;
3033 }
3034 count++;
3035 }
8da411cc
MY
3036 /* We went off the end of 'clock-indices' without finding it */
3037 if (prop && !vp)
3038 return NULL;
7a0fc1a3 3039
766e6a4e 3040 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3041 index,
0a4807c2
SB
3042 &clk_name) < 0) {
3043 /*
3044 * Best effort to get the name if the clock has been
3045 * registered with the framework. If the clock isn't
3046 * registered, we return the node name as the name of
3047 * the clock as long as #clock-cells = 0.
3048 */
3049 clk = of_clk_get_from_provider(&clkspec);
3050 if (IS_ERR(clk)) {
3051 if (clkspec.args_count == 0)
3052 clk_name = clkspec.np->name;
3053 else
3054 clk_name = NULL;
3055 } else {
3056 clk_name = __clk_get_name(clk);
3057 clk_put(clk);
3058 }
3059 }
3060
766e6a4e
GL
3061
3062 of_node_put(clkspec.np);
3063 return clk_name;
3064}
3065EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3066
2e61dfb3
DN
3067/**
3068 * of_clk_parent_fill() - Fill @parents with names of @np's parents and return
3069 * number of parents
3070 * @np: Device node pointer associated with clock provider
3071 * @parents: pointer to char array that hold the parents' names
3072 * @size: size of the @parents array
3073 *
3074 * Return: number of parents for the clock node.
3075 */
3076int of_clk_parent_fill(struct device_node *np, const char **parents,
3077 unsigned int size)
3078{
3079 unsigned int i = 0;
3080
3081 while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
3082 i++;
3083
3084 return i;
3085}
3086EXPORT_SYMBOL_GPL(of_clk_parent_fill);
3087
1771b10d
GC
3088struct clock_provider {
3089 of_clk_init_cb_t clk_init_cb;
3090 struct device_node *np;
3091 struct list_head node;
3092};
3093
1771b10d
GC
3094/*
3095 * This function looks for a parent clock. If there is one, then it
3096 * checks that the provider for this parent clock was initialized, in
3097 * this case the parent clock will be ready.
3098 */
3099static int parent_ready(struct device_node *np)
3100{
3101 int i = 0;
3102
3103 while (true) {
3104 struct clk *clk = of_clk_get(np, i);
3105
3106 /* this parent is ready we can check the next one */
3107 if (!IS_ERR(clk)) {
3108 clk_put(clk);
3109 i++;
3110 continue;
3111 }
3112
3113 /* at least one parent is not ready, we exit now */
3114 if (PTR_ERR(clk) == -EPROBE_DEFER)
3115 return 0;
3116
3117 /*
3118 * Here we make assumption that the device tree is
3119 * written correctly. So an error means that there is
3120 * no more parent. As we didn't exit yet, then the
3121 * previous parent are ready. If there is no clock
3122 * parent, no need to wait for them, then we can
3123 * consider their absence as being ready
3124 */
3125 return 1;
3126 }
3127}
3128
766e6a4e
GL
3129/**
3130 * of_clk_init() - Scan and init clock providers from the DT
3131 * @matches: array of compatible values and init functions for providers.
3132 *
1771b10d 3133 * This function scans the device tree for matching clock providers
e5ca8fb4 3134 * and calls their initialization functions. It also does it by trying
1771b10d 3135 * to follow the dependencies.
766e6a4e
GL
3136 */
3137void __init of_clk_init(const struct of_device_id *matches)
3138{
7f7ed584 3139 const struct of_device_id *match;
766e6a4e 3140 struct device_node *np;
1771b10d
GC
3141 struct clock_provider *clk_provider, *next;
3142 bool is_init_done;
3143 bool force = false;
2573a02a 3144 LIST_HEAD(clk_provider_list);
766e6a4e 3145
f2f6c255 3146 if (!matches)
819b4861 3147 matches = &__clk_of_table;
f2f6c255 3148
1771b10d 3149 /* First prepare the list of the clocks providers */
7f7ed584 3150 for_each_matching_node_and_match(np, matches, &match) {
2e3b19f1
SB
3151 struct clock_provider *parent;
3152
3e5dd6f6
GU
3153 if (!of_device_is_available(np))
3154 continue;
3155
2e3b19f1
SB
3156 parent = kzalloc(sizeof(*parent), GFP_KERNEL);
3157 if (!parent) {
3158 list_for_each_entry_safe(clk_provider, next,
3159 &clk_provider_list, node) {
3160 list_del(&clk_provider->node);
6bc9d9d6 3161 of_node_put(clk_provider->np);
2e3b19f1
SB
3162 kfree(clk_provider);
3163 }
6bc9d9d6 3164 of_node_put(np);
2e3b19f1
SB
3165 return;
3166 }
1771b10d
GC
3167
3168 parent->clk_init_cb = match->data;
6bc9d9d6 3169 parent->np = of_node_get(np);
3f6d439f 3170 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3171 }
3172
3173 while (!list_empty(&clk_provider_list)) {
3174 is_init_done = false;
3175 list_for_each_entry_safe(clk_provider, next,
3176 &clk_provider_list, node) {
3177 if (force || parent_ready(clk_provider->np)) {
86be408b 3178
1771b10d 3179 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3180 of_clk_set_defaults(clk_provider->np, true);
3181
1771b10d 3182 list_del(&clk_provider->node);
6bc9d9d6 3183 of_node_put(clk_provider->np);
1771b10d
GC
3184 kfree(clk_provider);
3185 is_init_done = true;
3186 }
3187 }
3188
3189 /*
e5ca8fb4 3190 * We didn't manage to initialize any of the
1771b10d
GC
3191 * remaining providers during the last loop, so now we
3192 * initialize all the remaining ones unconditionally
3193 * in case the clock parent was not mandatory
3194 */
3195 if (!is_init_done)
3196 force = true;
766e6a4e
GL
3197 }
3198}
3199#endif
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