clk: Add tracepoints for hardware operations
[deliverable/linux.git] / drivers / clk / clk.c
CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
b09d6d99 12#include <linux/clk-provider.h>
86be408b 13#include <linux/clk/clk-conf.h>
b2476490
MT
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/spinlock.h>
17#include <linux/err.h>
18#include <linux/list.h>
19#include <linux/slab.h>
766e6a4e 20#include <linux/of.h>
46c8773a 21#include <linux/device.h>
f2f6c255 22#include <linux/init.h>
533ddeb1 23#include <linux/sched.h>
b2476490 24
d6782c26
SN
25#include "clk.h"
26
b2476490
MT
27static DEFINE_SPINLOCK(enable_lock);
28static DEFINE_MUTEX(prepare_lock);
29
533ddeb1
MT
30static struct task_struct *prepare_owner;
31static struct task_struct *enable_owner;
32
33static int prepare_refcnt;
34static int enable_refcnt;
35
b2476490
MT
36static HLIST_HEAD(clk_root_list);
37static HLIST_HEAD(clk_orphan_list);
38static LIST_HEAD(clk_notifier_list);
39
035a61c3
TV
40static long clk_core_get_accuracy(struct clk_core *clk);
41static unsigned long clk_core_get_rate(struct clk_core *clk);
42static int clk_core_get_phase(struct clk_core *clk);
43static bool clk_core_is_prepared(struct clk_core *clk);
44static bool clk_core_is_enabled(struct clk_core *clk);
035a61c3
TV
45static struct clk_core *clk_core_lookup(const char *name);
46
b09d6d99
MT
47/*** private data structures ***/
48
49struct clk_core {
50 const char *name;
51 const struct clk_ops *ops;
52 struct clk_hw *hw;
53 struct module *owner;
54 struct clk_core *parent;
55 const char **parent_names;
56 struct clk_core **parents;
57 u8 num_parents;
58 u8 new_parent_index;
59 unsigned long rate;
1c8e6004 60 unsigned long req_rate;
b09d6d99
MT
61 unsigned long new_rate;
62 struct clk_core *new_parent;
63 struct clk_core *new_child;
64 unsigned long flags;
65 unsigned int enable_count;
66 unsigned int prepare_count;
67 unsigned long accuracy;
68 int phase;
69 struct hlist_head children;
70 struct hlist_node child_node;
71 struct hlist_node debug_node;
1c8e6004 72 struct hlist_head clks;
b09d6d99
MT
73 unsigned int notifier_count;
74#ifdef CONFIG_DEBUG_FS
75 struct dentry *dentry;
76#endif
77 struct kref ref;
78};
79
dfc202ea
SB
80#define CREATE_TRACE_POINTS
81#include <trace/events/clk.h>
82
b09d6d99
MT
83struct clk {
84 struct clk_core *core;
85 const char *dev_id;
86 const char *con_id;
1c8e6004
TV
87 unsigned long min_rate;
88 unsigned long max_rate;
89 struct hlist_node child_node;
b09d6d99
MT
90};
91
eab89f69
MT
92/*** locking ***/
93static void clk_prepare_lock(void)
94{
533ddeb1
MT
95 if (!mutex_trylock(&prepare_lock)) {
96 if (prepare_owner == current) {
97 prepare_refcnt++;
98 return;
99 }
100 mutex_lock(&prepare_lock);
101 }
102 WARN_ON_ONCE(prepare_owner != NULL);
103 WARN_ON_ONCE(prepare_refcnt != 0);
104 prepare_owner = current;
105 prepare_refcnt = 1;
eab89f69
MT
106}
107
108static void clk_prepare_unlock(void)
109{
533ddeb1
MT
110 WARN_ON_ONCE(prepare_owner != current);
111 WARN_ON_ONCE(prepare_refcnt == 0);
112
113 if (--prepare_refcnt)
114 return;
115 prepare_owner = NULL;
eab89f69
MT
116 mutex_unlock(&prepare_lock);
117}
118
119static unsigned long clk_enable_lock(void)
120{
121 unsigned long flags;
533ddeb1
MT
122
123 if (!spin_trylock_irqsave(&enable_lock, flags)) {
124 if (enable_owner == current) {
125 enable_refcnt++;
126 return flags;
127 }
128 spin_lock_irqsave(&enable_lock, flags);
129 }
130 WARN_ON_ONCE(enable_owner != NULL);
131 WARN_ON_ONCE(enable_refcnt != 0);
132 enable_owner = current;
133 enable_refcnt = 1;
eab89f69
MT
134 return flags;
135}
136
137static void clk_enable_unlock(unsigned long flags)
138{
533ddeb1
MT
139 WARN_ON_ONCE(enable_owner != current);
140 WARN_ON_ONCE(enable_refcnt == 0);
141
142 if (--enable_refcnt)
143 return;
144 enable_owner = NULL;
eab89f69
MT
145 spin_unlock_irqrestore(&enable_lock, flags);
146}
147
b2476490
MT
148/*** debugfs support ***/
149
ea72dc2c 150#ifdef CONFIG_DEBUG_FS
b2476490
MT
151#include <linux/debugfs.h>
152
153static struct dentry *rootdir;
b2476490 154static int inited = 0;
6314b679
SB
155static DEFINE_MUTEX(clk_debug_lock);
156static HLIST_HEAD(clk_debug_list);
b2476490 157
6b44c854
SK
158static struct hlist_head *all_lists[] = {
159 &clk_root_list,
160 &clk_orphan_list,
161 NULL,
162};
163
164static struct hlist_head *orphan_list[] = {
165 &clk_orphan_list,
166 NULL,
167};
168
035a61c3
TV
169static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
170 int level)
1af599df
PG
171{
172 if (!c)
173 return;
174
e59c5371 175 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
1af599df
PG
176 level * 3 + 1, "",
177 30 - level * 3, c->name,
035a61c3
TV
178 c->enable_count, c->prepare_count, clk_core_get_rate(c),
179 clk_core_get_accuracy(c), clk_core_get_phase(c));
1af599df
PG
180}
181
035a61c3 182static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
1af599df
PG
183 int level)
184{
035a61c3 185 struct clk_core *child;
1af599df
PG
186
187 if (!c)
188 return;
189
190 clk_summary_show_one(s, c, level);
191
b67bfe0d 192 hlist_for_each_entry(child, &c->children, child_node)
1af599df
PG
193 clk_summary_show_subtree(s, child, level + 1);
194}
195
196static int clk_summary_show(struct seq_file *s, void *data)
197{
035a61c3 198 struct clk_core *c;
27b8d5f7 199 struct hlist_head **lists = (struct hlist_head **)s->private;
1af599df 200
e59c5371
MT
201 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
202 seq_puts(s, "----------------------------------------------------------------------------------------\n");
1af599df 203
eab89f69 204 clk_prepare_lock();
1af599df 205
27b8d5f7
PDS
206 for (; *lists; lists++)
207 hlist_for_each_entry(c, *lists, child_node)
208 clk_summary_show_subtree(s, c, 0);
1af599df 209
eab89f69 210 clk_prepare_unlock();
1af599df
PG
211
212 return 0;
213}
214
215
216static int clk_summary_open(struct inode *inode, struct file *file)
217{
218 return single_open(file, clk_summary_show, inode->i_private);
219}
220
221static const struct file_operations clk_summary_fops = {
222 .open = clk_summary_open,
223 .read = seq_read,
224 .llseek = seq_lseek,
225 .release = single_release,
226};
227
035a61c3 228static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
bddca894
PG
229{
230 if (!c)
231 return;
232
233 seq_printf(s, "\"%s\": { ", c->name);
234 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
235 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
035a61c3
TV
236 seq_printf(s, "\"rate\": %lu", clk_core_get_rate(c));
237 seq_printf(s, "\"accuracy\": %lu", clk_core_get_accuracy(c));
238 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
bddca894
PG
239}
240
035a61c3 241static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
bddca894 242{
035a61c3 243 struct clk_core *child;
bddca894
PG
244
245 if (!c)
246 return;
247
248 clk_dump_one(s, c, level);
249
b67bfe0d 250 hlist_for_each_entry(child, &c->children, child_node) {
bddca894
PG
251 seq_printf(s, ",");
252 clk_dump_subtree(s, child, level + 1);
253 }
254
255 seq_printf(s, "}");
256}
257
258static int clk_dump(struct seq_file *s, void *data)
259{
035a61c3 260 struct clk_core *c;
bddca894 261 bool first_node = true;
27b8d5f7 262 struct hlist_head **lists = (struct hlist_head **)s->private;
bddca894
PG
263
264 seq_printf(s, "{");
265
eab89f69 266 clk_prepare_lock();
bddca894 267
27b8d5f7
PDS
268 for (; *lists; lists++) {
269 hlist_for_each_entry(c, *lists, child_node) {
270 if (!first_node)
271 seq_puts(s, ",");
272 first_node = false;
273 clk_dump_subtree(s, c, 0);
274 }
bddca894
PG
275 }
276
eab89f69 277 clk_prepare_unlock();
bddca894
PG
278
279 seq_printf(s, "}");
280 return 0;
281}
282
283
284static int clk_dump_open(struct inode *inode, struct file *file)
285{
286 return single_open(file, clk_dump, inode->i_private);
287}
288
289static const struct file_operations clk_dump_fops = {
290 .open = clk_dump_open,
291 .read = seq_read,
292 .llseek = seq_lseek,
293 .release = single_release,
294};
295
035a61c3 296static int clk_debug_create_one(struct clk_core *clk, struct dentry *pdentry)
b2476490
MT
297{
298 struct dentry *d;
299 int ret = -ENOMEM;
300
301 if (!clk || !pdentry) {
302 ret = -EINVAL;
303 goto out;
304 }
305
306 d = debugfs_create_dir(clk->name, pdentry);
307 if (!d)
308 goto out;
309
310 clk->dentry = d;
311
312 d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
313 (u32 *)&clk->rate);
314 if (!d)
315 goto err_out;
316
5279fc40
BB
317 d = debugfs_create_u32("clk_accuracy", S_IRUGO, clk->dentry,
318 (u32 *)&clk->accuracy);
319 if (!d)
320 goto err_out;
321
e59c5371
MT
322 d = debugfs_create_u32("clk_phase", S_IRUGO, clk->dentry,
323 (u32 *)&clk->phase);
324 if (!d)
325 goto err_out;
326
b2476490
MT
327 d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
328 (u32 *)&clk->flags);
329 if (!d)
330 goto err_out;
331
332 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
333 (u32 *)&clk->prepare_count);
334 if (!d)
335 goto err_out;
336
337 d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
338 (u32 *)&clk->enable_count);
339 if (!d)
340 goto err_out;
341
342 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
343 (u32 *)&clk->notifier_count);
344 if (!d)
345 goto err_out;
346
abeab450
CB
347 if (clk->ops->debug_init) {
348 ret = clk->ops->debug_init(clk->hw, clk->dentry);
349 if (ret)
c646cbf1 350 goto err_out;
abeab450 351 }
c646cbf1 352
b2476490
MT
353 ret = 0;
354 goto out;
355
356err_out:
b5f98e65
AE
357 debugfs_remove_recursive(clk->dentry);
358 clk->dentry = NULL;
b2476490
MT
359out:
360 return ret;
361}
362
b2476490
MT
363/**
364 * clk_debug_register - add a clk node to the debugfs clk tree
365 * @clk: the clk being added to the debugfs clk tree
366 *
367 * Dynamically adds a clk to the debugfs clk tree if debugfs has been
368 * initialized. Otherwise it bails out early since the debugfs clk tree
369 * will be created lazily by clk_debug_init as part of a late_initcall.
b2476490 370 */
035a61c3 371static int clk_debug_register(struct clk_core *clk)
b2476490 372{
b2476490
MT
373 int ret = 0;
374
6314b679
SB
375 mutex_lock(&clk_debug_lock);
376 hlist_add_head(&clk->debug_node, &clk_debug_list);
377
b2476490 378 if (!inited)
6314b679 379 goto unlock;
b2476490 380
6314b679
SB
381 ret = clk_debug_create_one(clk, rootdir);
382unlock:
383 mutex_unlock(&clk_debug_lock);
b2476490 384
b2476490
MT
385 return ret;
386}
387
fcb0ee6a
SN
388 /**
389 * clk_debug_unregister - remove a clk node from the debugfs clk tree
390 * @clk: the clk being removed from the debugfs clk tree
391 *
392 * Dynamically removes a clk and all it's children clk nodes from the
393 * debugfs clk tree if clk->dentry points to debugfs created by
394 * clk_debug_register in __clk_init.
fcb0ee6a 395 */
035a61c3 396static void clk_debug_unregister(struct clk_core *clk)
fcb0ee6a 397{
6314b679 398 mutex_lock(&clk_debug_lock);
6314b679 399 hlist_del_init(&clk->debug_node);
fcb0ee6a 400 debugfs_remove_recursive(clk->dentry);
6314b679 401 clk->dentry = NULL;
6314b679 402 mutex_unlock(&clk_debug_lock);
fcb0ee6a
SN
403}
404
61c7cddf 405struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
fb2b3c9f
PDS
406 void *data, const struct file_operations *fops)
407{
408 struct dentry *d = NULL;
409
035a61c3
TV
410 if (hw->core->dentry)
411 d = debugfs_create_file(name, mode, hw->core->dentry, data,
412 fops);
fb2b3c9f
PDS
413
414 return d;
415}
416EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
417
b2476490
MT
418/**
419 * clk_debug_init - lazily create the debugfs clk tree visualization
420 *
421 * clks are often initialized very early during boot before memory can
422 * be dynamically allocated and well before debugfs is setup.
423 * clk_debug_init walks the clk tree hierarchy while holding
424 * prepare_lock and creates the topology as part of a late_initcall,
425 * thus insuring that clks initialized very early will still be
426 * represented in the debugfs clk tree. This function should only be
427 * called once at boot-time, and all other clks added dynamically will
428 * be done so with clk_debug_register.
429 */
430static int __init clk_debug_init(void)
431{
035a61c3 432 struct clk_core *clk;
1af599df 433 struct dentry *d;
b2476490
MT
434
435 rootdir = debugfs_create_dir("clk", NULL);
436
437 if (!rootdir)
438 return -ENOMEM;
439
27b8d5f7 440 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
1af599df
PG
441 &clk_summary_fops);
442 if (!d)
443 return -ENOMEM;
444
27b8d5f7 445 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
bddca894
PG
446 &clk_dump_fops);
447 if (!d)
448 return -ENOMEM;
449
27b8d5f7
PDS
450 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
451 &orphan_list, &clk_summary_fops);
452 if (!d)
453 return -ENOMEM;
b2476490 454
27b8d5f7
PDS
455 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
456 &orphan_list, &clk_dump_fops);
457 if (!d)
b2476490
MT
458 return -ENOMEM;
459
6314b679
SB
460 mutex_lock(&clk_debug_lock);
461 hlist_for_each_entry(clk, &clk_debug_list, debug_node)
462 clk_debug_create_one(clk, rootdir);
b2476490
MT
463
464 inited = 1;
6314b679 465 mutex_unlock(&clk_debug_lock);
b2476490
MT
466
467 return 0;
468}
469late_initcall(clk_debug_init);
470#else
035a61c3
TV
471static inline int clk_debug_register(struct clk_core *clk) { return 0; }
472static inline void clk_debug_reparent(struct clk_core *clk,
473 struct clk_core *new_parent)
b33d212f
UH
474{
475}
035a61c3 476static inline void clk_debug_unregister(struct clk_core *clk)
fcb0ee6a
SN
477{
478}
70d347e6 479#endif
b2476490 480
1c155b3d 481/* caller must hold prepare_lock */
035a61c3 482static void clk_unprepare_unused_subtree(struct clk_core *clk)
1c155b3d 483{
035a61c3 484 struct clk_core *child;
1c155b3d 485
496eadf8
KK
486 lockdep_assert_held(&prepare_lock);
487
1c155b3d
UH
488 hlist_for_each_entry(child, &clk->children, child_node)
489 clk_unprepare_unused_subtree(child);
490
491 if (clk->prepare_count)
492 return;
493
494 if (clk->flags & CLK_IGNORE_UNUSED)
495 return;
496
035a61c3 497 if (clk_core_is_prepared(clk)) {
dfc202ea 498 trace_clk_unprepare(clk);
3cc8247f
UH
499 if (clk->ops->unprepare_unused)
500 clk->ops->unprepare_unused(clk->hw);
501 else if (clk->ops->unprepare)
1c155b3d 502 clk->ops->unprepare(clk->hw);
dfc202ea 503 trace_clk_unprepare_complete(clk);
3cc8247f 504 }
1c155b3d
UH
505}
506
b2476490 507/* caller must hold prepare_lock */
035a61c3 508static void clk_disable_unused_subtree(struct clk_core *clk)
b2476490 509{
035a61c3 510 struct clk_core *child;
b2476490
MT
511 unsigned long flags;
512
496eadf8
KK
513 lockdep_assert_held(&prepare_lock);
514
b67bfe0d 515 hlist_for_each_entry(child, &clk->children, child_node)
b2476490
MT
516 clk_disable_unused_subtree(child);
517
eab89f69 518 flags = clk_enable_lock();
b2476490
MT
519
520 if (clk->enable_count)
521 goto unlock_out;
522
523 if (clk->flags & CLK_IGNORE_UNUSED)
524 goto unlock_out;
525
7c045a55
MT
526 /*
527 * some gate clocks have special needs during the disable-unused
528 * sequence. call .disable_unused if available, otherwise fall
529 * back to .disable
530 */
035a61c3 531 if (clk_core_is_enabled(clk)) {
dfc202ea 532 trace_clk_disable(clk);
7c045a55
MT
533 if (clk->ops->disable_unused)
534 clk->ops->disable_unused(clk->hw);
535 else if (clk->ops->disable)
536 clk->ops->disable(clk->hw);
dfc202ea 537 trace_clk_disable_complete(clk);
7c045a55 538 }
b2476490
MT
539
540unlock_out:
eab89f69 541 clk_enable_unlock(flags);
b2476490
MT
542}
543
1e435256
OJ
544static bool clk_ignore_unused;
545static int __init clk_ignore_unused_setup(char *__unused)
546{
547 clk_ignore_unused = true;
548 return 1;
549}
550__setup("clk_ignore_unused", clk_ignore_unused_setup);
551
b2476490
MT
552static int clk_disable_unused(void)
553{
035a61c3 554 struct clk_core *clk;
b2476490 555
1e435256
OJ
556 if (clk_ignore_unused) {
557 pr_warn("clk: Not disabling unused clocks\n");
558 return 0;
559 }
560
eab89f69 561 clk_prepare_lock();
b2476490 562
b67bfe0d 563 hlist_for_each_entry(clk, &clk_root_list, child_node)
b2476490
MT
564 clk_disable_unused_subtree(clk);
565
b67bfe0d 566 hlist_for_each_entry(clk, &clk_orphan_list, child_node)
b2476490
MT
567 clk_disable_unused_subtree(clk);
568
1c155b3d
UH
569 hlist_for_each_entry(clk, &clk_root_list, child_node)
570 clk_unprepare_unused_subtree(clk);
571
572 hlist_for_each_entry(clk, &clk_orphan_list, child_node)
573 clk_unprepare_unused_subtree(clk);
574
eab89f69 575 clk_prepare_unlock();
b2476490
MT
576
577 return 0;
578}
d41d5805 579late_initcall_sync(clk_disable_unused);
b2476490
MT
580
581/*** helper functions ***/
582
65800b2c 583const char *__clk_get_name(struct clk *clk)
b2476490 584{
035a61c3 585 return !clk ? NULL : clk->core->name;
b2476490 586}
4895084c 587EXPORT_SYMBOL_GPL(__clk_get_name);
b2476490 588
65800b2c 589struct clk_hw *__clk_get_hw(struct clk *clk)
b2476490 590{
035a61c3 591 return !clk ? NULL : clk->core->hw;
b2476490 592}
0b7f04b8 593EXPORT_SYMBOL_GPL(__clk_get_hw);
b2476490 594
65800b2c 595u8 __clk_get_num_parents(struct clk *clk)
b2476490 596{
035a61c3 597 return !clk ? 0 : clk->core->num_parents;
b2476490 598}
0b7f04b8 599EXPORT_SYMBOL_GPL(__clk_get_num_parents);
b2476490 600
65800b2c 601struct clk *__clk_get_parent(struct clk *clk)
b2476490 602{
035a61c3
TV
603 if (!clk)
604 return NULL;
605
606 /* TODO: Create a per-user clk and change callers to call clk_put */
607 return !clk->core->parent ? NULL : clk->core->parent->hw->clk;
b2476490 608}
0b7f04b8 609EXPORT_SYMBOL_GPL(__clk_get_parent);
b2476490 610
035a61c3
TV
611static struct clk_core *clk_core_get_parent_by_index(struct clk_core *clk,
612 u8 index)
7ef3dcc8
JH
613{
614 if (!clk || index >= clk->num_parents)
615 return NULL;
616 else if (!clk->parents)
035a61c3 617 return clk_core_lookup(clk->parent_names[index]);
7ef3dcc8
JH
618 else if (!clk->parents[index])
619 return clk->parents[index] =
035a61c3 620 clk_core_lookup(clk->parent_names[index]);
7ef3dcc8
JH
621 else
622 return clk->parents[index];
623}
035a61c3
TV
624
625struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
626{
627 struct clk_core *parent;
628
629 if (!clk)
630 return NULL;
631
632 parent = clk_core_get_parent_by_index(clk->core, index);
633
634 return !parent ? NULL : parent->hw->clk;
635}
0b7f04b8 636EXPORT_SYMBOL_GPL(clk_get_parent_by_index);
7ef3dcc8 637
65800b2c 638unsigned int __clk_get_enable_count(struct clk *clk)
b2476490 639{
035a61c3 640 return !clk ? 0 : clk->core->enable_count;
b2476490
MT
641}
642
035a61c3 643static unsigned long clk_core_get_rate_nolock(struct clk_core *clk)
b2476490
MT
644{
645 unsigned long ret;
646
647 if (!clk) {
34e44fe8 648 ret = 0;
b2476490
MT
649 goto out;
650 }
651
652 ret = clk->rate;
653
654 if (clk->flags & CLK_IS_ROOT)
655 goto out;
656
657 if (!clk->parent)
34e44fe8 658 ret = 0;
b2476490
MT
659
660out:
661 return ret;
662}
035a61c3
TV
663
664unsigned long __clk_get_rate(struct clk *clk)
665{
666 if (!clk)
667 return 0;
668
669 return clk_core_get_rate_nolock(clk->core);
670}
0b7f04b8 671EXPORT_SYMBOL_GPL(__clk_get_rate);
b2476490 672
035a61c3 673static unsigned long __clk_get_accuracy(struct clk_core *clk)
5279fc40
BB
674{
675 if (!clk)
676 return 0;
677
678 return clk->accuracy;
679}
680
65800b2c 681unsigned long __clk_get_flags(struct clk *clk)
b2476490 682{
035a61c3 683 return !clk ? 0 : clk->core->flags;
b2476490 684}
b05c6836 685EXPORT_SYMBOL_GPL(__clk_get_flags);
b2476490 686
035a61c3 687static bool clk_core_is_prepared(struct clk_core *clk)
3d6ee287
UH
688{
689 int ret;
690
691 if (!clk)
692 return false;
693
694 /*
695 * .is_prepared is optional for clocks that can prepare
696 * fall back to software usage counter if it is missing
697 */
698 if (!clk->ops->is_prepared) {
699 ret = clk->prepare_count ? 1 : 0;
700 goto out;
701 }
702
703 ret = clk->ops->is_prepared(clk->hw);
704out:
705 return !!ret;
706}
707
035a61c3
TV
708bool __clk_is_prepared(struct clk *clk)
709{
710 if (!clk)
711 return false;
712
713 return clk_core_is_prepared(clk->core);
714}
715
716static bool clk_core_is_enabled(struct clk_core *clk)
b2476490
MT
717{
718 int ret;
719
720 if (!clk)
2ac6b1f5 721 return false;
b2476490
MT
722
723 /*
724 * .is_enabled is only mandatory for clocks that gate
725 * fall back to software usage counter if .is_enabled is missing
726 */
727 if (!clk->ops->is_enabled) {
728 ret = clk->enable_count ? 1 : 0;
729 goto out;
730 }
731
732 ret = clk->ops->is_enabled(clk->hw);
733out:
2ac6b1f5 734 return !!ret;
b2476490 735}
035a61c3
TV
736
737bool __clk_is_enabled(struct clk *clk)
738{
739 if (!clk)
740 return false;
741
742 return clk_core_is_enabled(clk->core);
743}
0b7f04b8 744EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 745
035a61c3
TV
746static struct clk_core *__clk_lookup_subtree(const char *name,
747 struct clk_core *clk)
b2476490 748{
035a61c3
TV
749 struct clk_core *child;
750 struct clk_core *ret;
b2476490
MT
751
752 if (!strcmp(clk->name, name))
753 return clk;
754
b67bfe0d 755 hlist_for_each_entry(child, &clk->children, child_node) {
b2476490
MT
756 ret = __clk_lookup_subtree(name, child);
757 if (ret)
758 return ret;
759 }
760
761 return NULL;
762}
763
035a61c3 764static struct clk_core *clk_core_lookup(const char *name)
b2476490 765{
035a61c3
TV
766 struct clk_core *root_clk;
767 struct clk_core *ret;
b2476490
MT
768
769 if (!name)
770 return NULL;
771
772 /* search the 'proper' clk tree first */
b67bfe0d 773 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
b2476490
MT
774 ret = __clk_lookup_subtree(name, root_clk);
775 if (ret)
776 return ret;
777 }
778
779 /* if not found, then search the orphan tree */
b67bfe0d 780 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
b2476490
MT
781 ret = __clk_lookup_subtree(name, root_clk);
782 if (ret)
783 return ret;
784 }
785
786 return NULL;
787}
788
15a02c1f
SB
789static bool mux_is_better_rate(unsigned long rate, unsigned long now,
790 unsigned long best, unsigned long flags)
e366fdd7 791{
15a02c1f
SB
792 if (flags & CLK_MUX_ROUND_CLOSEST)
793 return abs(now - rate) < abs(best - rate);
794
795 return now <= rate && now > best;
796}
797
798static long
799clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
800 unsigned long min_rate,
801 unsigned long max_rate,
15a02c1f
SB
802 unsigned long *best_parent_rate,
803 struct clk_hw **best_parent_p,
804 unsigned long flags)
e366fdd7 805{
035a61c3 806 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
e366fdd7
JH
807 int i, num_parents;
808 unsigned long parent_rate, best = 0;
809
810 /* if NO_REPARENT flag set, pass through to current parent */
035a61c3
TV
811 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
812 parent = core->parent;
813 if (core->flags & CLK_SET_RATE_PARENT)
9e0ad7d2
JMC
814 best = __clk_determine_rate(parent ? parent->hw : NULL,
815 rate, min_rate, max_rate);
e366fdd7 816 else if (parent)
035a61c3 817 best = clk_core_get_rate_nolock(parent);
e366fdd7 818 else
035a61c3 819 best = clk_core_get_rate_nolock(core);
e366fdd7
JH
820 goto out;
821 }
822
823 /* find the parent that can provide the fastest rate <= rate */
035a61c3 824 num_parents = core->num_parents;
e366fdd7 825 for (i = 0; i < num_parents; i++) {
035a61c3 826 parent = clk_core_get_parent_by_index(core, i);
e366fdd7
JH
827 if (!parent)
828 continue;
035a61c3 829 if (core->flags & CLK_SET_RATE_PARENT)
1c8e6004
TV
830 parent_rate = __clk_determine_rate(parent->hw, rate,
831 min_rate,
832 max_rate);
e366fdd7 833 else
035a61c3 834 parent_rate = clk_core_get_rate_nolock(parent);
15a02c1f 835 if (mux_is_better_rate(rate, parent_rate, best, flags)) {
e366fdd7
JH
836 best_parent = parent;
837 best = parent_rate;
838 }
839 }
840
841out:
842 if (best_parent)
646cafc6 843 *best_parent_p = best_parent->hw;
e366fdd7
JH
844 *best_parent_rate = best;
845
846 return best;
847}
15a02c1f 848
035a61c3
TV
849struct clk *__clk_lookup(const char *name)
850{
851 struct clk_core *core = clk_core_lookup(name);
852
853 return !core ? NULL : core->hw->clk;
854}
855
1c8e6004
TV
856static void clk_core_get_boundaries(struct clk_core *clk,
857 unsigned long *min_rate,
858 unsigned long *max_rate)
859{
860 struct clk *clk_user;
861
862 *min_rate = 0;
863 *max_rate = ULONG_MAX;
864
865 hlist_for_each_entry(clk_user, &clk->clks, child_node)
866 *min_rate = max(*min_rate, clk_user->min_rate);
867
868 hlist_for_each_entry(clk_user, &clk->clks, child_node)
869 *max_rate = min(*max_rate, clk_user->max_rate);
870}
871
15a02c1f
SB
872/*
873 * Helper for finding best parent to provide a given frequency. This can be used
874 * directly as a determine_rate callback (e.g. for a mux), or from a more
875 * complex clock that may combine a mux with other operations.
876 */
877long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
878 unsigned long min_rate,
879 unsigned long max_rate,
15a02c1f
SB
880 unsigned long *best_parent_rate,
881 struct clk_hw **best_parent_p)
882{
1c8e6004
TV
883 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
884 best_parent_rate,
15a02c1f
SB
885 best_parent_p, 0);
886}
0b7f04b8 887EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
e366fdd7 888
15a02c1f 889long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
890 unsigned long min_rate,
891 unsigned long max_rate,
15a02c1f
SB
892 unsigned long *best_parent_rate,
893 struct clk_hw **best_parent_p)
894{
1c8e6004
TV
895 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
896 best_parent_rate,
15a02c1f
SB
897 best_parent_p,
898 CLK_MUX_ROUND_CLOSEST);
899}
900EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
901
b2476490
MT
902/*** clk api ***/
903
035a61c3 904static void clk_core_unprepare(struct clk_core *clk)
b2476490
MT
905{
906 if (!clk)
907 return;
908
909 if (WARN_ON(clk->prepare_count == 0))
910 return;
911
912 if (--clk->prepare_count > 0)
913 return;
914
915 WARN_ON(clk->enable_count > 0);
916
dfc202ea
SB
917 trace_clk_unprepare(clk);
918
b2476490
MT
919 if (clk->ops->unprepare)
920 clk->ops->unprepare(clk->hw);
921
dfc202ea 922 trace_clk_unprepare_complete(clk);
035a61c3 923 clk_core_unprepare(clk->parent);
b2476490
MT
924}
925
926/**
927 * clk_unprepare - undo preparation of a clock source
24ee1a08 928 * @clk: the clk being unprepared
b2476490
MT
929 *
930 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
931 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
932 * if the operation may sleep. One example is a clk which is accessed over
933 * I2c. In the complex case a clk gate operation may require a fast and a slow
934 * part. It is this reason that clk_unprepare and clk_disable are not mutually
935 * exclusive. In fact clk_disable must be called before clk_unprepare.
936 */
937void clk_unprepare(struct clk *clk)
938{
63589e92
SB
939 if (IS_ERR_OR_NULL(clk))
940 return;
941
eab89f69 942 clk_prepare_lock();
035a61c3 943 clk_core_unprepare(clk->core);
eab89f69 944 clk_prepare_unlock();
b2476490
MT
945}
946EXPORT_SYMBOL_GPL(clk_unprepare);
947
035a61c3 948static int clk_core_prepare(struct clk_core *clk)
b2476490
MT
949{
950 int ret = 0;
951
952 if (!clk)
953 return 0;
954
955 if (clk->prepare_count == 0) {
035a61c3 956 ret = clk_core_prepare(clk->parent);
b2476490
MT
957 if (ret)
958 return ret;
959
dfc202ea
SB
960 trace_clk_prepare(clk);
961
962 if (clk->ops->prepare)
b2476490 963 ret = clk->ops->prepare(clk->hw);
dfc202ea
SB
964
965 trace_clk_prepare_complete(clk);
966
967 if (ret) {
968 clk_core_unprepare(clk->parent);
969 return ret;
b2476490
MT
970 }
971 }
972
973 clk->prepare_count++;
974
975 return 0;
976}
977
978/**
979 * clk_prepare - prepare a clock source
980 * @clk: the clk being prepared
981 *
982 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
983 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
984 * operation may sleep. One example is a clk which is accessed over I2c. In
985 * the complex case a clk ungate operation may require a fast and a slow part.
986 * It is this reason that clk_prepare and clk_enable are not mutually
987 * exclusive. In fact clk_prepare must be called before clk_enable.
988 * Returns 0 on success, -EERROR otherwise.
989 */
990int clk_prepare(struct clk *clk)
991{
992 int ret;
993
035a61c3
TV
994 if (!clk)
995 return 0;
996
eab89f69 997 clk_prepare_lock();
035a61c3 998 ret = clk_core_prepare(clk->core);
eab89f69 999 clk_prepare_unlock();
b2476490
MT
1000
1001 return ret;
1002}
1003EXPORT_SYMBOL_GPL(clk_prepare);
1004
035a61c3 1005static void clk_core_disable(struct clk_core *clk)
b2476490
MT
1006{
1007 if (!clk)
1008 return;
1009
1010 if (WARN_ON(clk->enable_count == 0))
1011 return;
1012
1013 if (--clk->enable_count > 0)
1014 return;
1015
dfc202ea
SB
1016 trace_clk_disable(clk);
1017
b2476490
MT
1018 if (clk->ops->disable)
1019 clk->ops->disable(clk->hw);
1020
dfc202ea
SB
1021 trace_clk_disable_complete(clk);
1022
035a61c3
TV
1023 clk_core_disable(clk->parent);
1024}
1025
1026static void __clk_disable(struct clk *clk)
1027{
1028 if (!clk)
1029 return;
1030
1031 clk_core_disable(clk->core);
b2476490
MT
1032}
1033
1034/**
1035 * clk_disable - gate a clock
1036 * @clk: the clk being gated
1037 *
1038 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
1039 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
1040 * clk if the operation is fast and will never sleep. One example is a
1041 * SoC-internal clk which is controlled via simple register writes. In the
1042 * complex case a clk gate operation may require a fast and a slow part. It is
1043 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
1044 * In fact clk_disable must be called before clk_unprepare.
1045 */
1046void clk_disable(struct clk *clk)
1047{
1048 unsigned long flags;
1049
63589e92
SB
1050 if (IS_ERR_OR_NULL(clk))
1051 return;
1052
eab89f69 1053 flags = clk_enable_lock();
b2476490 1054 __clk_disable(clk);
eab89f69 1055 clk_enable_unlock(flags);
b2476490
MT
1056}
1057EXPORT_SYMBOL_GPL(clk_disable);
1058
035a61c3 1059static int clk_core_enable(struct clk_core *clk)
b2476490
MT
1060{
1061 int ret = 0;
1062
1063 if (!clk)
1064 return 0;
1065
1066 if (WARN_ON(clk->prepare_count == 0))
1067 return -ESHUTDOWN;
1068
1069 if (clk->enable_count == 0) {
035a61c3 1070 ret = clk_core_enable(clk->parent);
b2476490
MT
1071
1072 if (ret)
1073 return ret;
1074
dfc202ea
SB
1075 trace_clk_enable(clk);
1076
1077 if (clk->ops->enable)
b2476490 1078 ret = clk->ops->enable(clk->hw);
dfc202ea
SB
1079
1080 trace_clk_enable_complete(clk);
1081
1082 if (ret) {
1083 clk_core_disable(clk->parent);
1084 return ret;
b2476490
MT
1085 }
1086 }
1087
1088 clk->enable_count++;
1089 return 0;
1090}
1091
035a61c3
TV
1092static int __clk_enable(struct clk *clk)
1093{
1094 if (!clk)
1095 return 0;
1096
1097 return clk_core_enable(clk->core);
1098}
1099
b2476490
MT
1100/**
1101 * clk_enable - ungate a clock
1102 * @clk: the clk being ungated
1103 *
1104 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
1105 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
1106 * if the operation will never sleep. One example is a SoC-internal clk which
1107 * is controlled via simple register writes. In the complex case a clk ungate
1108 * operation may require a fast and a slow part. It is this reason that
1109 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
1110 * must be called before clk_enable. Returns 0 on success, -EERROR
1111 * otherwise.
1112 */
1113int clk_enable(struct clk *clk)
1114{
1115 unsigned long flags;
1116 int ret;
1117
eab89f69 1118 flags = clk_enable_lock();
b2476490 1119 ret = __clk_enable(clk);
eab89f69 1120 clk_enable_unlock(flags);
b2476490
MT
1121
1122 return ret;
1123}
1124EXPORT_SYMBOL_GPL(clk_enable);
1125
035a61c3 1126static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
1c8e6004
TV
1127 unsigned long rate,
1128 unsigned long min_rate,
1129 unsigned long max_rate)
b2476490 1130{
81536e07 1131 unsigned long parent_rate = 0;
035a61c3 1132 struct clk_core *parent;
646cafc6 1133 struct clk_hw *parent_hw;
b2476490 1134
496eadf8
KK
1135 lockdep_assert_held(&prepare_lock);
1136
b2476490 1137 if (!clk)
2ac6b1f5 1138 return 0;
b2476490 1139
71472c0c
JH
1140 parent = clk->parent;
1141 if (parent)
1142 parent_rate = parent->rate;
1143
646cafc6
TV
1144 if (clk->ops->determine_rate) {
1145 parent_hw = parent ? parent->hw : NULL;
1c8e6004
TV
1146 return clk->ops->determine_rate(clk->hw, rate,
1147 min_rate, max_rate,
1148 &parent_rate, &parent_hw);
646cafc6 1149 } else if (clk->ops->round_rate)
71472c0c
JH
1150 return clk->ops->round_rate(clk->hw, rate, &parent_rate);
1151 else if (clk->flags & CLK_SET_RATE_PARENT)
1c8e6004
TV
1152 return clk_core_round_rate_nolock(clk->parent, rate, min_rate,
1153 max_rate);
71472c0c
JH
1154 else
1155 return clk->rate;
b2476490 1156}
035a61c3 1157
1c8e6004
TV
1158/**
1159 * __clk_determine_rate - get the closest rate actually supported by a clock
1160 * @hw: determine the rate of this clock
1161 * @rate: target rate
1162 * @min_rate: returned rate must be greater than this rate
1163 * @max_rate: returned rate must be less than this rate
1164 *
1165 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate and
1166 * .determine_rate.
1167 */
1168unsigned long __clk_determine_rate(struct clk_hw *hw,
1169 unsigned long rate,
1170 unsigned long min_rate,
1171 unsigned long max_rate)
1172{
1173 if (!hw)
1174 return 0;
1175
1176 return clk_core_round_rate_nolock(hw->core, rate, min_rate, max_rate);
1177}
1178EXPORT_SYMBOL_GPL(__clk_determine_rate);
1179
035a61c3
TV
1180/**
1181 * __clk_round_rate - round the given rate for a clk
1182 * @clk: round the rate of this clock
1183 * @rate: the rate which is to be rounded
1184 *
1185 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate
1186 */
1187unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
1188{
1c8e6004
TV
1189 unsigned long min_rate;
1190 unsigned long max_rate;
1191
035a61c3
TV
1192 if (!clk)
1193 return 0;
1194
1c8e6004
TV
1195 clk_core_get_boundaries(clk->core, &min_rate, &max_rate);
1196
1197 return clk_core_round_rate_nolock(clk->core, rate, min_rate, max_rate);
035a61c3 1198}
1cdf8ee2 1199EXPORT_SYMBOL_GPL(__clk_round_rate);
b2476490
MT
1200
1201/**
1202 * clk_round_rate - round the given rate for a clk
1203 * @clk: the clk for which we are rounding a rate
1204 * @rate: the rate which is to be rounded
1205 *
1206 * Takes in a rate as input and rounds it to a rate that the clk can actually
1207 * use which is then returned. If clk doesn't support round_rate operation
1208 * then the parent rate is returned.
1209 */
1210long clk_round_rate(struct clk *clk, unsigned long rate)
1211{
1212 unsigned long ret;
1213
035a61c3
TV
1214 if (!clk)
1215 return 0;
1216
eab89f69 1217 clk_prepare_lock();
b2476490 1218 ret = __clk_round_rate(clk, rate);
eab89f69 1219 clk_prepare_unlock();
b2476490
MT
1220
1221 return ret;
1222}
1223EXPORT_SYMBOL_GPL(clk_round_rate);
1224
1225/**
1226 * __clk_notify - call clk notifier chain
1227 * @clk: struct clk * that is changing rate
1228 * @msg: clk notifier type (see include/linux/clk.h)
1229 * @old_rate: old clk rate
1230 * @new_rate: new clk rate
1231 *
1232 * Triggers a notifier call chain on the clk rate-change notification
1233 * for 'clk'. Passes a pointer to the struct clk and the previous
1234 * and current rates to the notifier callback. Intended to be called by
1235 * internal clock code only. Returns NOTIFY_DONE from the last driver
1236 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
1237 * a driver returns that.
1238 */
035a61c3 1239static int __clk_notify(struct clk_core *clk, unsigned long msg,
b2476490
MT
1240 unsigned long old_rate, unsigned long new_rate)
1241{
1242 struct clk_notifier *cn;
1243 struct clk_notifier_data cnd;
1244 int ret = NOTIFY_DONE;
1245
b2476490
MT
1246 cnd.old_rate = old_rate;
1247 cnd.new_rate = new_rate;
1248
1249 list_for_each_entry(cn, &clk_notifier_list, node) {
035a61c3
TV
1250 if (cn->clk->core == clk) {
1251 cnd.clk = cn->clk;
b2476490
MT
1252 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
1253 &cnd);
b2476490
MT
1254 }
1255 }
1256
1257 return ret;
1258}
1259
5279fc40
BB
1260/**
1261 * __clk_recalc_accuracies
1262 * @clk: first clk in the subtree
1263 *
1264 * Walks the subtree of clks starting with clk and recalculates accuracies as
1265 * it goes. Note that if a clk does not implement the .recalc_accuracy
1266 * callback then it is assumed that the clock will take on the accuracy of it's
1267 * parent.
1268 *
1269 * Caller must hold prepare_lock.
1270 */
035a61c3 1271static void __clk_recalc_accuracies(struct clk_core *clk)
5279fc40
BB
1272{
1273 unsigned long parent_accuracy = 0;
035a61c3 1274 struct clk_core *child;
5279fc40 1275
496eadf8
KK
1276 lockdep_assert_held(&prepare_lock);
1277
5279fc40
BB
1278 if (clk->parent)
1279 parent_accuracy = clk->parent->accuracy;
1280
1281 if (clk->ops->recalc_accuracy)
1282 clk->accuracy = clk->ops->recalc_accuracy(clk->hw,
1283 parent_accuracy);
1284 else
1285 clk->accuracy = parent_accuracy;
1286
1287 hlist_for_each_entry(child, &clk->children, child_node)
1288 __clk_recalc_accuracies(child);
1289}
1290
035a61c3
TV
1291static long clk_core_get_accuracy(struct clk_core *clk)
1292{
1293 unsigned long accuracy;
1294
1295 clk_prepare_lock();
1296 if (clk && (clk->flags & CLK_GET_ACCURACY_NOCACHE))
1297 __clk_recalc_accuracies(clk);
1298
1299 accuracy = __clk_get_accuracy(clk);
1300 clk_prepare_unlock();
1301
1302 return accuracy;
1303}
1304
5279fc40
BB
1305/**
1306 * clk_get_accuracy - return the accuracy of clk
1307 * @clk: the clk whose accuracy is being returned
1308 *
1309 * Simply returns the cached accuracy of the clk, unless
1310 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
1311 * issued.
1312 * If clk is NULL then returns 0.
1313 */
1314long clk_get_accuracy(struct clk *clk)
1315{
035a61c3
TV
1316 if (!clk)
1317 return 0;
5279fc40 1318
035a61c3 1319 return clk_core_get_accuracy(clk->core);
5279fc40
BB
1320}
1321EXPORT_SYMBOL_GPL(clk_get_accuracy);
1322
035a61c3
TV
1323static unsigned long clk_recalc(struct clk_core *clk,
1324 unsigned long parent_rate)
8f2c2db1
SB
1325{
1326 if (clk->ops->recalc_rate)
1327 return clk->ops->recalc_rate(clk->hw, parent_rate);
1328 return parent_rate;
1329}
1330
b2476490
MT
1331/**
1332 * __clk_recalc_rates
1333 * @clk: first clk in the subtree
1334 * @msg: notification type (see include/linux/clk.h)
1335 *
1336 * Walks the subtree of clks starting with clk and recalculates rates as it
1337 * goes. Note that if a clk does not implement the .recalc_rate callback then
24ee1a08 1338 * it is assumed that the clock will take on the rate of its parent.
b2476490
MT
1339 *
1340 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1341 * if necessary.
1342 *
1343 * Caller must hold prepare_lock.
1344 */
035a61c3 1345static void __clk_recalc_rates(struct clk_core *clk, unsigned long msg)
b2476490
MT
1346{
1347 unsigned long old_rate;
1348 unsigned long parent_rate = 0;
035a61c3 1349 struct clk_core *child;
b2476490 1350
496eadf8
KK
1351 lockdep_assert_held(&prepare_lock);
1352
b2476490
MT
1353 old_rate = clk->rate;
1354
1355 if (clk->parent)
1356 parent_rate = clk->parent->rate;
1357
8f2c2db1 1358 clk->rate = clk_recalc(clk, parent_rate);
b2476490
MT
1359
1360 /*
1361 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1362 * & ABORT_RATE_CHANGE notifiers
1363 */
1364 if (clk->notifier_count && msg)
1365 __clk_notify(clk, msg, old_rate, clk->rate);
1366
b67bfe0d 1367 hlist_for_each_entry(child, &clk->children, child_node)
b2476490
MT
1368 __clk_recalc_rates(child, msg);
1369}
1370
035a61c3 1371static unsigned long clk_core_get_rate(struct clk_core *clk)
a093bde2
UH
1372{
1373 unsigned long rate;
1374
eab89f69 1375 clk_prepare_lock();
a093bde2
UH
1376
1377 if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
1378 __clk_recalc_rates(clk, 0);
1379
035a61c3 1380 rate = clk_core_get_rate_nolock(clk);
eab89f69 1381 clk_prepare_unlock();
a093bde2
UH
1382
1383 return rate;
1384}
035a61c3
TV
1385EXPORT_SYMBOL_GPL(clk_core_get_rate);
1386
1387/**
1388 * clk_get_rate - return the rate of clk
1389 * @clk: the clk whose rate is being returned
1390 *
1391 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1392 * is set, which means a recalc_rate will be issued.
1393 * If clk is NULL then returns 0.
1394 */
1395unsigned long clk_get_rate(struct clk *clk)
1396{
1397 if (!clk)
1398 return 0;
1399
1400 return clk_core_get_rate(clk->core);
1401}
a093bde2
UH
1402EXPORT_SYMBOL_GPL(clk_get_rate);
1403
035a61c3
TV
1404static int clk_fetch_parent_index(struct clk_core *clk,
1405 struct clk_core *parent)
4935b22c 1406{
f1c8b2ed 1407 int i;
4935b22c 1408
f1c8b2ed 1409 if (!clk->parents) {
96a7ed90
TF
1410 clk->parents = kcalloc(clk->num_parents,
1411 sizeof(struct clk *), GFP_KERNEL);
f1c8b2ed
TF
1412 if (!clk->parents)
1413 return -ENOMEM;
1414 }
4935b22c
JH
1415
1416 /*
1417 * find index of new parent clock using cached parent ptrs,
1418 * or if not yet cached, use string name comparison and cache
035a61c3 1419 * them now to avoid future calls to clk_core_lookup.
4935b22c
JH
1420 */
1421 for (i = 0; i < clk->num_parents; i++) {
da0f0b2c 1422 if (clk->parents[i] == parent)
f1c8b2ed 1423 return i;
da0f0b2c
TF
1424
1425 if (clk->parents[i])
1426 continue;
1427
1428 if (!strcmp(clk->parent_names[i], parent->name)) {
035a61c3 1429 clk->parents[i] = clk_core_lookup(parent->name);
f1c8b2ed 1430 return i;
4935b22c
JH
1431 }
1432 }
1433
f1c8b2ed 1434 return -EINVAL;
4935b22c
JH
1435}
1436
035a61c3 1437static void clk_reparent(struct clk_core *clk, struct clk_core *new_parent)
4935b22c
JH
1438{
1439 hlist_del(&clk->child_node);
1440
903efc55
JH
1441 if (new_parent) {
1442 /* avoid duplicate POST_RATE_CHANGE notifications */
1443 if (new_parent->new_child == clk)
1444 new_parent->new_child = NULL;
1445
4935b22c 1446 hlist_add_head(&clk->child_node, &new_parent->children);
903efc55 1447 } else {
4935b22c 1448 hlist_add_head(&clk->child_node, &clk_orphan_list);
903efc55 1449 }
4935b22c
JH
1450
1451 clk->parent = new_parent;
1452}
1453
035a61c3
TV
1454static struct clk_core *__clk_set_parent_before(struct clk_core *clk,
1455 struct clk_core *parent)
4935b22c
JH
1456{
1457 unsigned long flags;
035a61c3 1458 struct clk_core *old_parent = clk->parent;
4935b22c
JH
1459
1460 /*
1461 * Migrate prepare state between parents and prevent race with
1462 * clk_enable().
1463 *
1464 * If the clock is not prepared, then a race with
1465 * clk_enable/disable() is impossible since we already have the
1466 * prepare lock (future calls to clk_enable() need to be preceded by
1467 * a clk_prepare()).
1468 *
1469 * If the clock is prepared, migrate the prepared state to the new
1470 * parent and also protect against a race with clk_enable() by
1471 * forcing the clock and the new parent on. This ensures that all
1472 * future calls to clk_enable() are practically NOPs with respect to
1473 * hardware and software states.
1474 *
1475 * See also: Comment for clk_set_parent() below.
1476 */
1477 if (clk->prepare_count) {
035a61c3
TV
1478 clk_core_prepare(parent);
1479 clk_core_enable(parent);
1480 clk_core_enable(clk);
4935b22c
JH
1481 }
1482
1483 /* update the clk tree topology */
1484 flags = clk_enable_lock();
1485 clk_reparent(clk, parent);
1486 clk_enable_unlock(flags);
1487
3fa2252b
SB
1488 return old_parent;
1489}
1490
035a61c3
TV
1491static void __clk_set_parent_after(struct clk_core *core,
1492 struct clk_core *parent,
1493 struct clk_core *old_parent)
3fa2252b
SB
1494{
1495 /*
1496 * Finish the migration of prepare state and undo the changes done
1497 * for preventing a race with clk_enable().
1498 */
035a61c3
TV
1499 if (core->prepare_count) {
1500 clk_core_disable(core);
1501 clk_core_disable(old_parent);
1502 clk_core_unprepare(old_parent);
3fa2252b 1503 }
3fa2252b
SB
1504}
1505
035a61c3
TV
1506static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent,
1507 u8 p_index)
3fa2252b
SB
1508{
1509 unsigned long flags;
1510 int ret = 0;
035a61c3 1511 struct clk_core *old_parent;
3fa2252b
SB
1512
1513 old_parent = __clk_set_parent_before(clk, parent);
1514
dfc202ea
SB
1515 trace_clk_set_parent(clk, parent);
1516
4935b22c
JH
1517 /* change clock input source */
1518 if (parent && clk->ops->set_parent)
1519 ret = clk->ops->set_parent(clk->hw, p_index);
1520
dfc202ea
SB
1521 trace_clk_set_parent_complete(clk, parent);
1522
4935b22c
JH
1523 if (ret) {
1524 flags = clk_enable_lock();
1525 clk_reparent(clk, old_parent);
1526 clk_enable_unlock(flags);
1527
1528 if (clk->prepare_count) {
035a61c3
TV
1529 clk_core_disable(clk);
1530 clk_core_disable(parent);
1531 clk_core_unprepare(parent);
4935b22c
JH
1532 }
1533 return ret;
1534 }
1535
3fa2252b 1536 __clk_set_parent_after(clk, parent, old_parent);
4935b22c 1537
4935b22c
JH
1538 return 0;
1539}
1540
b2476490
MT
1541/**
1542 * __clk_speculate_rates
1543 * @clk: first clk in the subtree
1544 * @parent_rate: the "future" rate of clk's parent
1545 *
1546 * Walks the subtree of clks starting with clk, speculating rates as it
1547 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1548 *
1549 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1550 * pre-rate change notifications and returns early if no clks in the
1551 * subtree have subscribed to the notifications. Note that if a clk does not
1552 * implement the .recalc_rate callback then it is assumed that the clock will
24ee1a08 1553 * take on the rate of its parent.
b2476490
MT
1554 *
1555 * Caller must hold prepare_lock.
1556 */
035a61c3
TV
1557static int __clk_speculate_rates(struct clk_core *clk,
1558 unsigned long parent_rate)
b2476490 1559{
035a61c3 1560 struct clk_core *child;
b2476490
MT
1561 unsigned long new_rate;
1562 int ret = NOTIFY_DONE;
1563
496eadf8
KK
1564 lockdep_assert_held(&prepare_lock);
1565
8f2c2db1 1566 new_rate = clk_recalc(clk, parent_rate);
b2476490 1567
fb72a059 1568 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
b2476490
MT
1569 if (clk->notifier_count)
1570 ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
1571
86bcfa2e
MT
1572 if (ret & NOTIFY_STOP_MASK) {
1573 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1574 __func__, clk->name, ret);
b2476490 1575 goto out;
86bcfa2e 1576 }
b2476490 1577
b67bfe0d 1578 hlist_for_each_entry(child, &clk->children, child_node) {
b2476490 1579 ret = __clk_speculate_rates(child, new_rate);
fb72a059 1580 if (ret & NOTIFY_STOP_MASK)
b2476490
MT
1581 break;
1582 }
1583
1584out:
1585 return ret;
1586}
1587
035a61c3
TV
1588static void clk_calc_subtree(struct clk_core *clk, unsigned long new_rate,
1589 struct clk_core *new_parent, u8 p_index)
b2476490 1590{
035a61c3 1591 struct clk_core *child;
b2476490
MT
1592
1593 clk->new_rate = new_rate;
71472c0c
JH
1594 clk->new_parent = new_parent;
1595 clk->new_parent_index = p_index;
1596 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1597 clk->new_child = NULL;
1598 if (new_parent && new_parent != clk->parent)
1599 new_parent->new_child = clk;
b2476490 1600
b67bfe0d 1601 hlist_for_each_entry(child, &clk->children, child_node) {
8f2c2db1 1602 child->new_rate = clk_recalc(child, new_rate);
71472c0c 1603 clk_calc_subtree(child, child->new_rate, NULL, 0);
b2476490
MT
1604 }
1605}
1606
1607/*
1608 * calculate the new rates returning the topmost clock that has to be
1609 * changed.
1610 */
035a61c3
TV
1611static struct clk_core *clk_calc_new_rates(struct clk_core *clk,
1612 unsigned long rate)
b2476490 1613{
035a61c3
TV
1614 struct clk_core *top = clk;
1615 struct clk_core *old_parent, *parent;
646cafc6 1616 struct clk_hw *parent_hw;
81536e07 1617 unsigned long best_parent_rate = 0;
b2476490 1618 unsigned long new_rate;
1c8e6004
TV
1619 unsigned long min_rate;
1620 unsigned long max_rate;
f1c8b2ed 1621 int p_index = 0;
b2476490 1622
7452b219
MT
1623 /* sanity */
1624 if (IS_ERR_OR_NULL(clk))
1625 return NULL;
1626
63f5c3b2 1627 /* save parent rate, if it exists */
71472c0c
JH
1628 parent = old_parent = clk->parent;
1629 if (parent)
1630 best_parent_rate = parent->rate;
1631
1c8e6004
TV
1632 clk_core_get_boundaries(clk, &min_rate, &max_rate);
1633
71472c0c
JH
1634 /* find the closest rate and parent clk/rate */
1635 if (clk->ops->determine_rate) {
646cafc6 1636 parent_hw = parent ? parent->hw : NULL;
71472c0c 1637 new_rate = clk->ops->determine_rate(clk->hw, rate,
1c8e6004
TV
1638 min_rate,
1639 max_rate,
71472c0c 1640 &best_parent_rate,
646cafc6 1641 &parent_hw);
035a61c3 1642 parent = parent_hw ? parent_hw->core : NULL;
71472c0c
JH
1643 } else if (clk->ops->round_rate) {
1644 new_rate = clk->ops->round_rate(clk->hw, rate,
1645 &best_parent_rate);
1c8e6004
TV
1646 if (new_rate < min_rate || new_rate > max_rate)
1647 return NULL;
71472c0c
JH
1648 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
1649 /* pass-through clock without adjustable parent */
1650 clk->new_rate = clk->rate;
1651 return NULL;
1652 } else {
1653 /* pass-through clock with adjustable parent */
1654 top = clk_calc_new_rates(parent, rate);
1655 new_rate = parent->new_rate;
63f5c3b2 1656 goto out;
7452b219
MT
1657 }
1658
71472c0c
JH
1659 /* some clocks must be gated to change parent */
1660 if (parent != old_parent &&
1661 (clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
1662 pr_debug("%s: %s not gated but wants to reparent\n",
1663 __func__, clk->name);
b2476490
MT
1664 return NULL;
1665 }
1666
71472c0c 1667 /* try finding the new parent index */
4526e7b8 1668 if (parent && clk->num_parents > 1) {
71472c0c 1669 p_index = clk_fetch_parent_index(clk, parent);
f1c8b2ed 1670 if (p_index < 0) {
71472c0c
JH
1671 pr_debug("%s: clk %s can not be parent of clk %s\n",
1672 __func__, parent->name, clk->name);
1673 return NULL;
1674 }
b2476490
MT
1675 }
1676
71472c0c
JH
1677 if ((clk->flags & CLK_SET_RATE_PARENT) && parent &&
1678 best_parent_rate != parent->rate)
1679 top = clk_calc_new_rates(parent, best_parent_rate);
b2476490
MT
1680
1681out:
71472c0c 1682 clk_calc_subtree(clk, new_rate, parent, p_index);
b2476490
MT
1683
1684 return top;
1685}
1686
1687/*
1688 * Notify about rate changes in a subtree. Always walk down the whole tree
1689 * so that in case of an error we can walk down the whole tree again and
1690 * abort the change.
1691 */
035a61c3
TV
1692static struct clk_core *clk_propagate_rate_change(struct clk_core *clk,
1693 unsigned long event)
b2476490 1694{
035a61c3 1695 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1696 int ret = NOTIFY_DONE;
1697
1698 if (clk->rate == clk->new_rate)
5fda6858 1699 return NULL;
b2476490
MT
1700
1701 if (clk->notifier_count) {
1702 ret = __clk_notify(clk, event, clk->rate, clk->new_rate);
fb72a059 1703 if (ret & NOTIFY_STOP_MASK)
b2476490
MT
1704 fail_clk = clk;
1705 }
1706
b67bfe0d 1707 hlist_for_each_entry(child, &clk->children, child_node) {
71472c0c
JH
1708 /* Skip children who will be reparented to another clock */
1709 if (child->new_parent && child->new_parent != clk)
1710 continue;
1711 tmp_clk = clk_propagate_rate_change(child, event);
1712 if (tmp_clk)
1713 fail_clk = tmp_clk;
1714 }
1715
1716 /* handle the new child who might not be in clk->children yet */
1717 if (clk->new_child) {
1718 tmp_clk = clk_propagate_rate_change(clk->new_child, event);
1719 if (tmp_clk)
1720 fail_clk = tmp_clk;
b2476490
MT
1721 }
1722
1723 return fail_clk;
1724}
1725
1726/*
1727 * walk down a subtree and set the new rates notifying the rate
1728 * change on the way
1729 */
035a61c3 1730static void clk_change_rate(struct clk_core *clk)
b2476490 1731{
035a61c3 1732 struct clk_core *child;
067bb174 1733 struct hlist_node *tmp;
b2476490 1734 unsigned long old_rate;
bf47b4fd 1735 unsigned long best_parent_rate = 0;
3fa2252b 1736 bool skip_set_rate = false;
035a61c3 1737 struct clk_core *old_parent;
b2476490
MT
1738
1739 old_rate = clk->rate;
1740
3fa2252b
SB
1741 if (clk->new_parent)
1742 best_parent_rate = clk->new_parent->rate;
1743 else if (clk->parent)
bf47b4fd
PM
1744 best_parent_rate = clk->parent->rate;
1745
3fa2252b
SB
1746 if (clk->new_parent && clk->new_parent != clk->parent) {
1747 old_parent = __clk_set_parent_before(clk, clk->new_parent);
dfc202ea 1748 trace_clk_set_parent(clk, clk->new_parent);
3fa2252b
SB
1749
1750 if (clk->ops->set_rate_and_parent) {
1751 skip_set_rate = true;
1752 clk->ops->set_rate_and_parent(clk->hw, clk->new_rate,
1753 best_parent_rate,
1754 clk->new_parent_index);
1755 } else if (clk->ops->set_parent) {
1756 clk->ops->set_parent(clk->hw, clk->new_parent_index);
1757 }
1758
dfc202ea 1759 trace_clk_set_parent_complete(clk, clk->new_parent);
3fa2252b
SB
1760 __clk_set_parent_after(clk, clk->new_parent, old_parent);
1761 }
1762
dfc202ea
SB
1763 trace_clk_set_rate(clk, clk->new_rate);
1764
3fa2252b 1765 if (!skip_set_rate && clk->ops->set_rate)
bf47b4fd 1766 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate);
b2476490 1767
dfc202ea
SB
1768 trace_clk_set_rate_complete(clk, clk->new_rate);
1769
8f2c2db1 1770 clk->rate = clk_recalc(clk, best_parent_rate);
b2476490
MT
1771
1772 if (clk->notifier_count && old_rate != clk->rate)
1773 __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
1774
067bb174
TK
1775 /*
1776 * Use safe iteration, as change_rate can actually swap parents
1777 * for certain clock types.
1778 */
1779 hlist_for_each_entry_safe(child, tmp, &clk->children, child_node) {
71472c0c
JH
1780 /* Skip children who will be reparented to another clock */
1781 if (child->new_parent && child->new_parent != clk)
1782 continue;
b2476490 1783 clk_change_rate(child);
71472c0c
JH
1784 }
1785
1786 /* handle the new child who might not be in clk->children yet */
1787 if (clk->new_child)
1788 clk_change_rate(clk->new_child);
b2476490
MT
1789}
1790
1c8e6004
TV
1791static int clk_core_set_rate_nolock(struct clk_core *clk,
1792 unsigned long req_rate)
1793{
1794 struct clk_core *top, *fail_clk;
1795 unsigned long rate = req_rate;
1796 int ret = 0;
1797
1798 if (!clk)
1799 return 0;
1800
1801 /* bail early if nothing to do */
1802 if (rate == clk_core_get_rate_nolock(clk))
1803 return 0;
1804
1805 if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count)
1806 return -EBUSY;
1807
1808 /* calculate new rates and get the topmost changed clock */
1809 top = clk_calc_new_rates(clk, rate);
1810 if (!top)
1811 return -EINVAL;
1812
1813 /* notify that we are about to change rates */
1814 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1815 if (fail_clk) {
1816 pr_debug("%s: failed to set %s rate\n", __func__,
1817 fail_clk->name);
1818 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1819 return -EBUSY;
1820 }
1821
1822 /* change the rates */
1823 clk_change_rate(top);
1824
1825 clk->req_rate = req_rate;
1826
1827 return ret;
1828}
1829
b2476490
MT
1830/**
1831 * clk_set_rate - specify a new rate for clk
1832 * @clk: the clk whose rate is being changed
1833 * @rate: the new rate for clk
1834 *
5654dc94 1835 * In the simplest case clk_set_rate will only adjust the rate of clk.
b2476490 1836 *
5654dc94
MT
1837 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1838 * propagate up to clk's parent; whether or not this happens depends on the
1839 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1840 * after calling .round_rate then upstream parent propagation is ignored. If
1841 * *parent_rate comes back with a new rate for clk's parent then we propagate
24ee1a08 1842 * up to clk's parent and set its rate. Upward propagation will continue
5654dc94
MT
1843 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1844 * .round_rate stops requesting changes to clk's parent_rate.
b2476490 1845 *
5654dc94
MT
1846 * Rate changes are accomplished via tree traversal that also recalculates the
1847 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
b2476490
MT
1848 *
1849 * Returns 0 on success, -EERROR otherwise.
1850 */
1851int clk_set_rate(struct clk *clk, unsigned long rate)
1852{
1c8e6004 1853 int ret;
b2476490 1854
89ac8d7a
MT
1855 if (!clk)
1856 return 0;
1857
b2476490 1858 /* prevent racing with updates to the clock topology */
eab89f69 1859 clk_prepare_lock();
b2476490 1860
1c8e6004 1861 ret = clk_core_set_rate_nolock(clk->core, rate);
b2476490 1862
1c8e6004 1863 clk_prepare_unlock();
0e1c0301 1864
1c8e6004
TV
1865 return ret;
1866}
1867EXPORT_SYMBOL_GPL(clk_set_rate);
b2476490 1868
1c8e6004
TV
1869/**
1870 * clk_set_rate_range - set a rate range for a clock source
1871 * @clk: clock source
1872 * @min: desired minimum clock rate in Hz, inclusive
1873 * @max: desired maximum clock rate in Hz, inclusive
1874 *
1875 * Returns success (0) or negative errno.
1876 */
1877int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
1878{
1879 int ret = 0;
1880
1881 if (!clk)
1882 return 0;
1883
1884 if (min > max) {
1885 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1886 __func__, clk->core->name, clk->dev_id, clk->con_id,
1887 min, max);
1888 return -EINVAL;
b2476490
MT
1889 }
1890
1c8e6004
TV
1891 clk_prepare_lock();
1892
1893 if (min != clk->min_rate || max != clk->max_rate) {
1894 clk->min_rate = min;
1895 clk->max_rate = max;
1896 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
1897 }
b2476490 1898
eab89f69 1899 clk_prepare_unlock();
b2476490
MT
1900
1901 return ret;
1902}
1c8e6004
TV
1903EXPORT_SYMBOL_GPL(clk_set_rate_range);
1904
1905/**
1906 * clk_set_min_rate - set a minimum clock rate for a clock source
1907 * @clk: clock source
1908 * @rate: desired minimum clock rate in Hz, inclusive
1909 *
1910 * Returns success (0) or negative errno.
1911 */
1912int clk_set_min_rate(struct clk *clk, unsigned long rate)
1913{
1914 if (!clk)
1915 return 0;
1916
1917 return clk_set_rate_range(clk, rate, clk->max_rate);
1918}
1919EXPORT_SYMBOL_GPL(clk_set_min_rate);
1920
1921/**
1922 * clk_set_max_rate - set a maximum clock rate for a clock source
1923 * @clk: clock source
1924 * @rate: desired maximum clock rate in Hz, inclusive
1925 *
1926 * Returns success (0) or negative errno.
1927 */
1928int clk_set_max_rate(struct clk *clk, unsigned long rate)
1929{
1930 if (!clk)
1931 return 0;
1932
1933 return clk_set_rate_range(clk, clk->min_rate, rate);
1934}
1935EXPORT_SYMBOL_GPL(clk_set_max_rate);
b2476490
MT
1936
1937/**
1938 * clk_get_parent - return the parent of a clk
1939 * @clk: the clk whose parent gets returned
1940 *
1941 * Simply returns clk->parent. Returns NULL if clk is NULL.
1942 */
1943struct clk *clk_get_parent(struct clk *clk)
1944{
1945 struct clk *parent;
1946
eab89f69 1947 clk_prepare_lock();
b2476490 1948 parent = __clk_get_parent(clk);
eab89f69 1949 clk_prepare_unlock();
b2476490
MT
1950
1951 return parent;
1952}
1953EXPORT_SYMBOL_GPL(clk_get_parent);
1954
1955/*
1956 * .get_parent is mandatory for clocks with multiple possible parents. It is
1957 * optional for single-parent clocks. Always call .get_parent if it is
1958 * available and WARN if it is missing for multi-parent clocks.
1959 *
1960 * For single-parent clocks without .get_parent, first check to see if the
1961 * .parents array exists, and if so use it to avoid an expensive tree
035a61c3 1962 * traversal. If .parents does not exist then walk the tree.
b2476490 1963 */
035a61c3 1964static struct clk_core *__clk_init_parent(struct clk_core *clk)
b2476490 1965{
035a61c3 1966 struct clk_core *ret = NULL;
b2476490
MT
1967 u8 index;
1968
1969 /* handle the trivial cases */
1970
1971 if (!clk->num_parents)
1972 goto out;
1973
1974 if (clk->num_parents == 1) {
1975 if (IS_ERR_OR_NULL(clk->parent))
035a61c3 1976 clk->parent = clk_core_lookup(clk->parent_names[0]);
b2476490
MT
1977 ret = clk->parent;
1978 goto out;
1979 }
1980
1981 if (!clk->ops->get_parent) {
1982 WARN(!clk->ops->get_parent,
1983 "%s: multi-parent clocks must implement .get_parent\n",
1984 __func__);
1985 goto out;
1986 };
1987
1988 /*
1989 * Do our best to cache parent clocks in clk->parents. This prevents
035a61c3
TV
1990 * unnecessary and expensive lookups. We don't set clk->parent here;
1991 * that is done by the calling function.
b2476490
MT
1992 */
1993
1994 index = clk->ops->get_parent(clk->hw);
1995
1996 if (!clk->parents)
1997 clk->parents =
96a7ed90 1998 kcalloc(clk->num_parents, sizeof(struct clk *),
b2476490
MT
1999 GFP_KERNEL);
2000
035a61c3 2001 ret = clk_core_get_parent_by_index(clk, index);
b2476490
MT
2002
2003out:
2004 return ret;
2005}
2006
035a61c3
TV
2007static void clk_core_reparent(struct clk_core *clk,
2008 struct clk_core *new_parent)
b33d212f
UH
2009{
2010 clk_reparent(clk, new_parent);
5279fc40 2011 __clk_recalc_accuracies(clk);
b2476490
MT
2012 __clk_recalc_rates(clk, POST_RATE_CHANGE);
2013}
2014
b2476490 2015/**
4e88f3de
TR
2016 * clk_has_parent - check if a clock is a possible parent for another
2017 * @clk: clock source
2018 * @parent: parent clock source
b2476490 2019 *
4e88f3de
TR
2020 * This function can be used in drivers that need to check that a clock can be
2021 * the parent of another without actually changing the parent.
f8aa0bd5 2022 *
4e88f3de 2023 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 2024 */
4e88f3de
TR
2025bool clk_has_parent(struct clk *clk, struct clk *parent)
2026{
035a61c3 2027 struct clk_core *core, *parent_core;
4e88f3de
TR
2028 unsigned int i;
2029
2030 /* NULL clocks should be nops, so return success if either is NULL. */
2031 if (!clk || !parent)
2032 return true;
2033
035a61c3
TV
2034 core = clk->core;
2035 parent_core = parent->core;
2036
4e88f3de 2037 /* Optimize for the case where the parent is already the parent. */
035a61c3 2038 if (core->parent == parent_core)
4e88f3de
TR
2039 return true;
2040
035a61c3
TV
2041 for (i = 0; i < core->num_parents; i++)
2042 if (strcmp(core->parent_names[i], parent_core->name) == 0)
4e88f3de
TR
2043 return true;
2044
2045 return false;
2046}
2047EXPORT_SYMBOL_GPL(clk_has_parent);
2048
035a61c3 2049static int clk_core_set_parent(struct clk_core *clk, struct clk_core *parent)
b2476490
MT
2050{
2051 int ret = 0;
f1c8b2ed 2052 int p_index = 0;
031dcc9b 2053 unsigned long p_rate = 0;
b2476490 2054
89ac8d7a
MT
2055 if (!clk)
2056 return 0;
2057
031dcc9b
UH
2058 /* verify ops for for multi-parent clks */
2059 if ((clk->num_parents > 1) && (!clk->ops->set_parent))
b2476490
MT
2060 return -ENOSYS;
2061
2062 /* prevent racing with updates to the clock topology */
eab89f69 2063 clk_prepare_lock();
b2476490
MT
2064
2065 if (clk->parent == parent)
2066 goto out;
2067
031dcc9b
UH
2068 /* check that we are allowed to re-parent if the clock is in use */
2069 if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
2070 ret = -EBUSY;
2071 goto out;
2072 }
2073
2074 /* try finding the new parent index */
2075 if (parent) {
2076 p_index = clk_fetch_parent_index(clk, parent);
2077 p_rate = parent->rate;
f1c8b2ed 2078 if (p_index < 0) {
031dcc9b
UH
2079 pr_debug("%s: clk %s can not be parent of clk %s\n",
2080 __func__, parent->name, clk->name);
f1c8b2ed 2081 ret = p_index;
031dcc9b
UH
2082 goto out;
2083 }
2084 }
2085
b2476490 2086 /* propagate PRE_RATE_CHANGE notifications */
f3aab5d6 2087 ret = __clk_speculate_rates(clk, p_rate);
b2476490
MT
2088
2089 /* abort if a driver objects */
fb72a059 2090 if (ret & NOTIFY_STOP_MASK)
b2476490
MT
2091 goto out;
2092
031dcc9b
UH
2093 /* do the re-parent */
2094 ret = __clk_set_parent(clk, parent, p_index);
b2476490 2095
5279fc40
BB
2096 /* propagate rate an accuracy recalculation accordingly */
2097 if (ret) {
b2476490 2098 __clk_recalc_rates(clk, ABORT_RATE_CHANGE);
5279fc40 2099 } else {
a68de8e4 2100 __clk_recalc_rates(clk, POST_RATE_CHANGE);
5279fc40
BB
2101 __clk_recalc_accuracies(clk);
2102 }
b2476490
MT
2103
2104out:
eab89f69 2105 clk_prepare_unlock();
b2476490
MT
2106
2107 return ret;
2108}
035a61c3
TV
2109
2110/**
2111 * clk_set_parent - switch the parent of a mux clk
2112 * @clk: the mux clk whose input we are switching
2113 * @parent: the new input to clk
2114 *
2115 * Re-parent clk to use parent as its new input source. If clk is in
2116 * prepared state, the clk will get enabled for the duration of this call. If
2117 * that's not acceptable for a specific clk (Eg: the consumer can't handle
2118 * that, the reparenting is glitchy in hardware, etc), use the
2119 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
2120 *
2121 * After successfully changing clk's parent clk_set_parent will update the
2122 * clk topology, sysfs topology and propagate rate recalculation via
2123 * __clk_recalc_rates.
2124 *
2125 * Returns 0 on success, -EERROR otherwise.
2126 */
2127int clk_set_parent(struct clk *clk, struct clk *parent)
2128{
2129 if (!clk)
2130 return 0;
2131
2132 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
2133}
b2476490
MT
2134EXPORT_SYMBOL_GPL(clk_set_parent);
2135
e59c5371
MT
2136/**
2137 * clk_set_phase - adjust the phase shift of a clock signal
2138 * @clk: clock signal source
2139 * @degrees: number of degrees the signal is shifted
2140 *
2141 * Shifts the phase of a clock signal by the specified
2142 * degrees. Returns 0 on success, -EERROR otherwise.
2143 *
2144 * This function makes no distinction about the input or reference
2145 * signal that we adjust the clock signal phase against. For example
2146 * phase locked-loop clock signal generators we may shift phase with
2147 * respect to feedback clock signal input, but for other cases the
2148 * clock phase may be shifted with respect to some other, unspecified
2149 * signal.
2150 *
2151 * Additionally the concept of phase shift does not propagate through
2152 * the clock tree hierarchy, which sets it apart from clock rates and
2153 * clock accuracy. A parent clock phase attribute does not have an
2154 * impact on the phase attribute of a child clock.
2155 */
2156int clk_set_phase(struct clk *clk, int degrees)
2157{
08b95756 2158 int ret = -EINVAL;
e59c5371
MT
2159
2160 if (!clk)
08b95756 2161 return 0;
e59c5371
MT
2162
2163 /* sanity check degrees */
2164 degrees %= 360;
2165 if (degrees < 0)
2166 degrees += 360;
2167
2168 clk_prepare_lock();
2169
dfc202ea
SB
2170 trace_clk_set_phase(clk->core, degrees);
2171
08b95756
SB
2172 if (clk->core->ops->set_phase)
2173 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
e59c5371 2174
dfc202ea
SB
2175 trace_clk_set_phase_complete(clk->core, degrees);
2176
e59c5371 2177 if (!ret)
035a61c3 2178 clk->core->phase = degrees;
e59c5371 2179
e59c5371
MT
2180 clk_prepare_unlock();
2181
e59c5371
MT
2182 return ret;
2183}
9767b04f 2184EXPORT_SYMBOL_GPL(clk_set_phase);
e59c5371 2185
035a61c3 2186static int clk_core_get_phase(struct clk_core *clk)
e59c5371
MT
2187{
2188 int ret = 0;
2189
2190 if (!clk)
2191 goto out;
2192
2193 clk_prepare_lock();
2194 ret = clk->phase;
2195 clk_prepare_unlock();
2196
2197out:
2198 return ret;
2199}
9767b04f 2200EXPORT_SYMBOL_GPL(clk_get_phase);
e59c5371 2201
035a61c3
TV
2202/**
2203 * clk_get_phase - return the phase shift of a clock signal
2204 * @clk: clock signal source
2205 *
2206 * Returns the phase shift of a clock node in degrees, otherwise returns
2207 * -EERROR.
2208 */
2209int clk_get_phase(struct clk *clk)
2210{
2211 if (!clk)
2212 return 0;
2213
2214 return clk_core_get_phase(clk->core);
2215}
e59c5371 2216
b2476490
MT
2217/**
2218 * __clk_init - initialize the data structures in a struct clk
2219 * @dev: device initializing this clk, placeholder for now
2220 * @clk: clk being initialized
2221 *
035a61c3 2222 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2223 * parent and rate and sets them both.
b2476490 2224 */
b09d6d99 2225static int __clk_init(struct device *dev, struct clk *clk_user)
b2476490 2226{
d1302a36 2227 int i, ret = 0;
035a61c3 2228 struct clk_core *orphan;
b67bfe0d 2229 struct hlist_node *tmp2;
035a61c3 2230 struct clk_core *clk;
1c8e6004 2231 unsigned long rate;
b2476490 2232
035a61c3 2233 if (!clk_user)
d1302a36 2234 return -EINVAL;
b2476490 2235
035a61c3
TV
2236 clk = clk_user->core;
2237
eab89f69 2238 clk_prepare_lock();
b2476490
MT
2239
2240 /* check to see if a clock with this name is already registered */
035a61c3 2241 if (clk_core_lookup(clk->name)) {
d1302a36
MT
2242 pr_debug("%s: clk %s already initialized\n",
2243 __func__, clk->name);
2244 ret = -EEXIST;
b2476490 2245 goto out;
d1302a36 2246 }
b2476490 2247
d4d7e3dd
MT
2248 /* check that clk_ops are sane. See Documentation/clk.txt */
2249 if (clk->ops->set_rate &&
71472c0c
JH
2250 !((clk->ops->round_rate || clk->ops->determine_rate) &&
2251 clk->ops->recalc_rate)) {
2252 pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
d4d7e3dd 2253 __func__, clk->name);
d1302a36 2254 ret = -EINVAL;
d4d7e3dd
MT
2255 goto out;
2256 }
2257
2258 if (clk->ops->set_parent && !clk->ops->get_parent) {
2259 pr_warning("%s: %s must implement .get_parent & .set_parent\n",
2260 __func__, clk->name);
d1302a36 2261 ret = -EINVAL;
d4d7e3dd
MT
2262 goto out;
2263 }
2264
3fa2252b
SB
2265 if (clk->ops->set_rate_and_parent &&
2266 !(clk->ops->set_parent && clk->ops->set_rate)) {
2267 pr_warn("%s: %s must implement .set_parent & .set_rate\n",
2268 __func__, clk->name);
2269 ret = -EINVAL;
2270 goto out;
2271 }
2272
b2476490
MT
2273 /* throw a WARN if any entries in parent_names are NULL */
2274 for (i = 0; i < clk->num_parents; i++)
2275 WARN(!clk->parent_names[i],
2276 "%s: invalid NULL in %s's .parent_names\n",
2277 __func__, clk->name);
2278
2279 /*
2280 * Allocate an array of struct clk *'s to avoid unnecessary string
2281 * look-ups of clk's possible parents. This can fail for clocks passed
2282 * in to clk_init during early boot; thus any access to clk->parents[]
2283 * must always check for a NULL pointer and try to populate it if
2284 * necessary.
2285 *
2286 * If clk->parents is not NULL we skip this entire block. This allows
2287 * for clock drivers to statically initialize clk->parents.
2288 */
9ca1c5a4 2289 if (clk->num_parents > 1 && !clk->parents) {
96a7ed90
TF
2290 clk->parents = kcalloc(clk->num_parents, sizeof(struct clk *),
2291 GFP_KERNEL);
b2476490 2292 /*
035a61c3 2293 * clk_core_lookup returns NULL for parents that have not been
b2476490
MT
2294 * clk_init'd; thus any access to clk->parents[] must check
2295 * for a NULL pointer. We can always perform lazy lookups for
2296 * missing parents later on.
2297 */
2298 if (clk->parents)
2299 for (i = 0; i < clk->num_parents; i++)
2300 clk->parents[i] =
035a61c3 2301 clk_core_lookup(clk->parent_names[i]);
b2476490
MT
2302 }
2303
2304 clk->parent = __clk_init_parent(clk);
2305
2306 /*
2307 * Populate clk->parent if parent has already been __clk_init'd. If
2308 * parent has not yet been __clk_init'd then place clk in the orphan
2309 * list. If clk has set the CLK_IS_ROOT flag then place it in the root
2310 * clk list.
2311 *
2312 * Every time a new clk is clk_init'd then we walk the list of orphan
2313 * clocks and re-parent any that are children of the clock currently
2314 * being clk_init'd.
2315 */
2316 if (clk->parent)
2317 hlist_add_head(&clk->child_node,
2318 &clk->parent->children);
2319 else if (clk->flags & CLK_IS_ROOT)
2320 hlist_add_head(&clk->child_node, &clk_root_list);
2321 else
2322 hlist_add_head(&clk->child_node, &clk_orphan_list);
2323
5279fc40
BB
2324 /*
2325 * Set clk's accuracy. The preferred method is to use
2326 * .recalc_accuracy. For simple clocks and lazy developers the default
2327 * fallback is to use the parent's accuracy. If a clock doesn't have a
2328 * parent (or is orphaned) then accuracy is set to zero (perfect
2329 * clock).
2330 */
2331 if (clk->ops->recalc_accuracy)
2332 clk->accuracy = clk->ops->recalc_accuracy(clk->hw,
2333 __clk_get_accuracy(clk->parent));
2334 else if (clk->parent)
2335 clk->accuracy = clk->parent->accuracy;
2336 else
2337 clk->accuracy = 0;
2338
9824cf73
MR
2339 /*
2340 * Set clk's phase.
2341 * Since a phase is by definition relative to its parent, just
2342 * query the current clock phase, or just assume it's in phase.
2343 */
2344 if (clk->ops->get_phase)
2345 clk->phase = clk->ops->get_phase(clk->hw);
2346 else
2347 clk->phase = 0;
2348
b2476490
MT
2349 /*
2350 * Set clk's rate. The preferred method is to use .recalc_rate. For
2351 * simple clocks and lazy developers the default fallback is to use the
2352 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2353 * then rate is set to zero.
2354 */
2355 if (clk->ops->recalc_rate)
1c8e6004 2356 rate = clk->ops->recalc_rate(clk->hw,
035a61c3 2357 clk_core_get_rate_nolock(clk->parent));
b2476490 2358 else if (clk->parent)
1c8e6004 2359 rate = clk->parent->rate;
b2476490 2360 else
1c8e6004
TV
2361 rate = 0;
2362 clk->rate = clk->req_rate = rate;
b2476490
MT
2363
2364 /*
2365 * walk the list of orphan clocks and reparent any that are children of
2366 * this clock
2367 */
b67bfe0d 2368 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
12d29886 2369 if (orphan->num_parents && orphan->ops->get_parent) {
1f61e5f1
MF
2370 i = orphan->ops->get_parent(orphan->hw);
2371 if (!strcmp(clk->name, orphan->parent_names[i]))
035a61c3 2372 clk_core_reparent(orphan, clk);
1f61e5f1
MF
2373 continue;
2374 }
2375
b2476490
MT
2376 for (i = 0; i < orphan->num_parents; i++)
2377 if (!strcmp(clk->name, orphan->parent_names[i])) {
035a61c3 2378 clk_core_reparent(orphan, clk);
b2476490
MT
2379 break;
2380 }
1f61e5f1 2381 }
b2476490
MT
2382
2383 /*
2384 * optional platform-specific magic
2385 *
2386 * The .init callback is not used by any of the basic clock types, but
2387 * exists for weird hardware that must perform initialization magic.
2388 * Please consider other ways of solving initialization problems before
24ee1a08 2389 * using this callback, as its use is discouraged.
b2476490
MT
2390 */
2391 if (clk->ops->init)
2392 clk->ops->init(clk->hw);
2393
fcb0ee6a 2394 kref_init(&clk->ref);
b2476490 2395out:
eab89f69 2396 clk_prepare_unlock();
b2476490 2397
89f7e9de
SB
2398 if (!ret)
2399 clk_debug_register(clk);
2400
d1302a36 2401 return ret;
b2476490
MT
2402}
2403
035a61c3
TV
2404struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2405 const char *con_id)
0197b3ea 2406{
0197b3ea
SK
2407 struct clk *clk;
2408
035a61c3
TV
2409 /* This is to allow this function to be chained to others */
2410 if (!hw || IS_ERR(hw))
2411 return (struct clk *) hw;
0197b3ea 2412
035a61c3
TV
2413 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2414 if (!clk)
2415 return ERR_PTR(-ENOMEM);
2416
2417 clk->core = hw->core;
2418 clk->dev_id = dev_id;
2419 clk->con_id = con_id;
1c8e6004
TV
2420 clk->max_rate = ULONG_MAX;
2421
2422 clk_prepare_lock();
2423 hlist_add_head(&clk->child_node, &hw->core->clks);
2424 clk_prepare_unlock();
0197b3ea
SK
2425
2426 return clk;
2427}
035a61c3 2428
73e0e496 2429void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2430{
2431 clk_prepare_lock();
2432 hlist_del(&clk->child_node);
2433 clk_prepare_unlock();
2434
2435 kfree(clk);
2436}
0197b3ea 2437
293ba3b4
SB
2438/**
2439 * clk_register - allocate a new clock, register it and return an opaque cookie
2440 * @dev: device that is registering this clock
2441 * @hw: link to hardware-specific clock data
2442 *
2443 * clk_register is the primary interface for populating the clock tree with new
2444 * clock nodes. It returns a pointer to the newly allocated struct clk which
2445 * cannot be dereferenced by driver code but may be used in conjuction with the
2446 * rest of the clock API. In the event of an error clk_register will return an
2447 * error code; drivers must test for an error code after calling clk_register.
2448 */
2449struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2450{
d1302a36 2451 int i, ret;
035a61c3 2452 struct clk_core *clk;
293ba3b4
SB
2453
2454 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2455 if (!clk) {
2456 pr_err("%s: could not allocate clk\n", __func__);
2457 ret = -ENOMEM;
2458 goto fail_out;
2459 }
b2476490 2460
612936f2 2461 clk->name = kstrdup_const(hw->init->name, GFP_KERNEL);
0197b3ea
SK
2462 if (!clk->name) {
2463 pr_err("%s: could not allocate clk->name\n", __func__);
2464 ret = -ENOMEM;
2465 goto fail_name;
2466 }
2467 clk->ops = hw->init->ops;
ac2df527
SN
2468 if (dev && dev->driver)
2469 clk->owner = dev->driver->owner;
b2476490 2470 clk->hw = hw;
0197b3ea
SK
2471 clk->flags = hw->init->flags;
2472 clk->num_parents = hw->init->num_parents;
035a61c3 2473 hw->core = clk;
b2476490 2474
d1302a36 2475 /* allocate local copy in case parent_names is __initdata */
96a7ed90
TF
2476 clk->parent_names = kcalloc(clk->num_parents, sizeof(char *),
2477 GFP_KERNEL);
d1302a36
MT
2478
2479 if (!clk->parent_names) {
2480 pr_err("%s: could not allocate clk->parent_names\n", __func__);
2481 ret = -ENOMEM;
2482 goto fail_parent_names;
2483 }
2484
2485
2486 /* copy each string name in case parent_names is __initdata */
0197b3ea 2487 for (i = 0; i < clk->num_parents; i++) {
612936f2 2488 clk->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2489 GFP_KERNEL);
d1302a36
MT
2490 if (!clk->parent_names[i]) {
2491 pr_err("%s: could not copy parent_names\n", __func__);
2492 ret = -ENOMEM;
2493 goto fail_parent_names_copy;
2494 }
2495 }
2496
1c8e6004
TV
2497 INIT_HLIST_HEAD(&clk->clks);
2498
035a61c3
TV
2499 hw->clk = __clk_create_clk(hw, NULL, NULL);
2500 if (IS_ERR(hw->clk)) {
2501 pr_err("%s: could not allocate per-user clk\n", __func__);
2502 ret = PTR_ERR(hw->clk);
2503 goto fail_parent_names_copy;
2504 }
2505
2506 ret = __clk_init(dev, hw->clk);
d1302a36 2507 if (!ret)
035a61c3 2508 return hw->clk;
b2476490 2509
1c8e6004 2510 __clk_free_clk(hw->clk);
035a61c3 2511 hw->clk = NULL;
b2476490 2512
d1302a36
MT
2513fail_parent_names_copy:
2514 while (--i >= 0)
612936f2 2515 kfree_const(clk->parent_names[i]);
d1302a36
MT
2516 kfree(clk->parent_names);
2517fail_parent_names:
612936f2 2518 kfree_const(clk->name);
0197b3ea 2519fail_name:
d1302a36
MT
2520 kfree(clk);
2521fail_out:
2522 return ERR_PTR(ret);
b2476490
MT
2523}
2524EXPORT_SYMBOL_GPL(clk_register);
2525
fcb0ee6a
SN
2526/*
2527 * Free memory allocated for a clock.
2528 * Caller must hold prepare_lock.
2529 */
2530static void __clk_release(struct kref *ref)
2531{
035a61c3 2532 struct clk_core *clk = container_of(ref, struct clk_core, ref);
fcb0ee6a
SN
2533 int i = clk->num_parents;
2534
496eadf8
KK
2535 lockdep_assert_held(&prepare_lock);
2536
fcb0ee6a
SN
2537 kfree(clk->parents);
2538 while (--i >= 0)
612936f2 2539 kfree_const(clk->parent_names[i]);
fcb0ee6a
SN
2540
2541 kfree(clk->parent_names);
612936f2 2542 kfree_const(clk->name);
fcb0ee6a
SN
2543 kfree(clk);
2544}
2545
2546/*
2547 * Empty clk_ops for unregistered clocks. These are used temporarily
2548 * after clk_unregister() was called on a clock and until last clock
2549 * consumer calls clk_put() and the struct clk object is freed.
2550 */
2551static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2552{
2553 return -ENXIO;
2554}
2555
2556static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2557{
2558 WARN_ON_ONCE(1);
2559}
2560
2561static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2562 unsigned long parent_rate)
2563{
2564 return -ENXIO;
2565}
2566
2567static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2568{
2569 return -ENXIO;
2570}
2571
2572static const struct clk_ops clk_nodrv_ops = {
2573 .enable = clk_nodrv_prepare_enable,
2574 .disable = clk_nodrv_disable_unprepare,
2575 .prepare = clk_nodrv_prepare_enable,
2576 .unprepare = clk_nodrv_disable_unprepare,
2577 .set_rate = clk_nodrv_set_rate,
2578 .set_parent = clk_nodrv_set_parent,
2579};
2580
1df5c939
MB
2581/**
2582 * clk_unregister - unregister a currently registered clock
2583 * @clk: clock to unregister
1df5c939 2584 */
fcb0ee6a
SN
2585void clk_unregister(struct clk *clk)
2586{
2587 unsigned long flags;
2588
6314b679
SB
2589 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2590 return;
2591
035a61c3 2592 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2593
2594 clk_prepare_lock();
2595
035a61c3
TV
2596 if (clk->core->ops == &clk_nodrv_ops) {
2597 pr_err("%s: unregistered clock: %s\n", __func__,
2598 clk->core->name);
6314b679 2599 return;
fcb0ee6a
SN
2600 }
2601 /*
2602 * Assign empty clock ops for consumers that might still hold
2603 * a reference to this clock.
2604 */
2605 flags = clk_enable_lock();
035a61c3 2606 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2607 clk_enable_unlock(flags);
2608
035a61c3
TV
2609 if (!hlist_empty(&clk->core->children)) {
2610 struct clk_core *child;
874f224c 2611 struct hlist_node *t;
fcb0ee6a
SN
2612
2613 /* Reparent all children to the orphan list. */
035a61c3
TV
2614 hlist_for_each_entry_safe(child, t, &clk->core->children,
2615 child_node)
2616 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2617 }
2618
035a61c3 2619 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2620
035a61c3 2621 if (clk->core->prepare_count)
fcb0ee6a 2622 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2623 __func__, clk->core->name);
2624 kref_put(&clk->core->ref, __clk_release);
6314b679 2625
fcb0ee6a
SN
2626 clk_prepare_unlock();
2627}
1df5c939
MB
2628EXPORT_SYMBOL_GPL(clk_unregister);
2629
46c8773a
SB
2630static void devm_clk_release(struct device *dev, void *res)
2631{
293ba3b4 2632 clk_unregister(*(struct clk **)res);
46c8773a
SB
2633}
2634
2635/**
2636 * devm_clk_register - resource managed clk_register()
2637 * @dev: device that is registering this clock
2638 * @hw: link to hardware-specific clock data
2639 *
2640 * Managed clk_register(). Clocks returned from this function are
2641 * automatically clk_unregister()ed on driver detach. See clk_register() for
2642 * more information.
2643 */
2644struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2645{
2646 struct clk *clk;
293ba3b4 2647 struct clk **clkp;
46c8773a 2648
293ba3b4
SB
2649 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2650 if (!clkp)
46c8773a
SB
2651 return ERR_PTR(-ENOMEM);
2652
293ba3b4
SB
2653 clk = clk_register(dev, hw);
2654 if (!IS_ERR(clk)) {
2655 *clkp = clk;
2656 devres_add(dev, clkp);
46c8773a 2657 } else {
293ba3b4 2658 devres_free(clkp);
46c8773a
SB
2659 }
2660
2661 return clk;
2662}
2663EXPORT_SYMBOL_GPL(devm_clk_register);
2664
2665static int devm_clk_match(struct device *dev, void *res, void *data)
2666{
2667 struct clk *c = res;
2668 if (WARN_ON(!c))
2669 return 0;
2670 return c == data;
2671}
2672
2673/**
2674 * devm_clk_unregister - resource managed clk_unregister()
2675 * @clk: clock to unregister
2676 *
2677 * Deallocate a clock allocated with devm_clk_register(). Normally
2678 * this function will not need to be called and the resource management
2679 * code will ensure that the resource is freed.
2680 */
2681void devm_clk_unregister(struct device *dev, struct clk *clk)
2682{
2683 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2684}
2685EXPORT_SYMBOL_GPL(devm_clk_unregister);
2686
ac2df527
SN
2687/*
2688 * clkdev helpers
2689 */
2690int __clk_get(struct clk *clk)
2691{
035a61c3
TV
2692 struct clk_core *core = !clk ? NULL : clk->core;
2693
2694 if (core) {
2695 if (!try_module_get(core->owner))
00efcb1c 2696 return 0;
ac2df527 2697
035a61c3 2698 kref_get(&core->ref);
00efcb1c 2699 }
ac2df527
SN
2700 return 1;
2701}
2702
2703void __clk_put(struct clk *clk)
2704{
10cdfe54
TV
2705 struct module *owner;
2706
00efcb1c 2707 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2708 return;
2709
fcb0ee6a 2710 clk_prepare_lock();
1c8e6004
TV
2711
2712 hlist_del(&clk->child_node);
ec02ace8
TV
2713 if (clk->min_rate > clk->core->req_rate ||
2714 clk->max_rate < clk->core->req_rate)
2715 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2716
1c8e6004
TV
2717 owner = clk->core->owner;
2718 kref_put(&clk->core->ref, __clk_release);
2719
fcb0ee6a
SN
2720 clk_prepare_unlock();
2721
10cdfe54 2722 module_put(owner);
035a61c3 2723
035a61c3 2724 kfree(clk);
ac2df527
SN
2725}
2726
b2476490
MT
2727/*** clk rate change notifiers ***/
2728
2729/**
2730 * clk_notifier_register - add a clk rate change notifier
2731 * @clk: struct clk * to watch
2732 * @nb: struct notifier_block * with callback info
2733 *
2734 * Request notification when clk's rate changes. This uses an SRCU
2735 * notifier because we want it to block and notifier unregistrations are
2736 * uncommon. The callbacks associated with the notifier must not
2737 * re-enter into the clk framework by calling any top-level clk APIs;
2738 * this will cause a nested prepare_lock mutex.
2739 *
5324fda7
SB
2740 * In all notification cases cases (pre, post and abort rate change) the
2741 * original clock rate is passed to the callback via struct
2742 * clk_notifier_data.old_rate and the new frequency is passed via struct
b2476490
MT
2743 * clk_notifier_data.new_rate.
2744 *
b2476490
MT
2745 * clk_notifier_register() must be called from non-atomic context.
2746 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2747 * allocation failure; otherwise, passes along the return value of
2748 * srcu_notifier_chain_register().
2749 */
2750int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2751{
2752 struct clk_notifier *cn;
2753 int ret = -ENOMEM;
2754
2755 if (!clk || !nb)
2756 return -EINVAL;
2757
eab89f69 2758 clk_prepare_lock();
b2476490
MT
2759
2760 /* search the list of notifiers for this clk */
2761 list_for_each_entry(cn, &clk_notifier_list, node)
2762 if (cn->clk == clk)
2763 break;
2764
2765 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2766 if (cn->clk != clk) {
2767 cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2768 if (!cn)
2769 goto out;
2770
2771 cn->clk = clk;
2772 srcu_init_notifier_head(&cn->notifier_head);
2773
2774 list_add(&cn->node, &clk_notifier_list);
2775 }
2776
2777 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2778
035a61c3 2779 clk->core->notifier_count++;
b2476490
MT
2780
2781out:
eab89f69 2782 clk_prepare_unlock();
b2476490
MT
2783
2784 return ret;
2785}
2786EXPORT_SYMBOL_GPL(clk_notifier_register);
2787
2788/**
2789 * clk_notifier_unregister - remove a clk rate change notifier
2790 * @clk: struct clk *
2791 * @nb: struct notifier_block * with callback info
2792 *
2793 * Request no further notification for changes to 'clk' and frees memory
2794 * allocated in clk_notifier_register.
2795 *
2796 * Returns -EINVAL if called with null arguments; otherwise, passes
2797 * along the return value of srcu_notifier_chain_unregister().
2798 */
2799int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2800{
2801 struct clk_notifier *cn = NULL;
2802 int ret = -EINVAL;
2803
2804 if (!clk || !nb)
2805 return -EINVAL;
2806
eab89f69 2807 clk_prepare_lock();
b2476490
MT
2808
2809 list_for_each_entry(cn, &clk_notifier_list, node)
2810 if (cn->clk == clk)
2811 break;
2812
2813 if (cn->clk == clk) {
2814 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2815
035a61c3 2816 clk->core->notifier_count--;
b2476490
MT
2817
2818 /* XXX the notifier code should handle this better */
2819 if (!cn->notifier_head.head) {
2820 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 2821 list_del(&cn->node);
b2476490
MT
2822 kfree(cn);
2823 }
2824
2825 } else {
2826 ret = -ENOENT;
2827 }
2828
eab89f69 2829 clk_prepare_unlock();
b2476490
MT
2830
2831 return ret;
2832}
2833EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
2834
2835#ifdef CONFIG_OF
2836/**
2837 * struct of_clk_provider - Clock provider registration structure
2838 * @link: Entry in global list of clock providers
2839 * @node: Pointer to device tree node of clock provider
2840 * @get: Get clock callback. Returns NULL or a struct clk for the
2841 * given clock specifier
2842 * @data: context pointer to be passed into @get callback
2843 */
2844struct of_clk_provider {
2845 struct list_head link;
2846
2847 struct device_node *node;
2848 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
2849 void *data;
2850};
2851
f2f6c255
PG
2852static const struct of_device_id __clk_of_table_sentinel
2853 __used __section(__clk_of_table_end);
2854
766e6a4e 2855static LIST_HEAD(of_clk_providers);
d6782c26
SN
2856static DEFINE_MUTEX(of_clk_mutex);
2857
2858/* of_clk_provider list locking helpers */
2859void of_clk_lock(void)
2860{
2861 mutex_lock(&of_clk_mutex);
2862}
2863
2864void of_clk_unlock(void)
2865{
2866 mutex_unlock(&of_clk_mutex);
2867}
766e6a4e
GL
2868
2869struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2870 void *data)
2871{
2872 return data;
2873}
2874EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
2875
494bfec9
SG
2876struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
2877{
2878 struct clk_onecell_data *clk_data = data;
2879 unsigned int idx = clkspec->args[0];
2880
2881 if (idx >= clk_data->clk_num) {
2882 pr_err("%s: invalid clock index %d\n", __func__, idx);
2883 return ERR_PTR(-EINVAL);
2884 }
2885
2886 return clk_data->clks[idx];
2887}
2888EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
2889
766e6a4e
GL
2890/**
2891 * of_clk_add_provider() - Register a clock provider for a node
2892 * @np: Device node pointer associated with clock provider
2893 * @clk_src_get: callback for decoding clock
2894 * @data: context pointer for @clk_src_get callback.
2895 */
2896int of_clk_add_provider(struct device_node *np,
2897 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
2898 void *data),
2899 void *data)
2900{
2901 struct of_clk_provider *cp;
86be408b 2902 int ret;
766e6a4e
GL
2903
2904 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
2905 if (!cp)
2906 return -ENOMEM;
2907
2908 cp->node = of_node_get(np);
2909 cp->data = data;
2910 cp->get = clk_src_get;
2911
d6782c26 2912 mutex_lock(&of_clk_mutex);
766e6a4e 2913 list_add(&cp->link, &of_clk_providers);
d6782c26 2914 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2915 pr_debug("Added clock from %s\n", np->full_name);
2916
86be408b
SN
2917 ret = of_clk_set_defaults(np, true);
2918 if (ret < 0)
2919 of_clk_del_provider(np);
2920
2921 return ret;
766e6a4e
GL
2922}
2923EXPORT_SYMBOL_GPL(of_clk_add_provider);
2924
2925/**
2926 * of_clk_del_provider() - Remove a previously registered clock provider
2927 * @np: Device node pointer associated with clock provider
2928 */
2929void of_clk_del_provider(struct device_node *np)
2930{
2931 struct of_clk_provider *cp;
2932
d6782c26 2933 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2934 list_for_each_entry(cp, &of_clk_providers, link) {
2935 if (cp->node == np) {
2936 list_del(&cp->link);
2937 of_node_put(cp->node);
2938 kfree(cp);
2939 break;
2940 }
2941 }
d6782c26 2942 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2943}
2944EXPORT_SYMBOL_GPL(of_clk_del_provider);
2945
73e0e496
SB
2946struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
2947 const char *dev_id, const char *con_id)
766e6a4e
GL
2948{
2949 struct of_clk_provider *provider;
a34cd466 2950 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
766e6a4e
GL
2951
2952 /* Check if we have such a provider in our array */
766e6a4e
GL
2953 list_for_each_entry(provider, &of_clk_providers, link) {
2954 if (provider->node == clkspec->np)
2955 clk = provider->get(clkspec, provider->data);
73e0e496
SB
2956 if (!IS_ERR(clk)) {
2957 clk = __clk_create_clk(__clk_get_hw(clk), dev_id,
2958 con_id);
2959
2960 if (!IS_ERR(clk) && !__clk_get(clk)) {
2961 __clk_free_clk(clk);
2962 clk = ERR_PTR(-ENOENT);
2963 }
2964
766e6a4e 2965 break;
73e0e496 2966 }
766e6a4e 2967 }
d6782c26
SN
2968
2969 return clk;
2970}
2971
2972struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
2973{
2974 struct clk *clk;
2975
2976 mutex_lock(&of_clk_mutex);
73e0e496 2977 clk = __of_clk_get_from_provider(clkspec, NULL, __func__);
d6782c26 2978 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2979
2980 return clk;
2981}
2982
f6102742
MT
2983int of_clk_get_parent_count(struct device_node *np)
2984{
2985 return of_count_phandle_with_args(np, "clocks", "#clock-cells");
2986}
2987EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
2988
766e6a4e
GL
2989const char *of_clk_get_parent_name(struct device_node *np, int index)
2990{
2991 struct of_phandle_args clkspec;
7a0fc1a3 2992 struct property *prop;
766e6a4e 2993 const char *clk_name;
7a0fc1a3
BD
2994 const __be32 *vp;
2995 u32 pv;
766e6a4e 2996 int rc;
7a0fc1a3 2997 int count;
766e6a4e
GL
2998
2999 if (index < 0)
3000 return NULL;
3001
3002 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3003 &clkspec);
3004 if (rc)
3005 return NULL;
3006
7a0fc1a3
BD
3007 index = clkspec.args_count ? clkspec.args[0] : 0;
3008 count = 0;
3009
3010 /* if there is an indices property, use it to transfer the index
3011 * specified into an array offset for the clock-output-names property.
3012 */
3013 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3014 if (index == pv) {
3015 index = count;
3016 break;
3017 }
3018 count++;
3019 }
3020
766e6a4e 3021 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3022 index,
766e6a4e
GL
3023 &clk_name) < 0)
3024 clk_name = clkspec.np->name;
3025
3026 of_node_put(clkspec.np);
3027 return clk_name;
3028}
3029EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3030
1771b10d
GC
3031struct clock_provider {
3032 of_clk_init_cb_t clk_init_cb;
3033 struct device_node *np;
3034 struct list_head node;
3035};
3036
3037static LIST_HEAD(clk_provider_list);
3038
3039/*
3040 * This function looks for a parent clock. If there is one, then it
3041 * checks that the provider for this parent clock was initialized, in
3042 * this case the parent clock will be ready.
3043 */
3044static int parent_ready(struct device_node *np)
3045{
3046 int i = 0;
3047
3048 while (true) {
3049 struct clk *clk = of_clk_get(np, i);
3050
3051 /* this parent is ready we can check the next one */
3052 if (!IS_ERR(clk)) {
3053 clk_put(clk);
3054 i++;
3055 continue;
3056 }
3057
3058 /* at least one parent is not ready, we exit now */
3059 if (PTR_ERR(clk) == -EPROBE_DEFER)
3060 return 0;
3061
3062 /*
3063 * Here we make assumption that the device tree is
3064 * written correctly. So an error means that there is
3065 * no more parent. As we didn't exit yet, then the
3066 * previous parent are ready. If there is no clock
3067 * parent, no need to wait for them, then we can
3068 * consider their absence as being ready
3069 */
3070 return 1;
3071 }
3072}
3073
766e6a4e
GL
3074/**
3075 * of_clk_init() - Scan and init clock providers from the DT
3076 * @matches: array of compatible values and init functions for providers.
3077 *
1771b10d 3078 * This function scans the device tree for matching clock providers
e5ca8fb4 3079 * and calls their initialization functions. It also does it by trying
1771b10d 3080 * to follow the dependencies.
766e6a4e
GL
3081 */
3082void __init of_clk_init(const struct of_device_id *matches)
3083{
7f7ed584 3084 const struct of_device_id *match;
766e6a4e 3085 struct device_node *np;
1771b10d
GC
3086 struct clock_provider *clk_provider, *next;
3087 bool is_init_done;
3088 bool force = false;
766e6a4e 3089
f2f6c255 3090 if (!matches)
819b4861 3091 matches = &__clk_of_table;
f2f6c255 3092
1771b10d 3093 /* First prepare the list of the clocks providers */
7f7ed584 3094 for_each_matching_node_and_match(np, matches, &match) {
1771b10d
GC
3095 struct clock_provider *parent =
3096 kzalloc(sizeof(struct clock_provider), GFP_KERNEL);
3097
3098 parent->clk_init_cb = match->data;
3099 parent->np = np;
3f6d439f 3100 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3101 }
3102
3103 while (!list_empty(&clk_provider_list)) {
3104 is_init_done = false;
3105 list_for_each_entry_safe(clk_provider, next,
3106 &clk_provider_list, node) {
3107 if (force || parent_ready(clk_provider->np)) {
86be408b 3108
1771b10d 3109 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3110 of_clk_set_defaults(clk_provider->np, true);
3111
1771b10d
GC
3112 list_del(&clk_provider->node);
3113 kfree(clk_provider);
3114 is_init_done = true;
3115 }
3116 }
3117
3118 /*
e5ca8fb4 3119 * We didn't manage to initialize any of the
1771b10d
GC
3120 * remaining providers during the last loop, so now we
3121 * initialize all the remaining ones unconditionally
3122 * in case the clock parent was not mandatory
3123 */
3124 if (!is_init_done)
3125 force = true;
766e6a4e
GL
3126 }
3127}
3128#endif
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