Commit | Line | Data |
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5b48a614 SH |
1 | /* |
2 | * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | #include <linux/mm.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/clkdev.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/err.h> | |
0c831317 SG |
16 | #include <soc/imx/revision.h> |
17 | #include <asm/irq.h> | |
5b48a614 | 18 | |
5b48a614 | 19 | #include "clk.h" |
0c831317 SG |
20 | |
21 | #define MX35_CCM_BASE_ADDR 0x53f80000 | |
22 | #define MX35_GPT1_BASE_ADDR 0x53f90000 | |
23 | #define MX35_INT_GPT (NR_IRQS_LEGACY + 29) | |
24 | ||
25 | #define MXC_CCM_PDR0 0x04 | |
26 | #define MX35_CCM_PDR2 0x0c | |
27 | #define MX35_CCM_PDR3 0x10 | |
28 | #define MX35_CCM_PDR4 0x14 | |
29 | #define MX35_CCM_MPCTL 0x1c | |
30 | #define MX35_CCM_PPCTL 0x20 | |
31 | #define MX35_CCM_CGR0 0x2c | |
32 | #define MX35_CCM_CGR1 0x30 | |
33 | #define MX35_CCM_CGR2 0x34 | |
34 | #define MX35_CCM_CGR3 0x38 | |
5b48a614 SH |
35 | |
36 | struct arm_ahb_div { | |
37 | unsigned char arm, ahb, sel; | |
38 | }; | |
39 | ||
40 | static struct arm_ahb_div clk_consumer[] = { | |
41 | { .arm = 1, .ahb = 4, .sel = 0}, | |
42 | { .arm = 1, .ahb = 3, .sel = 1}, | |
43 | { .arm = 2, .ahb = 2, .sel = 0}, | |
44 | { .arm = 0, .ahb = 0, .sel = 0}, | |
45 | { .arm = 0, .ahb = 0, .sel = 0}, | |
46 | { .arm = 0, .ahb = 0, .sel = 0}, | |
47 | { .arm = 4, .ahb = 1, .sel = 0}, | |
48 | { .arm = 1, .ahb = 5, .sel = 0}, | |
49 | { .arm = 1, .ahb = 8, .sel = 0}, | |
50 | { .arm = 1, .ahb = 6, .sel = 1}, | |
51 | { .arm = 2, .ahb = 4, .sel = 0}, | |
52 | { .arm = 0, .ahb = 0, .sel = 0}, | |
53 | { .arm = 0, .ahb = 0, .sel = 0}, | |
54 | { .arm = 0, .ahb = 0, .sel = 0}, | |
55 | { .arm = 4, .ahb = 2, .sel = 0}, | |
56 | { .arm = 0, .ahb = 0, .sel = 0}, | |
57 | }; | |
58 | ||
59 | static char hsp_div_532[] = { 4, 8, 3, 0 }; | |
60 | static char hsp_div_400[] = { 3, 6, 3, 0 }; | |
61 | ||
a55a3d72 ST |
62 | static struct clk_onecell_data clk_data; |
63 | ||
5b48a614 SH |
64 | static const char *std_sel[] = {"ppll", "arm"}; |
65 | static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; | |
66 | ||
67 | enum mx35_clks { | |
68 | ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, | |
69 | arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel, | |
70 | esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre, | |
71 | spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre, | |
72 | ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate, | |
73 | audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate, | |
74 | edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate, | |
75 | esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate, | |
76 | gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate, | |
77 | kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate, | |
78 | rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate, | |
79 | ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate, | |
7852399c AG |
80 | wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate, |
81 | gpu2d_gate, clk_max | |
5b48a614 SH |
82 | }; |
83 | ||
84 | static struct clk *clk[clk_max]; | |
85 | ||
3ea80985 | 86 | int __init mx35_clocks_init(void) |
5b48a614 | 87 | { |
5ab96a8d | 88 | void __iomem *base; |
5b48a614 SH |
89 | u32 pdr0, consumer_sel, hsp_sel; |
90 | struct arm_ahb_div *aad; | |
91 | unsigned char *hsp_div; | |
5b48a614 | 92 | |
5ab96a8d SG |
93 | base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); |
94 | BUG_ON(!base); | |
95 | ||
5b48a614 SH |
96 | pdr0 = __raw_readl(base + MXC_CCM_PDR0); |
97 | consumer_sel = (pdr0 >> 16) & 0xf; | |
98 | aad = &clk_consumer[consumer_sel]; | |
99 | if (!aad->arm) { | |
100 | pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); | |
101 | /* | |
102 | * We are basically stuck. Continue with a default entry and hope we | |
103 | * get far enough to actually show the above message | |
104 | */ | |
105 | aad = &clk_consumer[0]; | |
106 | } | |
107 | ||
108 | clk[ckih] = imx_clk_fixed("ckih", 24000000); | |
3bec5f81 SG |
109 | clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); |
110 | clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); | |
5b48a614 SH |
111 | |
112 | clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); | |
113 | ||
114 | if (aad->sel) | |
115 | clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); | |
116 | else | |
117 | clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); | |
118 | ||
119 | if (clk_get_rate(clk[arm]) > 400000000) | |
120 | hsp_div = hsp_div_532; | |
121 | else | |
122 | hsp_div = hsp_div_400; | |
123 | ||
124 | hsp_sel = (pdr0 >> 20) & 0x3; | |
125 | if (!hsp_div[hsp_sel]) { | |
126 | pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); | |
127 | hsp_sel = 0; | |
128 | } | |
129 | ||
130 | clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); | |
131 | ||
132 | clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); | |
133 | clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); | |
134 | ||
135 | clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); | |
136 | clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); | |
137 | clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); | |
138 | ||
139 | clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); | |
140 | clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); | |
141 | ||
142 | clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); | |
143 | clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); | |
144 | clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); | |
145 | clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); | |
146 | ||
147 | clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); | |
148 | clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ | |
149 | clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); | |
150 | ||
151 | clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); | |
152 | clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); | |
153 | clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); | |
154 | clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); | |
155 | clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); | |
156 | ||
157 | clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); | |
158 | clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); | |
159 | ||
160 | clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); | |
161 | ||
7852399c AG |
162 | clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); |
163 | clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); | |
164 | ||
5b48a614 SH |
165 | clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); |
166 | clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); | |
167 | clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); | |
168 | clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); | |
169 | clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); | |
170 | clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); | |
171 | clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); | |
172 | clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); | |
173 | clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); | |
174 | clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); | |
175 | clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); | |
176 | clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); | |
177 | clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); | |
178 | clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); | |
179 | clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); | |
180 | clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); | |
181 | ||
182 | clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); | |
183 | clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); | |
184 | clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); | |
185 | clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); | |
186 | clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); | |
187 | clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); | |
188 | clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); | |
189 | clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); | |
190 | clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); | |
191 | clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); | |
192 | clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); | |
193 | clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); | |
194 | clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); | |
195 | clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); | |
196 | clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); | |
197 | clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); | |
198 | ||
199 | clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); | |
200 | clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); | |
201 | clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); | |
202 | clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); | |
203 | clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); | |
204 | clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); | |
205 | clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); | |
206 | clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); | |
207 | clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); | |
208 | clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); | |
209 | clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); | |
210 | clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); | |
211 | clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); | |
212 | clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); | |
213 | clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); | |
214 | ||
7852399c | 215 | clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); |
5b48a614 SH |
216 | clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); |
217 | clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); | |
218 | ||
229be9c1 | 219 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
5b48a614 | 220 | |
5b48a614 SH |
221 | clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); |
222 | clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); | |
223 | clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); | |
224 | clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0"); | |
225 | clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0"); | |
226 | clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1"); | |
227 | clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1"); | |
228 | clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0"); | |
229 | clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1"); | |
230 | clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0"); | |
231 | clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0"); | |
232 | clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0"); | |
233 | clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1"); | |
234 | clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1"); | |
235 | clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1"); | |
236 | clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2"); | |
237 | clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2"); | |
238 | clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2"); | |
239 | /* i.mx35 has the i.mx27 type fec */ | |
240 | clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); | |
241 | clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); | |
242 | clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); | |
5bdfba29 SG |
243 | clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); |
244 | clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); | |
245 | clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); | |
5b48a614 SH |
246 | clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); |
247 | clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); | |
7852399c | 248 | clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); |
5b48a614 SH |
249 | clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); |
250 | clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); | |
48540058 FE |
251 | clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); |
252 | clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); | |
5b48a614 SH |
253 | /* i.mx35 has the i.mx21 type uart */ |
254 | clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); | |
255 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); | |
256 | clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); | |
257 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); | |
258 | clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); | |
259 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); | |
260 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); | |
261 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); | |
262 | clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0"); | |
263 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); | |
264 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); | |
265 | clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1"); | |
266 | clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); | |
267 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); | |
268 | clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); | |
61c4b560 PC |
269 | clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); |
270 | clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); | |
271 | clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27"); | |
5b48a614 | 272 | clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); |
4d62435f | 273 | clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); |
7852399c | 274 | clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); |
75498083 | 275 | clk_register_clkdev(clk[admux_gate], "audmux", NULL); |
5b48a614 SH |
276 | |
277 | clk_prepare_enable(clk[spba_gate]); | |
278 | clk_prepare_enable(clk[gpio1_gate]); | |
279 | clk_prepare_enable(clk[gpio2_gate]); | |
280 | clk_prepare_enable(clk[gpio3_gate]); | |
281 | clk_prepare_enable(clk[iim_gate]); | |
282 | clk_prepare_enable(clk[emi_gate]); | |
5dc2eb7d | 283 | clk_prepare_enable(clk[max_gate]); |
cab1e0a3 | 284 | clk_prepare_enable(clk[iomuxc_gate]); |
5b48a614 | 285 | |
c520c921 UKK |
286 | /* |
287 | * SCC is needed to boot via mmc after a watchdog reset. The clock code | |
288 | * before conversion to common clk also enabled UART1 (which isn't | |
289 | * handled here and not needed for mmc) and IIM (which is enabled | |
290 | * unconditionally above). | |
291 | */ | |
292 | clk_prepare_enable(clk[scc_gate]); | |
293 | ||
5b48a614 SH |
294 | imx_print_silicon_rev("i.MX35", mx35_revision()); |
295 | ||
6c529c49 | 296 | mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT); |
5b48a614 SH |
297 | |
298 | return 0; | |
299 | } | |
a55a3d72 | 300 | |
25585daa | 301 | static void __init mx35_clocks_init_dt(struct device_node *ccm_node) |
a55a3d72 ST |
302 | { |
303 | clk_data.clks = clk; | |
304 | clk_data.clk_num = ARRAY_SIZE(clk); | |
305 | of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data); | |
306 | ||
307 | mx35_clocks_init(); | |
a55a3d72 ST |
308 | } |
309 | CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt); |