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8f6d8094 FL |
1 | /* |
2 | * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <dt-bindings/clock/imx7d-clock.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/clkdev.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <linux/of_irq.h> | |
21 | #include <linux/types.h> | |
22 | ||
23 | #include "clk.h" | |
24 | ||
25 | static struct clk *clks[IMX7D_CLK_END]; | |
26 | static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk", | |
27 | "pll_enet_500m_clk", "pll_dram_main_clk", | |
28 | "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_main_clk", | |
29 | "pll_usb_main_clk", }; | |
30 | ||
31 | static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk", | |
32 | "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk", | |
33 | "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", | |
34 | "pll_usb_main_clk", }; | |
35 | ||
36 | static const char *arm_m0_sel[] = { "osc", "pll_sys_main_120m_clk", | |
37 | "pll_enet_125m_clk", "pll_sys_pfd2_135m_clk", | |
38 | "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", | |
39 | "pll_usb_main_clk", }; | |
40 | ||
41 | static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", | |
42 | "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk", | |
43 | "pll_audio_main_clk", "pll_video_main_clk", "pll_sys_pfd7_clk", }; | |
44 | ||
45 | static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", | |
46 | "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk", | |
47 | "pll_sys_pfd7_clk", "pll_audio_main_clk", "pll_video_main_clk", }; | |
48 | ||
49 | static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk", | |
50 | "pll_dram_533m_clk", "pll_enet_250m_clk", | |
51 | "pll_sys_main_240m_clk", "pll_audio_main_clk", "pll_video_main_clk", | |
52 | "pll_sys_pfd4_clk", }; | |
53 | ||
54 | static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", | |
55 | "pll_dram_533m_clk", "pll_sys_main_240m_clk", | |
56 | "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk", | |
57 | "pll_audio_main_clk", }; | |
58 | ||
59 | static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
60 | "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", | |
61 | "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk", | |
62 | "pll_video_main_clk", }; | |
63 | ||
64 | static const char *dram_phym_sel[] = { "pll_dram_main_clk", | |
65 | "dram_phym_alt_clk", }; | |
66 | ||
67 | static const char *dram_sel[] = { "pll_dram_main_clk", | |
68 | "dram_alt_clk", }; | |
69 | ||
70 | static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk", | |
71 | "pll_sys_main_clk", "pll_enet_500m_clk", | |
72 | "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_main_clk", | |
73 | "pll_video_main_clk", }; | |
74 | ||
75 | static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk", | |
76 | "pll_sys_main_clk", "pll_enet_500m_clk", | |
77 | "pll_enet_250m_clk", "pll_sys_pfd0_392m_clk", | |
78 | "pll_audio_main_clk", "pll_sys_pfd2_270m_clk", }; | |
79 | ||
80 | static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk", | |
81 | "pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", | |
82 | "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; | |
83 | ||
84 | static const char *pcie_ctrl_sel[] = { "osc", "pll_enet_250m_clk", | |
85 | "pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk", | |
86 | "pll_dram_533m_clk", "pll_enet_500m_clk", | |
87 | "pll_sys_pfd1_332m_clk", "pll_sys_pfd6_clk", }; | |
88 | ||
89 | static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk", | |
90 | "pll_enet_500m_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", | |
91 | "ext_clk_4", "pll_sys_pfd0_392m_clk", }; | |
92 | ||
93 | static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk", | |
94 | "pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk", | |
95 | "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_main_clk", }; | |
96 | ||
97 | static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk", | |
98 | "pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk", | |
99 | "pll_sys_pfd2_270m_clk", "pll_video_main_clk", | |
100 | "pll_usb_main_clk", }; | |
101 | ||
102 | static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk", | |
103 | "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", | |
104 | "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_main_clk", }; | |
105 | ||
106 | static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk", | |
107 | "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", | |
108 | "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_main_clk", }; | |
109 | ||
110 | static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk", | |
111 | "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2", | |
112 | "pll_video_main_clk", "ext_clk_3", }; | |
113 | ||
114 | static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
115 | "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", | |
116 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; | |
117 | ||
118 | static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
119 | "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", | |
120 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; | |
121 | ||
122 | static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
123 | "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", | |
124 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", }; | |
125 | ||
126 | static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
127 | "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", | |
128 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", }; | |
129 | ||
130 | static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk", | |
131 | "pll_enet_50m_clk", "pll_enet_25m_clk", | |
132 | "pll_sys_main_120m_clk", "pll_audio_main_clk", "pll_video_main_clk", | |
133 | "ext_clk_4", }; | |
134 | ||
135 | static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk", | |
136 | "pll_audio_main_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", | |
137 | "ext_clk_4", "pll_video_main_clk", }; | |
138 | ||
139 | static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk", | |
140 | "pll_enet_50m_clk", "pll_enet_25m_clk", | |
141 | "pll_sys_main_120m_clk", "pll_audio_main_clk", "pll_video_main_clk", | |
142 | "ext_clk_4", }; | |
143 | ||
144 | static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk", | |
145 | "pll_audio_main_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", | |
146 | "ext_clk_4", "pll_video_main_clk", }; | |
147 | ||
148 | static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk", | |
149 | "pll_enet_50m_clk", "pll_enet_125m_clk", | |
150 | "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", | |
151 | "pll_sys_pfd3_clk", }; | |
152 | ||
153 | static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
154 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | |
155 | "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_enet_125m_clk", | |
156 | "pll_usb_main_clk", }; | |
157 | ||
158 | static const char *nand_sel[] = { "osc", "pll_sys_main_clk", | |
159 | "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk", | |
160 | "pll_enet_500m_clk", "pll_enet_250m_clk", | |
161 | "pll_video_main_clk", }; | |
162 | ||
163 | static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk", | |
164 | "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk", | |
165 | "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; | |
166 | ||
167 | static const char *usdhc1_sel[] = { "osc", "pll_sys_pfd0_392m_clk", | |
168 | "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", | |
169 | "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; | |
170 | ||
171 | static const char *usdhc2_sel[] = { "osc", "pll_sys_pfd0_392m_clk", | |
172 | "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", | |
173 | "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; | |
174 | ||
175 | static const char *usdhc3_sel[] = { "osc", "pll_sys_pfd0_392m_clk", | |
176 | "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk", | |
177 | "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", }; | |
178 | ||
179 | static const char *can1_sel[] = { "osc", "pll_sys_main_120m_clk", | |
180 | "pll_dram_533m_clk", "pll_sys_main_clk", | |
181 | "pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1", | |
182 | "ext_clk_4", }; | |
183 | ||
184 | static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk", | |
185 | "pll_dram_533m_clk", "pll_sys_main_clk", | |
186 | "pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1", | |
187 | "ext_clk_3", }; | |
188 | ||
189 | static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk", | |
190 | "pll_enet_50m_clk", "pll_dram_533m_clk", | |
191 | "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", | |
192 | "pll_sys_pfd2_135m_clk", }; | |
193 | ||
194 | static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk", | |
195 | "pll_enet_50m_clk", "pll_dram_533m_clk", | |
196 | "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", | |
197 | "pll_sys_pfd2_135m_clk", }; | |
198 | ||
199 | static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk", | |
200 | "pll_enet_50m_clk", "pll_dram_533m_clk", | |
201 | "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", | |
202 | "pll_sys_pfd2_135m_clk", }; | |
203 | ||
204 | static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk", | |
205 | "pll_enet_50m_clk", "pll_dram_533m_clk", | |
206 | "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", | |
207 | "pll_sys_pfd2_135m_clk", }; | |
208 | ||
209 | static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk", | |
210 | "pll_enet_40m_clk", "pll_enet_100m_clk", | |
211 | "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", | |
212 | "pll_usb_main_clk", }; | |
213 | ||
214 | static const char *uart2_sel[] = { "osc", "pll_sys_main_240m_clk", | |
215 | "pll_enet_40m_clk", "pll_enet_100m_clk", | |
216 | "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", | |
217 | "pll_usb_main_clk", }; | |
218 | ||
219 | static const char *uart3_sel[] = { "osc", "pll_sys_main_240m_clk", | |
220 | "pll_enet_40m_clk", "pll_enet_100m_clk", | |
221 | "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", | |
222 | "pll_usb_main_clk", }; | |
223 | ||
224 | static const char *uart4_sel[] = { "osc", "pll_sys_main_240m_clk", | |
225 | "pll_enet_40m_clk", "pll_enet_100m_clk", | |
226 | "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", | |
227 | "pll_usb_main_clk", }; | |
228 | ||
229 | static const char *uart5_sel[] = { "osc", "pll_sys_main_240m_clk", | |
230 | "pll_enet_40m_clk", "pll_enet_100m_clk", | |
231 | "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", | |
232 | "pll_usb_main_clk", }; | |
233 | ||
234 | static const char *uart6_sel[] = { "osc", "pll_sys_main_240m_clk", | |
235 | "pll_enet_40m_clk", "pll_enet_100m_clk", | |
236 | "pll_sys_main_clk", "ext_clk_2", "ext_clk_3", | |
237 | "pll_usb_main_clk", }; | |
238 | ||
239 | static const char *uart7_sel[] = { "osc", "pll_sys_main_240m_clk", | |
240 | "pll_enet_40m_clk", "pll_enet_100m_clk", | |
241 | "pll_sys_main_clk", "ext_clk_2", "ext_clk_4", | |
242 | "pll_usb_main_clk", }; | |
243 | ||
244 | static const char *ecspi1_sel[] = { "osc", "pll_sys_main_240m_clk", | |
245 | "pll_enet_40m_clk", "pll_sys_main_120m_clk", | |
246 | "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", | |
247 | "pll_usb_main_clk", }; | |
248 | ||
249 | static const char *ecspi2_sel[] = { "osc", "pll_sys_main_240m_clk", | |
250 | "pll_enet_40m_clk", "pll_sys_main_120m_clk", | |
251 | "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", | |
252 | "pll_usb_main_clk", }; | |
253 | ||
254 | static const char *ecspi3_sel[] = { "osc", "pll_sys_main_240m_clk", | |
255 | "pll_enet_40m_clk", "pll_sys_main_120m_clk", | |
256 | "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", | |
257 | "pll_usb_main_clk", }; | |
258 | ||
259 | static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk", | |
260 | "pll_enet_40m_clk", "pll_sys_main_120m_clk", | |
261 | "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk", | |
262 | "pll_usb_main_clk", }; | |
263 | ||
264 | static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk", | |
265 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | |
266 | "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; | |
267 | ||
268 | static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk", | |
269 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | |
270 | "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; | |
271 | ||
272 | static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk", | |
273 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | |
274 | "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; | |
275 | ||
276 | static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk", | |
277 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | |
278 | "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; | |
279 | ||
280 | static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk", | |
281 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | |
282 | "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; | |
283 | ||
284 | static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk", | |
285 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | |
286 | "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; | |
287 | ||
288 | static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
289 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | |
290 | "pll_usb_main_clk", "pll_audio_main_clk", "pll_enet_125m_clk", | |
291 | "pll_sys_pfd7_clk", }; | |
292 | ||
293 | static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
294 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | |
295 | "pll_usb_main_clk", "pll_video_main_clk", "pll_enet_125m_clk", | |
296 | "pll_sys_pfd7_clk", }; | |
297 | ||
298 | static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk", | |
299 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", | |
300 | "ref_1m_clk", "pll_audio_main_clk", "ext_clk_1", }; | |
301 | ||
302 | static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk", | |
303 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", | |
304 | "ref_1m_clk", "pll_audio_main_clk", "ext_clk_2", }; | |
305 | ||
306 | static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk", | |
307 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", | |
308 | "ref_1m_clk", "pll_audio_main_clk", "ext_clk_3", }; | |
309 | ||
310 | static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk", | |
311 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", | |
312 | "ref_1m_clk", "pll_audio_main_clk", "ext_clk_4", }; | |
313 | ||
314 | static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
315 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | |
316 | "pll_enet_125m_clk", "pll_usb_main_clk", "ext_clk_2", | |
317 | "ext_clk_3", }; | |
318 | ||
319 | static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
320 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | |
321 | "pll_enet_125m_clk", "pll_usb_main_clk", "ref_1m_clk", | |
322 | "pll_sys_pfd1_166m_clk", }; | |
323 | ||
324 | static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
325 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | |
326 | "pll_enet_125m_clk", "pll_audio_main_clk", "pll_video_main_clk", | |
327 | "pll_usb_main_clk", }; | |
328 | ||
329 | static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |
330 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | |
331 | "pll_enet_125m_clk", "pll_audio_main_clk", "pll_video_main_clk", | |
332 | "pll_usb_main_clk", }; | |
333 | ||
334 | static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk", | |
335 | "pll_dram_533m_clk", "pll_usb_main_clk", | |
336 | "pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk", | |
337 | "pll_enet_500m_clk", "pll_sys_pfd7_clk", }; | |
338 | ||
339 | static const char *clko1_sel[] = { "osc", "pll_sys_main_clk", | |
340 | "pll_sys_main_240m_clk", "pll_sys_pfd0_196m_clk", "pll_sys_pfd3_clk", | |
341 | "pll_enet_500m_clk", "pll_dram_533m_clk", "ref_1m_clk", }; | |
342 | ||
343 | static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk", | |
344 | "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk", | |
345 | "pll_audio_main_clk", "pll_video_main_clk", "osc_32k_clk", }; | |
346 | ||
347 | static const char *lvds1_sel[] = { "pll_arm_main_clk", | |
348 | "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk", | |
349 | "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", | |
350 | "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", | |
351 | "pll_audio_main_clk", "pll_video_main_clk", "pll_enet_500m_clk", | |
352 | "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk", | |
353 | "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk", | |
354 | "pll_dram_main_clk", }; | |
355 | ||
356 | static const char *pll_bypass_src_sel[] = { "osc", "dummy", }; | |
357 | static const char *pll_arm_bypass_sel[] = { "pll_arm_main", "pll_arm_main_src", }; | |
358 | static const char *pll_dram_bypass_sel[] = { "pll_dram_main", "pll_dram_main_src", }; | |
359 | static const char *pll_sys_bypass_sel[] = { "pll_sys_main", "pll_sys_main_src", }; | |
360 | static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src", }; | |
361 | static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", }; | |
362 | static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", }; | |
363 | ||
364 | static struct clk_onecell_data clk_data; | |
365 | ||
1b9af68f LS |
366 | static struct clk ** const uart_clks[] __initconst = { |
367 | &clks[IMX7D_UART1_ROOT_CLK], | |
368 | &clks[IMX7D_UART2_ROOT_CLK], | |
369 | &clks[IMX7D_UART3_ROOT_CLK], | |
370 | &clks[IMX7D_UART4_ROOT_CLK], | |
371 | &clks[IMX7D_UART5_ROOT_CLK], | |
372 | &clks[IMX7D_UART6_ROOT_CLK], | |
373 | &clks[IMX7D_UART7_ROOT_CLK], | |
374 | NULL | |
375 | }; | |
376 | ||
8f6d8094 FL |
377 | static void __init imx7d_clocks_init(struct device_node *ccm_node) |
378 | { | |
379 | struct device_node *np; | |
380 | void __iomem *base; | |
381 | int i; | |
382 | ||
383 | clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0); | |
384 | clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc"); | |
385 | ||
386 | np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop"); | |
387 | base = of_iomap(np, 0); | |
388 | WARN_ON(!base); | |
389 | ||
390 | clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); | |
391 | clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); | |
392 | clks[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); | |
393 | clks[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); | |
394 | clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); | |
395 | clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); | |
396 | ||
397 | clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "pll_arm_main_src", base + 0x60, 0x7f); | |
398 | clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_dram_main", "pll_dram_main_src", base + 0x70, 0x7f); | |
399 | clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "pll_sys_main_src", base + 0xb0, 0x1); | |
400 | clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "pll_enet_main_src", base + 0xe0, 0x0); | |
401 | clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "pll_audio_main_src", base + 0xf0, 0x7f); | |
402 | clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "pll_video_main_src", base + 0x130, 0x7f); | |
403 | ||
404 | clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT); | |
405 | clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT); | |
406 | clks[IMX7D_PLL_SYS_MAIN_BYPASS] = imx_clk_mux_flags("pll_sys_main_bypass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel), CLK_SET_RATE_PARENT); | |
407 | clks[IMX7D_PLL_ENET_MAIN_BYPASS] = imx_clk_mux_flags("pll_enet_main_bypass", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel), CLK_SET_RATE_PARENT); | |
408 | clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT); | |
409 | clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT); | |
410 | ||
411 | clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); | |
412 | clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); | |
413 | clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); | |
414 | clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]); | |
415 | clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]); | |
416 | clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]); | |
417 | ||
418 | clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13); | |
419 | clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_main_bypass", base + 0x70, 13); | |
420 | clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13); | |
421 | clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); | |
422 | clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); | |
423 | ||
424 | clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); | |
425 | clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); | |
426 | clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2); | |
427 | ||
428 | clks[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_pfd("pll_sys_pfd3_clk", "pll_sys_main_clk", base + 0xc0, 3); | |
429 | clks[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_pfd("pll_sys_pfd4_clk", "pll_sys_main_clk", base + 0xd0, 0); | |
430 | clks[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_pfd("pll_sys_pfd5_clk", "pll_sys_main_clk", base + 0xd0, 1); | |
431 | clks[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_pfd("pll_sys_pfd6_clk", "pll_sys_main_clk", base + 0xd0, 2); | |
432 | clks[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_pfd("pll_sys_pfd7_clk", "pll_sys_main_clk", base + 0xd0, 3); | |
433 | ||
434 | clks[IMX7D_PLL_SYS_MAIN_480M] = imx_clk_fixed_factor("pll_sys_main_480m", "pll_sys_main_clk", 1, 1); | |
435 | clks[IMX7D_PLL_SYS_MAIN_240M] = imx_clk_fixed_factor("pll_sys_main_240m", "pll_sys_main_clk", 1, 2); | |
436 | clks[IMX7D_PLL_SYS_MAIN_120M] = imx_clk_fixed_factor("pll_sys_main_120m", "pll_sys_main_clk", 1, 4); | |
437 | clks[IMX7D_PLL_DRAM_MAIN_533M] = imx_clk_fixed_factor("pll_dram_533m", "pll_dram_main_clk", 1, 2); | |
438 | ||
439 | clks[IMX7D_PLL_SYS_MAIN_480M_CLK] = imx_clk_gate_dis("pll_sys_main_480m_clk", "pll_sys_main_480m", base + 0xb0, 4); | |
440 | clks[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m", base + 0xb0, 5); | |
441 | clks[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m", base + 0xb0, 6); | |
442 | clks[IMX7D_PLL_DRAM_MAIN_533M_CLK] = imx_clk_gate("pll_dram_533m_clk", "pll_dram_533m", base + 0x70, 12); | |
443 | ||
444 | clks[IMX7D_PLL_SYS_PFD0_196M] = imx_clk_fixed_factor("pll_sys_pfd0_196m", "pll_sys_pfd0_392m_clk", 1, 2); | |
445 | clks[IMX7D_PLL_SYS_PFD1_166M] = imx_clk_fixed_factor("pll_sys_pfd1_166m", "pll_sys_pfd1_332m_clk", 1, 2); | |
446 | clks[IMX7D_PLL_SYS_PFD2_135M] = imx_clk_fixed_factor("pll_sys_pfd2_135m", "pll_sys_pfd2_270m_clk", 1, 2); | |
447 | ||
448 | clks[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m", base + 0xb0, 26); | |
449 | clks[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m", base + 0xb0, 27); | |
450 | clks[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m", base + 0xb0, 28); | |
451 | ||
452 | clks[IMX7D_PLL_ENET_MAIN_CLK] = imx_clk_fixed_factor("pll_enet_main_clk", "pll_enet_main_bypass", 1, 1); | |
453 | clks[IMX7D_PLL_ENET_MAIN_500M] = imx_clk_fixed_factor("pll_enet_500m", "pll_enet_main_clk", 1, 2); | |
454 | clks[IMX7D_PLL_ENET_MAIN_250M] = imx_clk_fixed_factor("pll_enet_250m", "pll_enet_main_clk", 1, 4); | |
455 | clks[IMX7D_PLL_ENET_MAIN_125M] = imx_clk_fixed_factor("pll_enet_125m", "pll_enet_main_clk", 1, 8); | |
456 | clks[IMX7D_PLL_ENET_MAIN_100M] = imx_clk_fixed_factor("pll_enet_100m", "pll_enet_main_clk", 1, 10); | |
457 | clks[IMX7D_PLL_ENET_MAIN_50M] = imx_clk_fixed_factor("pll_enet_50m", "pll_enet_main_clk", 1, 20); | |
458 | clks[IMX7D_PLL_ENET_MAIN_40M] = imx_clk_fixed_factor("pll_enet_40m", "pll_enet_main_clk", 1, 25); | |
459 | clks[IMX7D_PLL_ENET_MAIN_25M] = imx_clk_fixed_factor("pll_enet_25m", "pll_enet_main_clk", 1, 40); | |
460 | ||
461 | clks[IMX7D_PLL_ENET_MAIN_500M_CLK] = imx_clk_gate("pll_enet_500m_clk", "pll_enet_500m", base + 0xe0, 12); | |
462 | clks[IMX7D_PLL_ENET_MAIN_250M_CLK] = imx_clk_gate("pll_enet_250m_clk", "pll_enet_250m", base + 0xe0, 11); | |
463 | clks[IMX7D_PLL_ENET_MAIN_125M_CLK] = imx_clk_gate("pll_enet_125m_clk", "pll_enet_125m", base + 0xe0, 10); | |
464 | clks[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe0, 9); | |
465 | clks[IMX7D_PLL_ENET_MAIN_50M_CLK] = imx_clk_gate("pll_enet_50m_clk", "pll_enet_50m", base + 0xe0, 8); | |
466 | clks[IMX7D_PLL_ENET_MAIN_40M_CLK] = imx_clk_gate("pll_enet_40m_clk", "pll_enet_40m", base + 0xe0, 7); | |
467 | clks[IMX7D_PLL_ENET_MAIN_25M_CLK] = imx_clk_gate("pll_enet_25m_clk", "pll_enet_25m", base + 0xe0, 6); | |
468 | ||
469 | clks[IMX7D_LVDS1_OUT_SEL] = imx_clk_mux("lvds1_sel", base + 0x170, 0, 5, lvds1_sel, ARRAY_SIZE(lvds1_sel)); | |
470 | clks[IMX7D_LVDS1_OUT_CLK] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x170, 5, BIT(6)); | |
471 | ||
472 | np = ccm_node; | |
473 | base = of_iomap(np, 0); | |
474 | WARN_ON(!base); | |
475 | ||
476 | clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel)); | |
477 | clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel)); | |
478 | clks[IMX7D_ARM_M0_ROOT_SRC] = imx_clk_mux("arm_m0_src", base + 0x8100, 24, 3, arm_m0_sel, ARRAY_SIZE(arm_m0_sel)); | |
479 | clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel)); | |
480 | clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel)); | |
481 | clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel)); | |
482 | clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel)); | |
483 | clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel)); | |
484 | clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel)); | |
485 | clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel)); | |
486 | clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel)); | |
487 | clks[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_mux("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel)); | |
488 | clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel)); | |
489 | clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel)); | |
490 | clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel)); | |
491 | clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel)); | |
492 | clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel)); | |
493 | clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel)); | |
494 | clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel)); | |
495 | clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel)); | |
496 | clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel)); | |
497 | clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel)); | |
498 | clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel)); | |
499 | clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel)); | |
500 | clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel)); | |
501 | clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel)); | |
502 | clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel)); | |
503 | clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel)); | |
504 | clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel)); | |
505 | clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel)); | |
506 | clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel)); | |
507 | clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel)); | |
508 | clks[IMX7D_USDHC1_ROOT_SRC] = imx_clk_mux("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel)); | |
509 | clks[IMX7D_USDHC2_ROOT_SRC] = imx_clk_mux("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel)); | |
510 | clks[IMX7D_USDHC3_ROOT_SRC] = imx_clk_mux("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel)); | |
511 | clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel)); | |
512 | clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel)); | |
513 | clks[IMX7D_I2C1_ROOT_SRC] = imx_clk_mux("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel)); | |
514 | clks[IMX7D_I2C2_ROOT_SRC] = imx_clk_mux("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel)); | |
515 | clks[IMX7D_I2C3_ROOT_SRC] = imx_clk_mux("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel)); | |
516 | clks[IMX7D_I2C4_ROOT_SRC] = imx_clk_mux("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel)); | |
517 | clks[IMX7D_UART1_ROOT_SRC] = imx_clk_mux("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel)); | |
518 | clks[IMX7D_UART2_ROOT_SRC] = imx_clk_mux("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel)); | |
519 | clks[IMX7D_UART3_ROOT_SRC] = imx_clk_mux("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel)); | |
520 | clks[IMX7D_UART4_ROOT_SRC] = imx_clk_mux("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel)); | |
521 | clks[IMX7D_UART5_ROOT_SRC] = imx_clk_mux("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel)); | |
522 | clks[IMX7D_UART6_ROOT_SRC] = imx_clk_mux("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel)); | |
523 | clks[IMX7D_UART7_ROOT_SRC] = imx_clk_mux("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel)); | |
524 | clks[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_mux("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel)); | |
525 | clks[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_mux("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel)); | |
526 | clks[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_mux("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel)); | |
527 | clks[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_mux("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel)); | |
528 | clks[IMX7D_PWM1_ROOT_SRC] = imx_clk_mux("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel)); | |
529 | clks[IMX7D_PWM2_ROOT_SRC] = imx_clk_mux("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel)); | |
530 | clks[IMX7D_PWM3_ROOT_SRC] = imx_clk_mux("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel)); | |
531 | clks[IMX7D_PWM4_ROOT_SRC] = imx_clk_mux("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel)); | |
532 | clks[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_mux("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel)); | |
533 | clks[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_mux("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel)); | |
534 | clks[IMX7D_SIM1_ROOT_SRC] = imx_clk_mux("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel)); | |
535 | clks[IMX7D_SIM2_ROOT_SRC] = imx_clk_mux("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel)); | |
536 | clks[IMX7D_GPT1_ROOT_SRC] = imx_clk_mux("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel)); | |
537 | clks[IMX7D_GPT2_ROOT_SRC] = imx_clk_mux("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel)); | |
538 | clks[IMX7D_GPT3_ROOT_SRC] = imx_clk_mux("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel)); | |
539 | clks[IMX7D_GPT4_ROOT_SRC] = imx_clk_mux("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel)); | |
540 | clks[IMX7D_TRACE_ROOT_SRC] = imx_clk_mux("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel)); | |
541 | clks[IMX7D_WDOG_ROOT_SRC] = imx_clk_mux("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel)); | |
542 | clks[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_mux("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel)); | |
543 | clks[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_mux("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel)); | |
544 | clks[IMX7D_WRCLK_ROOT_SRC] = imx_clk_mux("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel)); | |
545 | clks[IMX7D_CLKO1_ROOT_SRC] = imx_clk_mux("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel)); | |
546 | clks[IMX7D_CLKO2_ROOT_SRC] = imx_clk_mux("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel)); | |
547 | ||
548 | clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate("arm_a7_cg", "arm_a7_src", base + 0x8000, 28); | |
549 | clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); | |
550 | clks[IMX7D_ARM_M0_ROOT_CG] = imx_clk_gate("arm_m0_cg", "arm_m0_src", base + 0x8100, 28); | |
551 | clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate("axi_cg", "axi_src", base + 0x8800, 28); | |
552 | clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate("disp_axi_cg", "disp_axi_src", base + 0x8880, 28); | |
553 | clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate("enet_axi_cg", "enet_axi_src", base + 0x8900, 28); | |
554 | clks[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_gate("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28); | |
555 | clks[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_gate("ahb_cg", "ahb_src", base + 0x9000, 28); | |
556 | clks[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_gate("dram_phym_cg", "dram_phym_src", base + 0x9800, 28); | |
557 | clks[IMX7D_DRAM_ROOT_CG] = imx_clk_gate("dram_cg", "dram_src", base + 0x9880, 28); | |
558 | clks[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_gate("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28); | |
559 | clks[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_gate("dram_alt_cg", "dram_alt_src", base + 0xa080, 28); | |
560 | clks[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_gate("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28); | |
561 | clks[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_gate("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28); | |
562 | clks[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_gate("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28); | |
563 | clks[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_gate("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28); | |
564 | clks[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_gate("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28); | |
565 | clks[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_gate("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28); | |
566 | clks[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_gate("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28); | |
567 | clks[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_gate("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28); | |
568 | clks[IMX7D_SAI1_ROOT_CG] = imx_clk_gate("sai1_cg", "sai1_src", base + 0xa500, 28); | |
569 | clks[IMX7D_SAI2_ROOT_CG] = imx_clk_gate("sai2_cg", "sai2_src", base + 0xa580, 28); | |
570 | clks[IMX7D_SAI3_ROOT_CG] = imx_clk_gate("sai3_cg", "sai3_src", base + 0xa600, 28); | |
571 | clks[IMX7D_SPDIF_ROOT_CG] = imx_clk_gate("spdif_cg", "spdif_src", base + 0xa680, 28); | |
572 | clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28); | |
573 | clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate("enet1_time_cg", "enet1_time_src", base + 0xa780, 28); | |
574 | clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28); | |
575 | clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate("enet2_time_cg", "enet2_time_src", base + 0xa880, 28); | |
576 | clks[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_gate("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28); | |
577 | clks[IMX7D_EIM_ROOT_CG] = imx_clk_gate("eim_cg", "eim_src", base + 0xa980, 28); | |
578 | clks[IMX7D_NAND_ROOT_CG] = imx_clk_gate("nand_cg", "nand_src", base + 0xaa00, 28); | |
579 | clks[IMX7D_QSPI_ROOT_CG] = imx_clk_gate("qspi_cg", "qspi_src", base + 0xaa80, 28); | |
580 | clks[IMX7D_USDHC1_ROOT_CG] = imx_clk_gate("usdhc1_cg", "usdhc1_src", base + 0xab00, 28); | |
581 | clks[IMX7D_USDHC2_ROOT_CG] = imx_clk_gate("usdhc2_cg", "usdhc2_src", base + 0xab80, 28); | |
582 | clks[IMX7D_USDHC3_ROOT_CG] = imx_clk_gate("usdhc3_cg", "usdhc3_src", base + 0xac00, 28); | |
583 | clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate("can1_cg", "can1_src", base + 0xac80, 28); | |
584 | clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate("can2_cg", "can2_src", base + 0xad00, 28); | |
585 | clks[IMX7D_I2C1_ROOT_CG] = imx_clk_gate("i2c1_cg", "i2c1_src", base + 0xad80, 28); | |
586 | clks[IMX7D_I2C2_ROOT_CG] = imx_clk_gate("i2c2_cg", "i2c2_src", base + 0xae00, 28); | |
587 | clks[IMX7D_I2C3_ROOT_CG] = imx_clk_gate("i2c3_cg", "i2c3_src", base + 0xae80, 28); | |
588 | clks[IMX7D_I2C4_ROOT_CG] = imx_clk_gate("i2c4_cg", "i2c4_src", base + 0xaf00, 28); | |
589 | clks[IMX7D_UART1_ROOT_CG] = imx_clk_gate("uart1_cg", "uart1_src", base + 0xaf80, 28); | |
590 | clks[IMX7D_UART2_ROOT_CG] = imx_clk_gate("uart2_cg", "uart2_src", base + 0xb000, 28); | |
591 | clks[IMX7D_UART3_ROOT_CG] = imx_clk_gate("uart3_cg", "uart3_src", base + 0xb080, 28); | |
592 | clks[IMX7D_UART4_ROOT_CG] = imx_clk_gate("uart4_cg", "uart4_src", base + 0xb100, 28); | |
593 | clks[IMX7D_UART5_ROOT_CG] = imx_clk_gate("uart5_cg", "uart5_src", base + 0xb180, 28); | |
594 | clks[IMX7D_UART6_ROOT_CG] = imx_clk_gate("uart6_cg", "uart6_src", base + 0xb200, 28); | |
595 | clks[IMX7D_UART7_ROOT_CG] = imx_clk_gate("uart7_cg", "uart7_src", base + 0xb280, 28); | |
596 | clks[IMX7D_ECSPI1_ROOT_CG] = imx_clk_gate("ecspi1_cg", "ecspi1_src", base + 0xb300, 28); | |
597 | clks[IMX7D_ECSPI2_ROOT_CG] = imx_clk_gate("ecspi2_cg", "ecspi2_src", base + 0xb380, 28); | |
598 | clks[IMX7D_ECSPI3_ROOT_CG] = imx_clk_gate("ecspi3_cg", "ecspi3_src", base + 0xb400, 28); | |
599 | clks[IMX7D_ECSPI4_ROOT_CG] = imx_clk_gate("ecspi4_cg", "ecspi4_src", base + 0xb480, 28); | |
600 | clks[IMX7D_PWM1_ROOT_CG] = imx_clk_gate("pwm1_cg", "pwm1_src", base + 0xb500, 28); | |
601 | clks[IMX7D_PWM2_ROOT_CG] = imx_clk_gate("pwm2_cg", "pwm2_src", base + 0xb580, 28); | |
602 | clks[IMX7D_PWM3_ROOT_CG] = imx_clk_gate("pwm3_cg", "pwm3_src", base + 0xb600, 28); | |
603 | clks[IMX7D_PWM4_ROOT_CG] = imx_clk_gate("pwm4_cg", "pwm4_src", base + 0xb680, 28); | |
604 | clks[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_gate("flextimer1_cg", "flextimer1_src", base + 0xb700, 28); | |
605 | clks[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_gate("flextimer2_cg", "flextimer2_src", base + 0xb780, 28); | |
606 | clks[IMX7D_SIM1_ROOT_CG] = imx_clk_gate("sim1_cg", "sim1_src", base + 0xb800, 28); | |
607 | clks[IMX7D_SIM2_ROOT_CG] = imx_clk_gate("sim2_cg", "sim2_src", base + 0xb880, 28); | |
608 | clks[IMX7D_GPT1_ROOT_CG] = imx_clk_gate("gpt1_cg", "gpt1_src", base + 0xb900, 28); | |
609 | clks[IMX7D_GPT2_ROOT_CG] = imx_clk_gate("gpt2_cg", "gpt2_src", base + 0xb980, 28); | |
610 | clks[IMX7D_GPT3_ROOT_CG] = imx_clk_gate("gpt3_cg", "gpt3_src", base + 0xbA00, 28); | |
611 | clks[IMX7D_GPT4_ROOT_CG] = imx_clk_gate("gpt4_cg", "gpt4_src", base + 0xbA80, 28); | |
612 | clks[IMX7D_TRACE_ROOT_CG] = imx_clk_gate("trace_cg", "trace_src", base + 0xbb00, 28); | |
613 | clks[IMX7D_WDOG_ROOT_CG] = imx_clk_gate("wdog_cg", "wdog_src", base + 0xbb80, 28); | |
614 | clks[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_gate("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28); | |
615 | clks[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_gate("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28); | |
616 | clks[IMX7D_WRCLK_ROOT_CG] = imx_clk_gate("wrclk_cg", "wrclk_src", base + 0xbd00, 28); | |
617 | clks[IMX7D_CLKO1_ROOT_CG] = imx_clk_gate("clko1_cg", "clko1_src", base + 0xbd80, 28); | |
618 | clks[IMX7D_CLKO2_ROOT_CG] = imx_clk_gate("clko2_cg", "clko2_src", base + 0xbe00, 28); | |
619 | ||
620 | clks[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_divider("axi_pre_div", "axi_cg", base + 0x8800, 16, 3); | |
621 | clks[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_divider("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3); | |
622 | clks[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_divider("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3); | |
623 | clks[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_divider("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3); | |
624 | clks[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_divider("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3); | |
625 | clks[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_divider("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3); | |
626 | clks[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_divider("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3); | |
627 | clks[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_divider("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3); | |
628 | clks[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_divider("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3); | |
629 | clks[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_divider("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3); | |
630 | clks[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_divider("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3); | |
631 | clks[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_divider("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3); | |
632 | clks[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_divider("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3); | |
633 | clks[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_divider("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3); | |
634 | clks[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_divider("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3); | |
635 | clks[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_divider("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3); | |
636 | clks[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_divider("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3); | |
637 | clks[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_divider("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3); | |
638 | clks[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_divider("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3); | |
639 | clks[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_divider("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3); | |
640 | clks[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_divider("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3); | |
641 | clks[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_divider("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3); | |
642 | clks[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_divider("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3); | |
643 | clks[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_divider("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3); | |
644 | clks[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_divider("eim_pre_div", "eim_cg", base + 0xa980, 16, 3); | |
645 | clks[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_divider("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3); | |
646 | clks[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_divider("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3); | |
647 | clks[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_divider("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3); | |
648 | clks[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_divider("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3); | |
649 | clks[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_divider("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3); | |
650 | clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider("can1_pre_div", "can1_cg", base + 0xac80, 16, 3); | |
651 | clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider("can2_pre_div", "can2_cg", base + 0xad00, 16, 3); | |
652 | clks[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_divider("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3); | |
653 | clks[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_divider("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3); | |
654 | clks[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_divider("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3); | |
655 | clks[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_divider("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3); | |
656 | clks[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_divider("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3); | |
657 | clks[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_divider("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3); | |
658 | clks[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_divider("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3); | |
659 | clks[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_divider("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3); | |
660 | clks[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_divider("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3); | |
661 | clks[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_divider("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3); | |
662 | clks[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_divider("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3); | |
663 | clks[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_divider("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3); | |
664 | clks[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_divider("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3); | |
665 | clks[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_divider("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3); | |
666 | clks[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_divider("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3); | |
667 | clks[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_divider("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3); | |
668 | clks[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_divider("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3); | |
669 | clks[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_divider("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3); | |
670 | clks[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_divider("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3); | |
671 | clks[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_divider("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3); | |
672 | clks[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_divider("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3); | |
673 | clks[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_divider("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3); | |
674 | clks[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_divider("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3); | |
675 | clks[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_divider("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3); | |
676 | clks[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_divider("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3); | |
677 | clks[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_divider("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3); | |
678 | clks[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_divider("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3); | |
679 | clks[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_divider("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3); | |
680 | clks[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_divider("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3); | |
681 | clks[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_divider("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3); | |
682 | clks[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_divider("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3); | |
683 | clks[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_divider("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3); | |
684 | clks[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_divider("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3); | |
685 | clks[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_divider("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3); | |
686 | ||
687 | clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3); | |
688 | clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); | |
689 | clks[IMX7D_ARM_M0_ROOT_DIV] = imx_clk_divider("arm_m0_div", "arm_m0_cg", base + 0x8100, 0, 3); | |
690 | clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6); | |
691 | clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); | |
692 | clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); | |
693 | clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6); | |
694 | clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6); | |
695 | clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider("dram_post_div", "dram_cg", base + 0x9880, 0, 3); | |
696 | clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); | |
697 | clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); | |
698 | clks[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_divider("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6); | |
699 | clks[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_divider("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6); | |
700 | clks[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_divider("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6); | |
701 | clks[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_divider("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6); | |
702 | clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6); | |
703 | clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6); | |
704 | clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6); | |
705 | clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6); | |
706 | clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6); | |
707 | clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6); | |
708 | clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6); | |
709 | clks[IMX7D_SPDIF_ROOT_DIV] = imx_clk_divider("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6); | |
710 | clks[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_divider("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6); | |
711 | clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6); | |
712 | clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6); | |
713 | clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); | |
714 | clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); | |
715 | clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); | |
716 | clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6); | |
717 | clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); | |
718 | clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); | |
719 | clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); | |
720 | clks[IMX7D_USDHC3_ROOT_DIV] = imx_clk_divider("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6); | |
721 | clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6); | |
722 | clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6); | |
723 | clks[IMX7D_I2C1_ROOT_DIV] = imx_clk_divider("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6); | |
724 | clks[IMX7D_I2C2_ROOT_DIV] = imx_clk_divider("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6); | |
725 | clks[IMX7D_I2C3_ROOT_DIV] = imx_clk_divider("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6); | |
726 | clks[IMX7D_I2C4_ROOT_DIV] = imx_clk_divider("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6); | |
727 | clks[IMX7D_UART1_ROOT_DIV] = imx_clk_divider("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6); | |
728 | clks[IMX7D_UART2_ROOT_DIV] = imx_clk_divider("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6); | |
729 | clks[IMX7D_UART3_ROOT_DIV] = imx_clk_divider("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6); | |
730 | clks[IMX7D_UART4_ROOT_DIV] = imx_clk_divider("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6); | |
731 | clks[IMX7D_UART5_ROOT_DIV] = imx_clk_divider("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6); | |
732 | clks[IMX7D_UART6_ROOT_DIV] = imx_clk_divider("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6); | |
733 | clks[IMX7D_UART7_ROOT_DIV] = imx_clk_divider("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6); | |
734 | clks[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_divider("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6); | |
735 | clks[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_divider("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6); | |
736 | clks[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_divider("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6); | |
737 | clks[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_divider("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6); | |
738 | clks[IMX7D_PWM1_ROOT_DIV] = imx_clk_divider("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6); | |
739 | clks[IMX7D_PWM2_ROOT_DIV] = imx_clk_divider("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6); | |
740 | clks[IMX7D_PWM3_ROOT_DIV] = imx_clk_divider("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6); | |
741 | clks[IMX7D_PWM4_ROOT_DIV] = imx_clk_divider("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6); | |
742 | clks[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_divider("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6); | |
743 | clks[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_divider("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6); | |
744 | clks[IMX7D_SIM1_ROOT_DIV] = imx_clk_divider("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6); | |
745 | clks[IMX7D_SIM2_ROOT_DIV] = imx_clk_divider("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6); | |
746 | clks[IMX7D_GPT1_ROOT_DIV] = imx_clk_divider("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6); | |
747 | clks[IMX7D_GPT2_ROOT_DIV] = imx_clk_divider("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6); | |
748 | clks[IMX7D_GPT3_ROOT_DIV] = imx_clk_divider("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6); | |
749 | clks[IMX7D_GPT4_ROOT_DIV] = imx_clk_divider("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6); | |
750 | clks[IMX7D_TRACE_ROOT_DIV] = imx_clk_divider("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6); | |
751 | clks[IMX7D_WDOG_ROOT_DIV] = imx_clk_divider("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6); | |
752 | clks[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_divider("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6); | |
753 | clks[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_divider("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6); | |
754 | clks[IMX7D_WRCLK_ROOT_DIV] = imx_clk_divider("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6); | |
755 | clks[IMX7D_CLKO1_ROOT_DIV] = imx_clk_divider("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6); | |
756 | clks[IMX7D_CLKO2_ROOT_DIV] = imx_clk_divider("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6); | |
757 | ||
758 | clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate2("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0); | |
759 | clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate2("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0); | |
760 | clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate2("arm_m0_root_clk", "arm_m0_div", base + 0x4020, 0); | |
761 | clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate2("main_axi_root_clk", "axi_post_div", base + 0x4040, 0); | |
762 | clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate2("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); | |
763 | clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate2("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); | |
764 | clks[IMX7D_OCRAM_CLK] = imx_clk_gate2("ocram_clk", "axi_post_div", base + 0x4110, 0); | |
765 | clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate2("ocram_s_clk", "ahb_post_div", base + 0x4120, 0); | |
766 | clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate2("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0); | |
767 | clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate2("ahb_root_clk", "ahb_post_div", base + 0x4200, 0); | |
768 | clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate2("dram_root_clk", "dram_post_div", base + 0x4130, 0); | |
769 | clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate2("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); | |
770 | clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate2("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); | |
771 | clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate2("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); | |
772 | clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate2("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); | |
773 | clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate2("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); | |
774 | clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate2("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0); | |
775 | clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate2("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0); | |
776 | clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate2("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0); | |
777 | clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate2("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0); | |
778 | clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate2("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0); | |
779 | clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate2("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0); | |
780 | clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0); | |
781 | clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0); | |
782 | clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0); | |
783 | clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate2("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0); | |
784 | clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate2("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0); | |
785 | clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0); | |
786 | clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate2("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0); | |
787 | clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0); | |
788 | clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate2("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); | |
789 | clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate2("eim_root_clk", "eim_post_div", base + 0x4160, 0); | |
790 | clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate2("nand_root_clk", "nand_post_div", base + 0x4140, 0); | |
791 | clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate2("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); | |
792 | clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate2("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); | |
793 | clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate2("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); | |
794 | clks[IMX7D_USDHC3_ROOT_CLK] = imx_clk_gate2("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0); | |
795 | clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate2("can1_root_clk", "can1_post_div", base + 0x4740, 0); | |
796 | clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate2("can2_root_clk", "can2_post_div", base + 0x4750, 0); | |
797 | clks[IMX7D_I2C1_ROOT_CLK] = imx_clk_gate2("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0); | |
798 | clks[IMX7D_I2C2_ROOT_CLK] = imx_clk_gate2("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0); | |
799 | clks[IMX7D_I2C3_ROOT_CLK] = imx_clk_gate2("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0); | |
800 | clks[IMX7D_I2C4_ROOT_CLK] = imx_clk_gate2("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0); | |
801 | clks[IMX7D_UART1_ROOT_CLK] = imx_clk_gate2("uart1_root_clk", "uart1_post_div", base + 0x4940, 0); | |
802 | clks[IMX7D_UART2_ROOT_CLK] = imx_clk_gate2("uart2_root_clk", "uart2_post_div", base + 0x4950, 0); | |
803 | clks[IMX7D_UART3_ROOT_CLK] = imx_clk_gate2("uart3_root_clk", "uart3_post_div", base + 0x4960, 0); | |
804 | clks[IMX7D_UART4_ROOT_CLK] = imx_clk_gate2("uart4_root_clk", "uart4_post_div", base + 0x4970, 0); | |
805 | clks[IMX7D_UART5_ROOT_CLK] = imx_clk_gate2("uart5_root_clk", "uart5_post_div", base + 0x4980, 0); | |
806 | clks[IMX7D_UART6_ROOT_CLK] = imx_clk_gate2("uart6_root_clk", "uart6_post_div", base + 0x4990, 0); | |
807 | clks[IMX7D_UART7_ROOT_CLK] = imx_clk_gate2("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0); | |
808 | clks[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_gate2("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0); | |
809 | clks[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_gate2("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0); | |
810 | clks[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_gate2("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0); | |
811 | clks[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_gate2("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0); | |
812 | clks[IMX7D_PWM1_ROOT_CLK] = imx_clk_gate2("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0); | |
813 | clks[IMX7D_PWM2_ROOT_CLK] = imx_clk_gate2("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0); | |
814 | clks[IMX7D_PWM3_ROOT_CLK] = imx_clk_gate2("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0); | |
815 | clks[IMX7D_PWM4_ROOT_CLK] = imx_clk_gate2("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0); | |
816 | clks[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_gate2("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0); | |
817 | clks[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_gate2("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0); | |
818 | clks[IMX7D_SIM1_ROOT_CLK] = imx_clk_gate2("sim1_root_clk", "sim1_post_div", base + 0x4900, 0); | |
819 | clks[IMX7D_SIM2_ROOT_CLK] = imx_clk_gate2("sim2_root_clk", "sim2_post_div", base + 0x4910, 0); | |
820 | clks[IMX7D_GPT1_ROOT_CLK] = imx_clk_gate2("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0); | |
821 | clks[IMX7D_GPT2_ROOT_CLK] = imx_clk_gate2("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0); | |
822 | clks[IMX7D_GPT3_ROOT_CLK] = imx_clk_gate2("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0); | |
823 | clks[IMX7D_GPT4_ROOT_CLK] = imx_clk_gate2("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0); | |
824 | clks[IMX7D_TRACE_ROOT_CLK] = imx_clk_gate2("trace_root_clk", "trace_post_div", base + 0x4300, 0); | |
825 | clks[IMX7D_WDOG1_ROOT_CLK] = imx_clk_gate2("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0); | |
826 | clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate2("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0); | |
827 | clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate2("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0); | |
828 | clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate2("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0); | |
829 | clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate2("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0); | |
830 | clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate2("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0); | |
831 | clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate2("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0); | |
ab4c6a24 | 832 | clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate2("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); |
8f6d8094 FL |
833 | |
834 | clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); | |
835 | ||
fdb868cd BP |
836 | clks[IMX7D_CLK_ARM] = imx_clk_cpu("arm", "arm_a7_root_clk", |
837 | clks[IMX7D_ARM_A7_ROOT_CLK], | |
838 | clks[IMX7D_ARM_A7_ROOT_SRC], | |
839 | clks[IMX7D_PLL_ARM_MAIN_CLK], | |
840 | clks[IMX7D_PLL_SYS_MAIN_CLK]); | |
841 | ||
31cbb57d | 842 | imx_check_clocks(clks, ARRAY_SIZE(clks)); |
8f6d8094 FL |
843 | |
844 | clk_data.clks = clks; | |
845 | clk_data.clk_num = ARRAY_SIZE(clks); | |
846 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
847 | ||
848 | /* TO BE FIXED LATER | |
849 | * Enable all clock to bring up imx7, otherwise system will be halt and block | |
850 | * the other part upstream Because imx7d clock design changed, clock framework | |
851 | * need do a little modify. | |
852 | * Dong Aisheng is working on this. After that, this part need be changed. | |
853 | */ | |
854 | for (i = 0; i < IMX7D_CLK_END; i++) | |
855 | clk_prepare_enable(clks[i]); | |
856 | ||
857 | /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ | |
858 | clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); | |
859 | ||
860 | /* | |
861 | * init enet clock source: | |
862 | * AXI clock source is 250MHz | |
863 | * Phy refrence clock is 25MHz | |
864 | * 1588 time clock source is 100MHz | |
865 | */ | |
866 | clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]); | |
867 | clk_set_parent(clks[IMX7D_ENET_PHY_REF_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_25M_CLK]); | |
868 | clk_set_parent(clks[IMX7D_ENET1_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); | |
869 | clk_set_parent(clks[IMX7D_ENET2_TIME_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_100M_CLK]); | |
870 | ||
871 | /* set uart module clock's parent clock source that must be great then 80MHz */ | |
872 | clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); | |
873 | ||
1b9af68f LS |
874 | imx_register_uart_clocks(uart_clks); |
875 | ||
8f6d8094 FL |
876 | } |
877 | CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); |