[deliverable/linux.git] / drivers / clk / mmp / clk-mmp2.c

/*
 * mmp2 clock framework source file
 *
 * Copyright (C) 2012 Marvell
 * Chao Xie <xiechao.mail@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/err.h>

#include "clk.h"

#define APBC_RTC	0x0
#define APBC_TWSI0	0x4
#define APBC_TWSI1	0x8
#define APBC_TWSI2	0xc
#define APBC_TWSI3	0x10
#define APBC_TWSI4	0x7c
#define APBC_TWSI5	0x80
#define APBC_KPC	0x18
#define APBC_UART0	0x2c
#define APBC_UART1	0x30
#define APBC_UART2	0x34
#define APBC_UART3	0x88
#define APBC_GPIO	0x38
#define APBC_PWM0	0x3c
#define APBC_PWM1	0x40
#define APBC_PWM2	0x44
#define APBC_PWM3	0x48
#define APBC_SSP0	0x50
#define APBC_SSP1	0x54
#define APBC_SSP2	0x58
#define APBC_SSP3	0x5c
#define APMU_SDH0	0x54
#define APMU_SDH1	0x58
#define APMU_SDH2	0xe8
#define APMU_SDH3	0xec
#define APMU_USB	0x5c
#define APMU_DISP0	0x4c
#define APMU_DISP1	0x110
#define APMU_CCIC0	0x50
#define APMU_CCIC1	0xf4
#define MPMU_UART_PLL	0x14

static DEFINE_SPINLOCK(clk_lock);

static struct mmp_clk_factor_masks uart_factor_masks = {
	.factor = 2,
	.num_mask = 0x1fff,
	.den_mask = 0x1fff,
	.num_shift = 16,
	.den_shift = 0,
};

static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
	{.num = 8125, .den = 1536},	/*14.745MHZ */
	{.num = 3521, .den = 689},	/*19.23MHZ */
};

static const char *uart_parent[] = {"uart_pll", "vctcxo"};
static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};

void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
			  phys_addr_t apbc_phys)
{
	struct clk *clk;
	struct clk *vctcxo;
	void __iomem *mpmu_base;
	void __iomem *apmu_base;
	void __iomem *apbc_base;

	mpmu_base = ioremap(mpmu_phys, SZ_4K);
	if (mpmu_base == NULL) {
		pr_err("error to ioremap MPMU base\n");
		return;
	}

	apmu_base = ioremap(apmu_phys, SZ_4K);
	if (apmu_base == NULL) {
		pr_err("error to ioremap APMU base\n");
		return;
	}

	apbc_base = ioremap(apbc_phys, SZ_4K);
	if (apbc_base == NULL) {
		pr_err("error to ioremap APBC base\n");
		return;
	}

	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
	clk_register_clkdev(clk, "clk32", NULL);

	vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
				26000000);
	clk_register_clkdev(vctcxo, "vctcxo", NULL);

	clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
				800000000);
	clk_register_clkdev(clk, "pll1", NULL);

	clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
				480000000);
	clk_register_clkdev(clk, "usb_pll", NULL);

	clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
				960000000);
	clk_register_clkdev(clk, "pll2", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_2", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_4", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_8", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_16", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
				CLK_SET_RATE_PARENT, 1, 5);
	clk_register_clkdev(clk, "pll1_20", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
				CLK_SET_RATE_PARENT, 1, 3);
	clk_register_clkdev(clk, "pll1_3", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_6", NULL);

	clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll1_12", NULL);

	clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll2_2", NULL);

	clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll2_4", NULL);

	clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll2_8", NULL);

	clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll2_16", NULL);

	clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
				CLK_SET_RATE_PARENT, 1, 3);
	clk_register_clkdev(clk, "pll2_3", NULL);

	clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll2_6", NULL);

	clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "pll2_12", NULL);

	clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "vctcxo_2", NULL);

	clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
				CLK_SET_RATE_PARENT, 1, 2);
	clk_register_clkdev(clk, "vctcxo_4", NULL);

	clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
				mpmu_base + MPMU_UART_PLL,
				&uart_factor_masks, uart_factor_tbl,
				ARRAY_SIZE(uart_factor_tbl), &clk_lock);
	clk_set_rate(clk, 14745600);
	clk_register_clkdev(clk, "uart_pll", NULL);

	clk = mmp_clk_register_apbc("twsi0", "vctcxo",
				apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");

	clk = mmp_clk_register_apbc("twsi1", "vctcxo",
				apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");

	clk = mmp_clk_register_apbc("twsi2", "vctcxo",
				apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");

	clk = mmp_clk_register_apbc("twsi3", "vctcxo",
				apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");

	clk = mmp_clk_register_apbc("twsi4", "vctcxo",
				apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");

	clk = mmp_clk_register_apbc("twsi5", "vctcxo",
				apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");

	clk = mmp_clk_register_apbc("gpio", "vctcxo",
				apbc_base + APBC_GPIO, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp2-gpio");

	clk = mmp_clk_register_apbc("kpc", "clk32",
				apbc_base + APBC_KPC, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa27x-keypad");

	clk = mmp_clk_register_apbc("rtc", "clk32",
				apbc_base + APBC_RTC, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-rtc");

	clk = mmp_clk_register_apbc("pwm0", "vctcxo",
				apbc_base + APBC_PWM0, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp2-pwm.0");

	clk = mmp_clk_register_apbc("pwm1", "vctcxo",
				apbc_base + APBC_PWM1, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp2-pwm.1");

	clk = mmp_clk_register_apbc("pwm2", "vctcxo",
				apbc_base + APBC_PWM2, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp2-pwm.2");

	clk = mmp_clk_register_apbc("pwm3", "vctcxo",
				apbc_base + APBC_PWM3, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp2-pwm.3");

	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
				ARRAY_SIZE(uart_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
	clk_set_parent(clk, vctcxo);
	clk_register_clkdev(clk, "uart_mux.0", NULL);

	clk = mmp_clk_register_apbc("uart0", "uart0_mux",
				apbc_base + APBC_UART0, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");

	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
				ARRAY_SIZE(uart_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
	clk_set_parent(clk, vctcxo);
	clk_register_clkdev(clk, "uart_mux.1", NULL);

	clk = mmp_clk_register_apbc("uart1", "uart1_mux",
				apbc_base + APBC_UART1, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");

	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
				ARRAY_SIZE(uart_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
	clk_set_parent(clk, vctcxo);
	clk_register_clkdev(clk, "uart_mux.2", NULL);

	clk = mmp_clk_register_apbc("uart2", "uart2_mux",
				apbc_base + APBC_UART2, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");

	clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
				ARRAY_SIZE(uart_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
	clk_set_parent(clk, vctcxo);
	clk_register_clkdev(clk, "uart_mux.3", NULL);

	clk = mmp_clk_register_apbc("uart3", "uart3_mux",
				apbc_base + APBC_UART3, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");

	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
				ARRAY_SIZE(ssp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
	clk_register_clkdev(clk, "uart_mux.0", NULL);

	clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
				apbc_base + APBC_SSP0, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-ssp.0");

	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
				ARRAY_SIZE(ssp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
	clk_register_clkdev(clk, "ssp_mux.1", NULL);

	clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
				apbc_base + APBC_SSP1, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-ssp.1");

	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
				ARRAY_SIZE(ssp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
	clk_register_clkdev(clk, "ssp_mux.2", NULL);

	clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
				apbc_base + APBC_SSP2, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-ssp.2");

	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
				ARRAY_SIZE(ssp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
	clk_register_clkdev(clk, "ssp_mux.3", NULL);

	clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
				apbc_base + APBC_SSP3, 10, 0, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-ssp.3");

	clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
				ARRAY_SIZE(sdh_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
	clk_register_clkdev(clk, "sdh_mux", NULL);

	clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
				CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
				10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	clk_register_clkdev(clk, "sdh_div", NULL);

	clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
				0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");

	clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
				0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");

	clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
				0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");

	clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
				0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");

	clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
				0x9, &clk_lock);
	clk_register_clkdev(clk, "usb_clk", NULL);

	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
				ARRAY_SIZE(disp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
	clk_register_clkdev(clk, "disp_mux.0", NULL);

	clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	clk_register_clkdev(clk, "disp_div.0", NULL);

	clk = mmp_clk_register_apmu("disp0", "disp0_div",
				apmu_base + APMU_DISP0, 0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-disp.0");

	clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
				apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
	clk_register_clkdev(clk, "disp_sphy_div.0", NULL);

	clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
				apmu_base + APMU_DISP0, 0x1024, &clk_lock);
	clk_register_clkdev(clk, "disp_sphy.0", NULL);

	clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
				ARRAY_SIZE(disp_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
	clk_register_clkdev(clk, "disp_mux.1", NULL);

	clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
				CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
				8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	clk_register_clkdev(clk, "disp_div.1", NULL);

	clk = mmp_clk_register_apmu("disp1", "disp1_div",
				apmu_base + APMU_DISP1, 0x1b, &clk_lock);
	clk_register_clkdev(clk, NULL, "mmp-disp.1");

	clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
				apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
	clk_register_clkdev(clk, "ccic_arbiter", NULL);

	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
				ARRAY_SIZE(ccic_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
	clk_register_clkdev(clk, "ccic_mux.0", NULL);

	clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
				17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	clk_register_clkdev(clk, "ccic_div.0", NULL);

	clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
				apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");

	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
				apmu_base + APMU_CCIC0, 0x24, &clk_lock);
	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");

	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
				10, 5, 0, &clk_lock);
	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");

	clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
				apmu_base + APMU_CCIC0, 0x300, &clk_lock);
	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");

	clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
				ARRAY_SIZE(ccic_parent),
				CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
				apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
	clk_register_clkdev(clk, "ccic_mux.1", NULL);

	clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
				16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	clk_register_clkdev(clk, "ccic_div.1", NULL);

	clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
				apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
	clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");

	clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
				apmu_base + APMU_CCIC1, 0x24, &clk_lock);
	clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");

	clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
				CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
				10, 5, 0, &clk_lock);
	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");

	clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
				apmu_base + APMU_CCIC1, 0x300, &clk_lock);
	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
}
Commit	Line	Data
4c5bca34 CX	1	/*
	2	* mmp2 clock framework source file
	3	*
	4	* Copyright (C) 2012 Marvell
	5	* Chao Xie <xiechao.mail@gmail.com>
	6	*
	7	* This file is licensed under the terms of the GNU General Public
	8	* License version 2. This program is licensed "as is" without any
	9	* warranty of any kind, whether express or implied.
	10	*/
	11
990f2f22	12	#include <linux/clk.h>
4c5bca34 CX	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/io.h>
	17	#include <linux/delay.h>
	18	#include <linux/err.h>
	19
4c5bca34 CX	20	#include "clk.h"
	21
	22	#define APBC_RTC 0x0
	23	#define APBC_TWSI0 0x4
	24	#define APBC_TWSI1 0x8
	25	#define APBC_TWSI2 0xc
	26	#define APBC_TWSI3 0x10
	27	#define APBC_TWSI4 0x7c
	28	#define APBC_TWSI5 0x80
	29	#define APBC_KPC 0x18
	30	#define APBC_UART0 0x2c
	31	#define APBC_UART1 0x30
	32	#define APBC_UART2 0x34
	33	#define APBC_UART3 0x88
	34	#define APBC_GPIO 0x38
	35	#define APBC_PWM0 0x3c
	36	#define APBC_PWM1 0x40
	37	#define APBC_PWM2 0x44
	38	#define APBC_PWM3 0x48
	39	#define APBC_SSP0 0x50
	40	#define APBC_SSP1 0x54
	41	#define APBC_SSP2 0x58
	42	#define APBC_SSP3 0x5c
	43	#define APMU_SDH0 0x54
	44	#define APMU_SDH1 0x58
	45	#define APMU_SDH2 0xe8
	46	#define APMU_SDH3 0xec
	47	#define APMU_USB 0x5c
	48	#define APMU_DISP0 0x4c
	49	#define APMU_DISP1 0x110
	50	#define APMU_CCIC0 0x50
	51	#define APMU_CCIC1 0xf4
	52	#define MPMU_UART_PLL 0x14
	53
	54	static DEFINE_SPINLOCK(clk_lock);
	55
2bd1e256	56	static struct mmp_clk_factor_masks uart_factor_masks = {
4c5bca34 CX	57	.factor = 2,
	58	.num_mask = 0x1fff,
	59	.den_mask = 0x1fff,
	60	.num_shift = 16,
	61	.den_shift = 0,
	62	};
	63
2bd1e256	64	static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
6644fddf	65	{.num = 8125, .den = 1536}, /14.745MHZ /
4c5bca34	66	{.num = 3521, .den = 689}, /19.23MHZ /
4c5bca34 CX	67	};
	68
	69	static const char *uart_parent[] = {"uart_pll", "vctcxo"};
	70	static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
	71	static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
	72	static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
	73	static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
	74
990f2f22 AB	75	void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
990f2f22 AB	76	phys_addr_t apbc_phys)
4c5bca34 CX	77	{
	78	struct clk *clk;
	79	struct clk *vctcxo;
	80	void __iomem *mpmu_base;
	81	void __iomem *apmu_base;
	82	void __iomem *apbc_base;
	83
990f2f22	84	mpmu_base = ioremap(mpmu_phys, SZ_4K);
4c5bca34 CX	85	if (mpmu_base == NULL) {
	86	pr_err("error to ioremap MPMU base\n");
	87	return;
	88	}
	89
990f2f22	90	apmu_base = ioremap(apmu_phys, SZ_4K);
4c5bca34 CX	91	if (apmu_base == NULL) {
	92	pr_err("error to ioremap APMU base\n");
	93	return;
	94	}
	95
990f2f22	96	apbc_base = ioremap(apbc_phys, SZ_4K);
4c5bca34 CX	97	if (apbc_base == NULL) {
	98	pr_err("error to ioremap APBC base\n");
	99	return;
	100	}
	101
	102	clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
	103	clk_register_clkdev(clk, "clk32", NULL);
	104
	105	vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
	106	26000000);
	107	clk_register_clkdev(vctcxo, "vctcxo", NULL);
	108
	109	clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
	110	800000000);
	111	clk_register_clkdev(clk, "pll1", NULL);
	112
	113	clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
	114	480000000);
	115	clk_register_clkdev(clk, "usb_pll", NULL);
	116
	117	clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
	118	960000000);
	119	clk_register_clkdev(clk, "pll2", NULL);
	120
	121	clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
	122	CLK_SET_RATE_PARENT, 1, 2);
	123	clk_register_clkdev(clk, "pll1_2", NULL);
	124
	125	clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
	126	CLK_SET_RATE_PARENT, 1, 2);
	127	clk_register_clkdev(clk, "pll1_4", NULL);
	128
	129	clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
	130	CLK_SET_RATE_PARENT, 1, 2);
	131	clk_register_clkdev(clk, "pll1_8", NULL);
	132
	133	clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
	134	CLK_SET_RATE_PARENT, 1, 2);
	135	clk_register_clkdev(clk, "pll1_16", NULL);
	136
	137	clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
	138	CLK_SET_RATE_PARENT, 1, 5);
	139	clk_register_clkdev(clk, "pll1_20", NULL);
	140
	141	clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
	142	CLK_SET_RATE_PARENT, 1, 3);
	143	clk_register_clkdev(clk, "pll1_3", NULL);
	144
	145	clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
	146	CLK_SET_RATE_PARENT, 1, 2);
	147	clk_register_clkdev(clk, "pll1_6", NULL);
	148
	149	clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
	150	CLK_SET_RATE_PARENT, 1, 2);
	151	clk_register_clkdev(clk, "pll1_12", NULL);
	152
	153	clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
	154	CLK_SET_RATE_PARENT, 1, 2);
	155	clk_register_clkdev(clk, "pll2_2", NULL);
	156
	157	clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
	158	CLK_SET_RATE_PARENT, 1, 2);
	159	clk_register_clkdev(clk, "pll2_4", NULL);
	160
161	clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
162	CLK_SET_RATE_PARENT, 1, 2);
163	clk_register_clkdev(clk, "pll2_8", NULL);
164
165	clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
166	CLK_SET_RATE_PARENT, 1, 2);
167	clk_register_clkdev(clk, "pll2_16", NULL);
168
169	clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
170	CLK_SET_RATE_PARENT, 1, 3);
171	clk_register_clkdev(clk, "pll2_3", NULL);
172
173	clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
174	CLK_SET_RATE_PARENT, 1, 2);
175	clk_register_clkdev(clk, "pll2_6", NULL);
176
177	clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
178	CLK_SET_RATE_PARENT, 1, 2);
179	clk_register_clkdev(clk, "pll2_12", NULL);
180
181	clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
182	CLK_SET_RATE_PARENT, 1, 2);
183	clk_register_clkdev(clk, "vctcxo_2", NULL);
184
185	clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
186	CLK_SET_RATE_PARENT, 1, 2);
187	clk_register_clkdev(clk, "vctcxo_4", NULL);
188
189	clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
190	mpmu_base + MPMU_UART_PLL,
191	&uart_factor_masks, uart_factor_tbl,
61256133	192	ARRAY_SIZE(uart_factor_tbl), &clk_lock);
4c5bca34 CX	193	clk_set_rate(clk, 14745600);
	194	clk_register_clkdev(clk, "uart_pll", NULL);
	195
	196	clk = mmp_clk_register_apbc("twsi0", "vctcxo",
	197	apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
	198	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
	199
	200	clk = mmp_clk_register_apbc("twsi1", "vctcxo",
	201	apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
	202	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
	203
	204	clk = mmp_clk_register_apbc("twsi2", "vctcxo",
	205	apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
	206	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
	207
	208	clk = mmp_clk_register_apbc("twsi3", "vctcxo",
	209	apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
	210	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
	211
	212	clk = mmp_clk_register_apbc("twsi4", "vctcxo",
	213	apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
	214	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
	215
	216	clk = mmp_clk_register_apbc("twsi5", "vctcxo",
	217	apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
	218	clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
	219
	220	clk = mmp_clk_register_apbc("gpio", "vctcxo",
	221	apbc_base + APBC_GPIO, 10, 0, &clk_lock);
2cab0292	222	clk_register_clkdev(clk, NULL, "mmp2-gpio");
4c5bca34 CX	223
	224	clk = mmp_clk_register_apbc("kpc", "clk32",
	225	apbc_base + APBC_KPC, 10, 0, &clk_lock);
	226	clk_register_clkdev(clk, NULL, "pxa27x-keypad");
	227
	228	clk = mmp_clk_register_apbc("rtc", "clk32",
	229	apbc_base + APBC_RTC, 10, 0, &clk_lock);
	230	clk_register_clkdev(clk, NULL, "mmp-rtc");
	231
	232	clk = mmp_clk_register_apbc("pwm0", "vctcxo",
	233	apbc_base + APBC_PWM0, 10, 0, &clk_lock);
	234	clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
	235
	236	clk = mmp_clk_register_apbc("pwm1", "vctcxo",
	237	apbc_base + APBC_PWM1, 10, 0, &clk_lock);
	238	clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
	239
	240	clk = mmp_clk_register_apbc("pwm2", "vctcxo",
	241	apbc_base + APBC_PWM2, 10, 0, &clk_lock);
	242	clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
	243
	244	clk = mmp_clk_register_apbc("pwm3", "vctcxo",
	245	apbc_base + APBC_PWM3, 10, 0, &clk_lock);
	246	clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
	247
	248	clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
819c1de3 JH	249	ARRAY_SIZE(uart_parent),
819c1de3 JH	250	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	251	apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
	252	clk_set_parent(clk, vctcxo);
	253	clk_register_clkdev(clk, "uart_mux.0", NULL);
	254
	255	clk = mmp_clk_register_apbc("uart0", "uart0_mux",
	256	apbc_base + APBC_UART0, 10, 0, &clk_lock);
	257	clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
	258
	259	clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
819c1de3 JH	260	ARRAY_SIZE(uart_parent),
819c1de3 JH	261	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	262	apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
	263	clk_set_parent(clk, vctcxo);
	264	clk_register_clkdev(clk, "uart_mux.1", NULL);
	265
	266	clk = mmp_clk_register_apbc("uart1", "uart1_mux",
	267	apbc_base + APBC_UART1, 10, 0, &clk_lock);
	268	clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
	269
	270	clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
819c1de3 JH	271	ARRAY_SIZE(uart_parent),
819c1de3 JH	272	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	273	apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
	274	clk_set_parent(clk, vctcxo);
	275	clk_register_clkdev(clk, "uart_mux.2", NULL);
	276
	277	clk = mmp_clk_register_apbc("uart2", "uart2_mux",
	278	apbc_base + APBC_UART2, 10, 0, &clk_lock);
	279	clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
	280
	281	clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
819c1de3 JH	282	ARRAY_SIZE(uart_parent),
819c1de3 JH	283	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	284	apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
	285	clk_set_parent(clk, vctcxo);
	286	clk_register_clkdev(clk, "uart_mux.3", NULL);
	287
	288	clk = mmp_clk_register_apbc("uart3", "uart3_mux",
	289	apbc_base + APBC_UART3, 10, 0, &clk_lock);
	290	clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
	291
	292	clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
819c1de3 JH	293	ARRAY_SIZE(ssp_parent),
819c1de3 JH	294	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	295	apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
	296	clk_register_clkdev(clk, "uart_mux.0", NULL);
	297
	298	clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
	299	apbc_base + APBC_SSP0, 10, 0, &clk_lock);
	300	clk_register_clkdev(clk, NULL, "mmp-ssp.0");
	301
	302	clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
819c1de3 JH	303	ARRAY_SIZE(ssp_parent),
819c1de3 JH	304	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	305	apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
	306	clk_register_clkdev(clk, "ssp_mux.1", NULL);
	307
	308	clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
	309	apbc_base + APBC_SSP1, 10, 0, &clk_lock);
	310	clk_register_clkdev(clk, NULL, "mmp-ssp.1");
	311
	312	clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
819c1de3 JH	313	ARRAY_SIZE(ssp_parent),
819c1de3 JH	314	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	315	apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
	316	clk_register_clkdev(clk, "ssp_mux.2", NULL);
	317
	318	clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
	319	apbc_base + APBC_SSP2, 10, 0, &clk_lock);
	320	clk_register_clkdev(clk, NULL, "mmp-ssp.2");
	321
	322	clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
819c1de3 JH	323	ARRAY_SIZE(ssp_parent),
819c1de3 JH	324	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	325	apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
	326	clk_register_clkdev(clk, "ssp_mux.3", NULL);
	327
	328	clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
	329	apbc_base + APBC_SSP3, 10, 0, &clk_lock);
	330	clk_register_clkdev(clk, NULL, "mmp-ssp.3");
	331
	332	clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
819c1de3 JH	333	ARRAY_SIZE(sdh_parent),
819c1de3 JH	334	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	335	apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
	336	clk_register_clkdev(clk, "sdh_mux", NULL);
	337
	338	clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
	339	CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
	340	10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	341	clk_register_clkdev(clk, "sdh_div", NULL);
	342
	343	clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
	344	0x1b, &clk_lock);
	345	clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
	346
	347	clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
	348	0x1b, &clk_lock);
	349	clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
	350
	351	clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
	352	0x1b, &clk_lock);
	353	clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
	354
	355	clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
	356	0x1b, &clk_lock);
	357	clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
	358
	359	clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
	360	0x9, &clk_lock);
	361	clk_register_clkdev(clk, "usb_clk", NULL);
	362
	363	clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
819c1de3 JH	364	ARRAY_SIZE(disp_parent),
819c1de3 JH	365	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	366	apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
	367	clk_register_clkdev(clk, "disp_mux.0", NULL);
	368
	369	clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
	370	CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
	371	8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	372	clk_register_clkdev(clk, "disp_div.0", NULL);
	373
	374	clk = mmp_clk_register_apmu("disp0", "disp0_div",
	375	apmu_base + APMU_DISP0, 0x1b, &clk_lock);
	376	clk_register_clkdev(clk, NULL, "mmp-disp.0");
	377
	378	clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
	379	apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
	380	clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
	381
	382	clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
	383	apmu_base + APMU_DISP0, 0x1024, &clk_lock);
	384	clk_register_clkdev(clk, "disp_sphy.0", NULL);
	385
	386	clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
819c1de3 JH	387	ARRAY_SIZE(disp_parent),
819c1de3 JH	388	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	389	apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
	390	clk_register_clkdev(clk, "disp_mux.1", NULL);
	391
	392	clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
	393	CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
	394	8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	395	clk_register_clkdev(clk, "disp_div.1", NULL);
	396
	397	clk = mmp_clk_register_apmu("disp1", "disp1_div",
	398	apmu_base + APMU_DISP1, 0x1b, &clk_lock);
	399	clk_register_clkdev(clk, NULL, "mmp-disp.1");
	400
	401	clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
	402	apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
	403	clk_register_clkdev(clk, "ccic_arbiter", NULL);
	404
	405	clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
819c1de3 JH	406	ARRAY_SIZE(ccic_parent),
819c1de3 JH	407	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	408	apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
	409	clk_register_clkdev(clk, "ccic_mux.0", NULL);
	410
	411	clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
	412	CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
	413	17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	414	clk_register_clkdev(clk, "ccic_div.0", NULL);
	415
	416	clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
	417	apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
	418	clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
	419
	420	clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
	421	apmu_base + APMU_CCIC0, 0x24, &clk_lock);
	422	clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
	423
	424	clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
	425	CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
	426	10, 5, 0, &clk_lock);
	427	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
	428
	429	clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
	430	apmu_base + APMU_CCIC0, 0x300, &clk_lock);
	431	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
	432
	433	clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
819c1de3 JH	434	ARRAY_SIZE(ccic_parent),
819c1de3 JH	435	CLK_SET_RATE_PARENT \| CLK_SET_RATE_NO_REPARENT,
4c5bca34 CX	436	apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
	437	clk_register_clkdev(clk, "ccic_mux.1", NULL);
	438
	439	clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
	440	CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
	441	16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
	442	clk_register_clkdev(clk, "ccic_div.1", NULL);
	443
	444	clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
	445	apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
	446	clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
	447
	448	clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
	449	apmu_base + APMU_CCIC1, 0x24, &clk_lock);
	450	clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
	451
	452	clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
	453	CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
	454	10, 5, 0, &clk_lock);
	455	clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
	456
	457	clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
	458	apmu_base + APMU_CCIC1, 0x300, &clk_lock);
	459	clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
	460	}