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84a62e6e CX |
1 | /* |
2 | * pxa910 clock framework source file | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * Chao Xie <xiechao.mail@gmail.com> | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/err.h> | |
18 | ||
19 | #include <mach/addr-map.h> | |
20 | ||
21 | #include "clk.h" | |
22 | ||
23 | #define APBC_RTC 0x28 | |
24 | #define APBC_TWSI0 0x2c | |
25 | #define APBC_KPC 0x18 | |
26 | #define APBC_UART0 0x0 | |
27 | #define APBC_UART1 0x4 | |
28 | #define APBC_GPIO 0x8 | |
29 | #define APBC_PWM0 0xc | |
30 | #define APBC_PWM1 0x10 | |
31 | #define APBC_PWM2 0x14 | |
32 | #define APBC_PWM3 0x18 | |
33 | #define APBC_SSP0 0x1c | |
34 | #define APBC_SSP1 0x20 | |
35 | #define APBC_SSP2 0x4c | |
36 | #define APBCP_TWSI1 0x28 | |
37 | #define APBCP_UART2 0x1c | |
38 | #define APMU_SDH0 0x54 | |
39 | #define APMU_SDH1 0x58 | |
40 | #define APMU_USB 0x5c | |
41 | #define APMU_DISP0 0x4c | |
42 | #define APMU_CCIC0 0x50 | |
43 | #define APMU_DFC 0x60 | |
44 | #define MPMU_UART_PLL 0x14 | |
45 | ||
46 | static DEFINE_SPINLOCK(clk_lock); | |
47 | ||
48 | static struct clk_factor_masks uart_factor_masks = { | |
49 | .factor = 2, | |
50 | .num_mask = 0x1fff, | |
51 | .den_mask = 0x1fff, | |
52 | .num_shift = 16, | |
53 | .den_shift = 0, | |
54 | }; | |
55 | ||
56 | static struct clk_factor_tbl uart_factor_tbl[] = { | |
57 | {.num = 8125, .den = 1536}, /*14.745MHZ */ | |
58 | }; | |
59 | ||
60 | static const char *uart_parent[] = {"pll1_3_16", "uart_pll"}; | |
61 | static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; | |
62 | static const char *sdh_parent[] = {"pll1_12", "pll1_13"}; | |
63 | static const char *disp_parent[] = {"pll1_2", "pll1_12"}; | |
64 | static const char *ccic_parent[] = {"pll1_2", "pll1_12"}; | |
65 | static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"}; | |
66 | ||
67 | void __init pxa910_clk_init(void) | |
68 | { | |
69 | struct clk *clk; | |
70 | struct clk *uart_pll; | |
71 | void __iomem *mpmu_base; | |
72 | void __iomem *apmu_base; | |
73 | void __iomem *apbcp_base; | |
74 | void __iomem *apbc_base; | |
75 | ||
76 | mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K); | |
77 | if (mpmu_base == NULL) { | |
78 | pr_err("error to ioremap MPMU base\n"); | |
79 | return; | |
80 | } | |
81 | ||
82 | apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K); | |
83 | if (apmu_base == NULL) { | |
84 | pr_err("error to ioremap APMU base\n"); | |
85 | return; | |
86 | } | |
87 | ||
88 | apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K); | |
89 | if (apbcp_base == NULL) { | |
90 | pr_err("error to ioremap APBC extension base\n"); | |
91 | return; | |
92 | } | |
93 | ||
94 | apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K); | |
95 | if (apbc_base == NULL) { | |
96 | pr_err("error to ioremap APBC base\n"); | |
97 | return; | |
98 | } | |
99 | ||
100 | clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); | |
101 | clk_register_clkdev(clk, "clk32", NULL); | |
102 | ||
103 | clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, | |
104 | 26000000); | |
105 | clk_register_clkdev(clk, "vctcxo", NULL); | |
106 | ||
107 | clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, | |
108 | 624000000); | |
109 | clk_register_clkdev(clk, "pll1", NULL); | |
110 | ||
111 | clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", | |
112 | CLK_SET_RATE_PARENT, 1, 2); | |
113 | clk_register_clkdev(clk, "pll1_2", NULL); | |
114 | ||
115 | clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", | |
116 | CLK_SET_RATE_PARENT, 1, 2); | |
117 | clk_register_clkdev(clk, "pll1_4", NULL); | |
118 | ||
119 | clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", | |
120 | CLK_SET_RATE_PARENT, 1, 2); | |
121 | clk_register_clkdev(clk, "pll1_8", NULL); | |
122 | ||
123 | clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", | |
124 | CLK_SET_RATE_PARENT, 1, 2); | |
125 | clk_register_clkdev(clk, "pll1_16", NULL); | |
126 | ||
127 | clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", | |
128 | CLK_SET_RATE_PARENT, 1, 3); | |
129 | clk_register_clkdev(clk, "pll1_6", NULL); | |
130 | ||
131 | clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", | |
132 | CLK_SET_RATE_PARENT, 1, 2); | |
133 | clk_register_clkdev(clk, "pll1_12", NULL); | |
134 | ||
135 | clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", | |
136 | CLK_SET_RATE_PARENT, 1, 2); | |
137 | clk_register_clkdev(clk, "pll1_24", NULL); | |
138 | ||
139 | clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", | |
140 | CLK_SET_RATE_PARENT, 1, 2); | |
141 | clk_register_clkdev(clk, "pll1_48", NULL); | |
142 | ||
143 | clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", | |
144 | CLK_SET_RATE_PARENT, 1, 2); | |
145 | clk_register_clkdev(clk, "pll1_96", NULL); | |
146 | ||
147 | clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", | |
148 | CLK_SET_RATE_PARENT, 1, 13); | |
149 | clk_register_clkdev(clk, "pll1_13", NULL); | |
150 | ||
151 | clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", | |
152 | CLK_SET_RATE_PARENT, 2, 3); | |
153 | clk_register_clkdev(clk, "pll1_13_1_5", NULL); | |
154 | ||
155 | clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", | |
156 | CLK_SET_RATE_PARENT, 2, 3); | |
157 | clk_register_clkdev(clk, "pll1_2_1_5", NULL); | |
158 | ||
159 | clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", | |
160 | CLK_SET_RATE_PARENT, 3, 16); | |
161 | clk_register_clkdev(clk, "pll1_3_16", NULL); | |
162 | ||
163 | uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0, | |
164 | mpmu_base + MPMU_UART_PLL, | |
165 | &uart_factor_masks, uart_factor_tbl, | |
166 | ARRAY_SIZE(uart_factor_tbl)); | |
167 | clk_set_rate(uart_pll, 14745600); | |
168 | clk_register_clkdev(uart_pll, "uart_pll", NULL); | |
169 | ||
170 | clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", | |
171 | apbc_base + APBC_TWSI0, 10, 0, &clk_lock); | |
172 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); | |
173 | ||
174 | clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", | |
175 | apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock); | |
176 | clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); | |
177 | ||
178 | clk = mmp_clk_register_apbc("gpio", "vctcxo", | |
179 | apbc_base + APBC_GPIO, 10, 0, &clk_lock); | |
2cab0292 | 180 | clk_register_clkdev(clk, NULL, "mmp-gpio"); |
84a62e6e CX |
181 | |
182 | clk = mmp_clk_register_apbc("kpc", "clk32", | |
183 | apbc_base + APBC_KPC, 10, 0, &clk_lock); | |
184 | clk_register_clkdev(clk, NULL, "pxa27x-keypad"); | |
185 | ||
186 | clk = mmp_clk_register_apbc("rtc", "clk32", | |
187 | apbc_base + APBC_RTC, 10, 0, &clk_lock); | |
188 | clk_register_clkdev(clk, NULL, "sa1100-rtc"); | |
189 | ||
190 | clk = mmp_clk_register_apbc("pwm0", "pll1_48", | |
191 | apbc_base + APBC_PWM0, 10, 0, &clk_lock); | |
192 | clk_register_clkdev(clk, NULL, "pxa910-pwm.0"); | |
193 | ||
194 | clk = mmp_clk_register_apbc("pwm1", "pll1_48", | |
195 | apbc_base + APBC_PWM1, 10, 0, &clk_lock); | |
196 | clk_register_clkdev(clk, NULL, "pxa910-pwm.1"); | |
197 | ||
198 | clk = mmp_clk_register_apbc("pwm2", "pll1_48", | |
199 | apbc_base + APBC_PWM2, 10, 0, &clk_lock); | |
200 | clk_register_clkdev(clk, NULL, "pxa910-pwm.2"); | |
201 | ||
202 | clk = mmp_clk_register_apbc("pwm3", "pll1_48", | |
203 | apbc_base + APBC_PWM3, 10, 0, &clk_lock); | |
204 | clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); | |
205 | ||
206 | clk = clk_register_mux(NULL, "uart0_mux", uart_parent, | |
819c1de3 JH |
207 | ARRAY_SIZE(uart_parent), |
208 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
209 | apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); |
210 | clk_set_parent(clk, uart_pll); | |
211 | clk_register_clkdev(clk, "uart_mux.0", NULL); | |
212 | ||
213 | clk = mmp_clk_register_apbc("uart0", "uart0_mux", | |
214 | apbc_base + APBC_UART0, 10, 0, &clk_lock); | |
215 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); | |
216 | ||
217 | clk = clk_register_mux(NULL, "uart1_mux", uart_parent, | |
819c1de3 JH |
218 | ARRAY_SIZE(uart_parent), |
219 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
220 | apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); |
221 | clk_set_parent(clk, uart_pll); | |
222 | clk_register_clkdev(clk, "uart_mux.1", NULL); | |
223 | ||
224 | clk = mmp_clk_register_apbc("uart1", "uart1_mux", | |
225 | apbc_base + APBC_UART1, 10, 0, &clk_lock); | |
226 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); | |
227 | ||
228 | clk = clk_register_mux(NULL, "uart2_mux", uart_parent, | |
819c1de3 JH |
229 | ARRAY_SIZE(uart_parent), |
230 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
231 | apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); |
232 | clk_set_parent(clk, uart_pll); | |
233 | clk_register_clkdev(clk, "uart_mux.2", NULL); | |
234 | ||
235 | clk = mmp_clk_register_apbc("uart2", "uart2_mux", | |
236 | apbcp_base + APBCP_UART2, 10, 0, &clk_lock); | |
237 | clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); | |
238 | ||
239 | clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, | |
819c1de3 JH |
240 | ARRAY_SIZE(ssp_parent), |
241 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
242 | apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); |
243 | clk_register_clkdev(clk, "uart_mux.0", NULL); | |
244 | ||
245 | clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", | |
246 | apbc_base + APBC_SSP0, 10, 0, &clk_lock); | |
247 | clk_register_clkdev(clk, NULL, "mmp-ssp.0"); | |
248 | ||
249 | clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, | |
819c1de3 JH |
250 | ARRAY_SIZE(ssp_parent), |
251 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
252 | apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); |
253 | clk_register_clkdev(clk, "ssp_mux.1", NULL); | |
254 | ||
255 | clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", | |
256 | apbc_base + APBC_SSP1, 10, 0, &clk_lock); | |
257 | clk_register_clkdev(clk, NULL, "mmp-ssp.1"); | |
258 | ||
259 | clk = mmp_clk_register_apmu("dfc", "pll1_4", | |
260 | apmu_base + APMU_DFC, 0x19b, &clk_lock); | |
261 | clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); | |
262 | ||
263 | clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, | |
819c1de3 JH |
264 | ARRAY_SIZE(sdh_parent), |
265 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
266 | apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); |
267 | clk_register_clkdev(clk, "sdh0_mux", NULL); | |
268 | ||
269 | clk = mmp_clk_register_apmu("sdh0", "sdh_mux", | |
270 | apmu_base + APMU_SDH0, 0x1b, &clk_lock); | |
271 | clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); | |
272 | ||
273 | clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, | |
819c1de3 JH |
274 | ARRAY_SIZE(sdh_parent), |
275 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
276 | apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); |
277 | clk_register_clkdev(clk, "sdh1_mux", NULL); | |
278 | ||
279 | clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", | |
280 | apmu_base + APMU_SDH1, 0x1b, &clk_lock); | |
281 | clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); | |
282 | ||
283 | clk = mmp_clk_register_apmu("usb", "usb_pll", | |
284 | apmu_base + APMU_USB, 0x9, &clk_lock); | |
285 | clk_register_clkdev(clk, "usb_clk", NULL); | |
286 | ||
287 | clk = mmp_clk_register_apmu("sph", "usb_pll", | |
288 | apmu_base + APMU_USB, 0x12, &clk_lock); | |
289 | clk_register_clkdev(clk, "sph_clk", NULL); | |
290 | ||
291 | clk = clk_register_mux(NULL, "disp0_mux", disp_parent, | |
819c1de3 JH |
292 | ARRAY_SIZE(disp_parent), |
293 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
294 | apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); |
295 | clk_register_clkdev(clk, "disp_mux.0", NULL); | |
296 | ||
297 | clk = mmp_clk_register_apmu("disp0", "disp0_mux", | |
298 | apmu_base + APMU_DISP0, 0x1b, &clk_lock); | |
299 | clk_register_clkdev(clk, NULL, "mmp-disp.0"); | |
300 | ||
301 | clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, | |
819c1de3 JH |
302 | ARRAY_SIZE(ccic_parent), |
303 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
84a62e6e CX |
304 | apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); |
305 | clk_register_clkdev(clk, "ccic_mux.0", NULL); | |
306 | ||
307 | clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", | |
308 | apmu_base + APMU_CCIC0, 0x1b, &clk_lock); | |
309 | clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); | |
310 | ||
311 | clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, | |
312 | ARRAY_SIZE(ccic_phy_parent), | |
819c1de3 JH |
313 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
314 | apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); | |
84a62e6e CX |
315 | clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); |
316 | ||
317 | clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", | |
318 | apmu_base + APMU_CCIC0, 0x24, &clk_lock); | |
319 | clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); | |
320 | ||
321 | clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", | |
322 | CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, | |
323 | 10, 5, 0, &clk_lock); | |
324 | clk_register_clkdev(clk, "sphyclk_div", NULL); | |
325 | ||
326 | clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", | |
327 | apmu_base + APMU_CCIC0, 0x300, &clk_lock); | |
328 | clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); | |
329 | } |