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ff261b7f SG |
1 | /* |
2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/clkdev.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/io.h> | |
17 | #include <mach/common.h> | |
18 | #include <mach/mx23.h> | |
19 | #include "clk.h" | |
20 | ||
21 | #define DIGCTRL MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR) | |
22 | #define CLKCTRL MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR) | |
23 | #define PLLCTRL0 (CLKCTRL + 0x0000) | |
24 | #define CPU (CLKCTRL + 0x0020) | |
25 | #define HBUS (CLKCTRL + 0x0030) | |
26 | #define XBUS (CLKCTRL + 0x0040) | |
27 | #define XTAL (CLKCTRL + 0x0050) | |
28 | #define PIX (CLKCTRL + 0x0060) | |
29 | #define SSP (CLKCTRL + 0x0070) | |
30 | #define GPMI (CLKCTRL + 0x0080) | |
31 | #define SPDIF (CLKCTRL + 0x0090) | |
32 | #define EMI (CLKCTRL + 0x00a0) | |
33 | #define SAIF (CLKCTRL + 0x00c0) | |
34 | #define TV (CLKCTRL + 0x00d0) | |
35 | #define ETM (CLKCTRL + 0x00e0) | |
36 | #define FRAC (CLKCTRL + 0x00f0) | |
37 | #define CLKSEQ (CLKCTRL + 0x0110) | |
38 | ||
39 | #define BP_CPU_INTERRUPT_WAIT 12 | |
40 | #define BP_CLKSEQ_BYPASS_SAIF 0 | |
41 | #define BP_CLKSEQ_BYPASS_SSP 5 | |
42 | #define BP_SAIF_DIV_FRAC_EN 16 | |
43 | #define BP_FRAC_IOFRAC 24 | |
44 | ||
45 | static void __init clk_misc_init(void) | |
46 | { | |
47 | u32 val; | |
48 | ||
49 | /* Gate off cpu clock in WFI for power saving */ | |
50 | __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU); | |
51 | ||
52 | /* Clear BYPASS for SAIF */ | |
53 | __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ); | |
54 | ||
55 | /* SAIF has to use frac div for functional operation */ | |
56 | val = readl_relaxed(SAIF); | |
57 | val |= 1 << BP_SAIF_DIV_FRAC_EN; | |
58 | writel_relaxed(val, SAIF); | |
59 | ||
60 | /* | |
61 | * Source ssp clock from ref_io than ref_xtal, | |
62 | * as ref_xtal only provides 24 MHz as maximum. | |
63 | */ | |
64 | __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ); | |
65 | ||
66 | /* | |
67 | * 480 MHz seems too high to be ssp clock source directly, | |
68 | * so set frac to get a 288 MHz ref_io. | |
69 | */ | |
70 | __mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC); | |
71 | __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC); | |
72 | } | |
73 | ||
d03ac61d | 74 | static struct clk_lookup uart_lookups[] = { |
ff261b7f SG |
75 | { .dev_id = "duart", }, |
76 | { .dev_id = "mxs-auart.0", }, | |
77 | { .dev_id = "mxs-auart.1", }, | |
78 | { .dev_id = "8006c000.serial", }, | |
79 | { .dev_id = "8006e000.serial", }, | |
80 | { .dev_id = "80070000.serial", }, | |
81 | }; | |
82 | ||
d03ac61d | 83 | static struct clk_lookup hbus_lookups[] = { |
8c920136 | 84 | { .dev_id = "imx23-dma-apbh", }, |
ff261b7f SG |
85 | { .dev_id = "80004000.dma-apbh", }, |
86 | }; | |
87 | ||
d03ac61d | 88 | static struct clk_lookup xbus_lookups[] = { |
ff261b7f | 89 | { .dev_id = "duart", .con_id = "apb_pclk"}, |
2954ff39 | 90 | { .dev_id = "80070000.serial", .con_id = "apb_pclk"}, |
8c920136 | 91 | { .dev_id = "imx23-dma-apbx", }, |
ff261b7f SG |
92 | { .dev_id = "80024000.dma-apbx", }, |
93 | }; | |
94 | ||
d03ac61d | 95 | static struct clk_lookup ssp_lookups[] = { |
ef9b4d39 SG |
96 | { .dev_id = "imx23-mmc.0", }, |
97 | { .dev_id = "imx23-mmc.1", }, | |
ff261b7f SG |
98 | { .dev_id = "80010000.ssp", }, |
99 | { .dev_id = "80034000.ssp", }, | |
100 | }; | |
101 | ||
d03ac61d | 102 | static struct clk_lookup lcdif_lookups[] = { |
ff261b7f SG |
103 | { .dev_id = "imx23-fb", }, |
104 | { .dev_id = "80030000.lcdif", }, | |
105 | }; | |
106 | ||
d03ac61d | 107 | static struct clk_lookup gpmi_lookups[] = { |
ff261b7f | 108 | { .dev_id = "imx23-gpmi-nand", }, |
8c6facab | 109 | { .dev_id = "8000c000.gpmi-nand", }, |
ff261b7f SG |
110 | }; |
111 | ||
112 | static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; | |
113 | static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; | |
114 | static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; | |
115 | static const char *sel_io[] __initconst = { "ref_io", "ref_xtal", }; | |
116 | static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; | |
117 | static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; | |
118 | ||
119 | enum imx23_clk { | |
120 | ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel, | |
121 | lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll, | |
122 | cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll, | |
123 | emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div, | |
124 | clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif, | |
125 | lcdif, etm, usb, usb_pwr, | |
126 | clk_max | |
127 | }; | |
128 | ||
129 | static struct clk *clks[clk_max]; | |
130 | ||
131 | static enum imx23_clk clks_init_on[] __initdata = { | |
132 | cpu, hbus, xbus, emi, uart, | |
133 | }; | |
134 | ||
135 | int __init mx23_clocks_init(void) | |
136 | { | |
137 | int i; | |
138 | ||
139 | clk_misc_init(); | |
140 | ||
141 | clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); | |
142 | clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); | |
143 | clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); | |
144 | clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); | |
145 | clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); | |
146 | clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); | |
147 | clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); | |
148 | clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); | |
149 | clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); | |
150 | clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io)); | |
151 | clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels)); | |
152 | clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); | |
153 | clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); | |
154 | clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); | |
155 | clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); | |
156 | clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29); | |
157 | clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); | |
158 | clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29); | |
159 | clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29); | |
160 | clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); | |
161 | clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); | |
162 | clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); | |
163 | clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); | |
164 | clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29); | |
165 | clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); | |
166 | clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); | |
167 | clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16); | |
168 | clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4); | |
169 | clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); | |
170 | clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28); | |
171 | clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); | |
172 | clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30); | |
173 | clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); | |
174 | clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31); | |
175 | clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); | |
176 | clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); | |
177 | clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); | |
178 | clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31); | |
179 | clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31); | |
180 | clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); | |
181 | clks[usb] = mxs_clk_gate("usb", "usb_pwr", DIGCTRL, 2); | |
182 | clks[usb_pwr] = clk_register_gate(NULL, "usb_pwr", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock); | |
183 | ||
184 | for (i = 0; i < ARRAY_SIZE(clks); i++) | |
185 | if (IS_ERR(clks[i])) { | |
186 | pr_err("i.MX23 clk %d: register failed with %ld\n", | |
187 | i, PTR_ERR(clks[i])); | |
188 | return PTR_ERR(clks[i]); | |
189 | } | |
190 | ||
191 | clk_register_clkdev(clks[clk32k], NULL, "timrot"); | |
275d5802 | 192 | clk_register_clkdev(clks[pwm], NULL, "80064000.pwm"); |
ff261b7f SG |
193 | clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups)); |
194 | clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups)); | |
195 | clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups)); | |
196 | clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups)); | |
197 | clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups)); | |
198 | clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups)); | |
199 | ||
200 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) | |
201 | clk_prepare_enable(clks[clks_init_on[i]]); | |
202 | ||
50260924 | 203 | mxs_timer_init(MX23_INT_TIMER0); |
ff261b7f SG |
204 | |
205 | return 0; | |
206 | } |