[deliverable/linux.git] / drivers / clk / qcom / common.c

/*
 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/export.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/reset-controller.h>
#include <linux/of.h>

#include "common.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "reset.h"
#include "gdsc.h"

struct qcom_cc {
	struct qcom_reset_controller reset;
	struct clk_onecell_data data;
	struct clk *clks[];
};

const
struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
{
	if (!f)
		return NULL;

	for (; f->freq; f++)
		if (rate <= f->freq)
			return f;

	/* Default to our fastest rate */
	return f - 1;
}
EXPORT_SYMBOL_GPL(qcom_find_freq);

int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
{
	int i, num_parents = clk_hw_get_num_parents(hw);

	for (i = 0; i < num_parents; i++)
		if (src == map[i].src)
			return i;

	return -ENOENT;
}
EXPORT_SYMBOL_GPL(qcom_find_src_index);

struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	void __iomem *base;
	struct resource *res;
	struct device *dev = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return ERR_CAST(base);

	return devm_regmap_init_mmio(dev, base, desc->config);
}
EXPORT_SYMBOL_GPL(qcom_cc_map);

static void qcom_cc_del_clk_provider(void *data)
{
	of_clk_del_provider(data);
}

static void qcom_cc_reset_unregister(void *data)
{
	reset_controller_unregister(data);
}

static void qcom_cc_gdsc_unregister(void *data)
{
	gdsc_unregister(data);
}

/*
 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
 * clock to translate 'path' clk into 'name' clk and regsiter the 'path'
 * clk as a fixed rate clock if it isn't present.
 */
static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
				       const char *name, unsigned long rate,
				       bool add_factor)
{
	struct device_node *node = NULL;
	struct device_node *clocks_node;
	struct clk_fixed_factor *factor;
	struct clk_fixed_rate *fixed;
	struct clk *clk;
	struct clk_init_data init_data = { };

	clocks_node = of_find_node_by_path("/clocks");
	if (clocks_node)
		node = of_find_node_by_name(clocks_node, path);
	of_node_put(clocks_node);

	if (!node) {
		fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
		if (!fixed)
			return -EINVAL;

		fixed->fixed_rate = rate;
		fixed->hw.init = &init_data;

		init_data.name = path;
		init_data.flags = CLK_IS_ROOT;
		init_data.ops = &clk_fixed_rate_ops;

		clk = devm_clk_register(dev, &fixed->hw);
		if (IS_ERR(clk))
			return PTR_ERR(clk);
	}
	of_node_put(node);

	if (add_factor) {
		factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
		if (!factor)
			return -EINVAL;

		factor->mult = factor->div = 1;
		factor->hw.init = &init_data;

		init_data.name = name;
		init_data.parent_names = &path;
		init_data.num_parents = 1;
		init_data.flags = 0;
		init_data.ops = &clk_fixed_factor_ops;

		clk = devm_clk_register(dev, &factor->hw);
		if (IS_ERR(clk))
			return PTR_ERR(clk);
	}

	return 0;
}

int qcom_cc_register_board_clk(struct device *dev, const char *path,
			       const char *name, unsigned long rate)
{
	bool add_factor = true;
	struct device_node *node;

	/* The RPM clock driver will add the factor clock if present */
	if (IS_ENABLED(CONFIG_QCOM_RPMCC)) {
		node = of_find_compatible_node(NULL, NULL, "qcom,rpmcc");
		if (of_device_is_available(node))
			add_factor = false;
		of_node_put(node);
	}

	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);

int qcom_cc_register_sleep_clk(struct device *dev)
{
	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
					   32768, true);
}
EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);

int qcom_cc_really_probe(struct platform_device *pdev,
			 const struct qcom_cc_desc *desc, struct regmap *regmap)
{
	int i, ret;
	struct device *dev = &pdev->dev;
	struct clk *clk;
	struct clk_onecell_data *data;
	struct clk **clks;
	struct qcom_reset_controller *reset;
	struct qcom_cc *cc;
	size_t num_clks = desc->num_clks;
	struct clk_regmap **rclks = desc->clks;

	cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
			  GFP_KERNEL);
	if (!cc)
		return -ENOMEM;

	clks = cc->clks;
	data = &cc->data;
	data->clks = clks;
	data->clk_num = num_clks;

	for (i = 0; i < num_clks; i++) {
		if (!rclks[i]) {
			clks[i] = ERR_PTR(-ENOENT);
			continue;
		}
		clk = devm_clk_register_regmap(dev, rclks[i]);
		if (IS_ERR(clk))
			return PTR_ERR(clk);
		clks[i] = clk;
	}

	ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
	if (ret)
		return ret;

	devm_add_action(dev, qcom_cc_del_clk_provider, pdev->dev.of_node);

	reset = &cc->reset;
	reset->rcdev.of_node = dev->of_node;
	reset->rcdev.ops = &qcom_reset_ops;
	reset->rcdev.owner = dev->driver->owner;
	reset->rcdev.nr_resets = desc->num_resets;
	reset->regmap = regmap;
	reset->reset_map = desc->resets;

	ret = reset_controller_register(&reset->rcdev);
	if (ret)
		return ret;

	devm_add_action(dev, qcom_cc_reset_unregister, &reset->rcdev);

	if (desc->gdscs && desc->num_gdscs) {
		ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs,
				    &reset->rcdev, regmap);
		if (ret)
			return ret;
	}

	devm_add_action(dev, qcom_cc_gdsc_unregister, dev);


	return 0;
}
EXPORT_SYMBOL_GPL(qcom_cc_really_probe);

int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
	struct regmap *regmap;

	regmap = qcom_cc_map(pdev, desc);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	return qcom_cc_really_probe(pdev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
49fc825f SB	1	/*
	2	* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/export.h>
169f05e8	15	#include <linux/module.h>
49fc825f SB	16	#include <linux/regmap.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/clk-provider.h>
	19	#include <linux/reset-controller.h>
ee15faff	20	#include <linux/of.h>
49fc825f SB	21
49fc825f SB	22	#include "common.h"
50c6a503	23	#include "clk-rcg.h"
49fc825f SB	24	#include "clk-regmap.h"
49fc825f SB	25	#include "reset.h"
5e5cc241	26	#include "gdsc.h"
49fc825f SB	27
	28	struct qcom_cc {
	29	struct qcom_reset_controller reset;
	30	struct clk_onecell_data data;
	31	struct clk *clks[];
	32	};
	33
50c6a503 SB	34	const
	35	struct freq_tbl qcom_find_freq(const struct freq_tbl f, unsigned long rate)
	36	{
	37	if (!f)
	38	return NULL;
	39
	40	for (; f->freq; f++)
	41	if (rate <= f->freq)
	42	return f;
	43
	44	/* Default to our fastest rate */
	45	return f - 1;
	46	}
	47	EXPORT_SYMBOL_GPL(qcom_find_freq);
	48
293d2e97 GD	49	int qcom_find_src_index(struct clk_hw hw, const struct parent_map map, u8 src)
293d2e97 GD	50	{
497295af	51	int i, num_parents = clk_hw_get_num_parents(hw);
293d2e97 GD	52
	53	for (i = 0; i < num_parents; i++)
	54	if (src == map[i].src)
	55	return i;
	56
	57	return -ENOENT;
	58	}
	59	EXPORT_SYMBOL_GPL(qcom_find_src_index);
	60
5b6b7490 SB	61	struct regmap *
5b6b7490 SB	62	qcom_cc_map(struct platform_device pdev, const struct qcom_cc_desc desc)
49fc825f SB	63	{
	64	void __iomem *base;
	65	struct resource *res;
5b6b7490 SB	66	struct device *dev = &pdev->dev;
	67
	68	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	69	base = devm_ioremap_resource(dev, res);
	70	if (IS_ERR(base))
	71	return ERR_CAST(base);
	72
	73	return devm_regmap_init_mmio(dev, base, desc->config);
	74	}
	75	EXPORT_SYMBOL_GPL(qcom_cc_map);
	76
94c51f40 SB	77	static void qcom_cc_del_clk_provider(void *data)
	78	{
	79	of_clk_del_provider(data);
	80	}
	81
	82	static void qcom_cc_reset_unregister(void *data)
	83	{
	84	reset_controller_unregister(data);
	85	}
	86
	87	static void qcom_cc_gdsc_unregister(void *data)
	88	{
	89	gdsc_unregister(data);
	90	}
	91
ee15faff SB	92	/*
	93	* Backwards compatibility with old DTs. Register a pass-through factor 1/1
	94	* clock to translate 'path' clk into 'name' clk and regsiter the 'path'
	95	* clk as a fixed rate clock if it isn't present.
	96	*/
	97	static int _qcom_cc_register_board_clk(struct device dev, const char path,
	98	const char *name, unsigned long rate,
	99	bool add_factor)
	100	{
	101	struct device_node *node = NULL;
	102	struct device_node *clocks_node;
	103	struct clk_fixed_factor *factor;
	104	struct clk_fixed_rate *fixed;
	105	struct clk *clk;
	106	struct clk_init_data init_data = { };
	107
	108	clocks_node = of_find_node_by_path("/clocks");
	109	if (clocks_node)
	110	node = of_find_node_by_name(clocks_node, path);
	111	of_node_put(clocks_node);
	112
	113	if (!node) {
	114	fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
	115	if (!fixed)
	116	return -EINVAL;
	117
	118	fixed->fixed_rate = rate;
	119	fixed->hw.init = &init_data;
	120
	121	init_data.name = path;
	122	init_data.flags = CLK_IS_ROOT;
	123	init_data.ops = &clk_fixed_rate_ops;
	124
	125	clk = devm_clk_register(dev, &fixed->hw);
	126	if (IS_ERR(clk))
	127	return PTR_ERR(clk);
	128	}
	129	of_node_put(node);
	130
	131	if (add_factor) {
	132	factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
	133	if (!factor)
	134	return -EINVAL;
	135
	136	factor->mult = factor->div = 1;
	137	factor->hw.init = &init_data;
	138
	139	init_data.name = name;
	140	init_data.parent_names = &path;
	141	init_data.num_parents = 1;
	142	init_data.flags = 0;
	143	init_data.ops = &clk_fixed_factor_ops;
	144
	145	clk = devm_clk_register(dev, &factor->hw);
	146	if (IS_ERR(clk))
	147	return PTR_ERR(clk);
	148	}
	149
	150	return 0;
	151	}
	152
	153	int qcom_cc_register_board_clk(struct device dev, const char path,
	154	const char *name, unsigned long rate)
	155	{
156	bool add_factor = true;
157	struct device_node *node;
158
159	/* The RPM clock driver will add the factor clock if present */
160	if (IS_ENABLED(CONFIG_QCOM_RPMCC)) {
161	node = of_find_compatible_node(NULL, NULL, "qcom,rpmcc");
162	if (of_device_is_available(node))
163	add_factor = false;
164	of_node_put(node);
165	}
166
167	return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
168	}
169	EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
170
171	int qcom_cc_register_sleep_clk(struct device *dev)
172	{
173	return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
174	32768, true);
175	}
176	EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
177
5b6b7490 SB	178	int qcom_cc_really_probe(struct platform_device *pdev,
	179	const struct qcom_cc_desc desc, struct regmap regmap)
	180	{
49fc825f SB	181	int i, ret;
	182	struct device *dev = &pdev->dev;
	183	struct clk *clk;
	184	struct clk_onecell_data *data;
	185	struct clk **clks;
49fc825f SB	186	struct qcom_reset_controller *reset;
	187	struct qcom_cc *cc;
	188	size_t num_clks = desc->num_clks;
	189	struct clk_regmap **rclks = desc->clks;
	190
49fc825f SB	191	cc = devm_kzalloc(dev, sizeof(cc) + sizeof(clks) * num_clks,
	192	GFP_KERNEL);
	193	if (!cc)
	194	return -ENOMEM;
	195
	196	clks = cc->clks;
	197	data = &cc->data;
	198	data->clks = clks;
	199	data->clk_num = num_clks;
	200
	201	for (i = 0; i < num_clks; i++) {
9ec2749b SB	202	if (!rclks[i]) {
9ec2749b SB	203	clks[i] = ERR_PTR(-ENOENT);
49fc825f	204	continue;
9ec2749b	205	}
49fc825f SB	206	clk = devm_clk_register_regmap(dev, rclks[i]);
	207	if (IS_ERR(clk))
	208	return PTR_ERR(clk);
	209	clks[i] = clk;
	210	}
	211
	212	ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
	213	if (ret)
	214	return ret;
	215
94c51f40 SB	216	devm_add_action(dev, qcom_cc_del_clk_provider, pdev->dev.of_node);
94c51f40 SB	217
49fc825f SB	218	reset = &cc->reset;
	219	reset->rcdev.of_node = dev->of_node;
	220	reset->rcdev.ops = &qcom_reset_ops;
	221	reset->rcdev.owner = dev->driver->owner;
	222	reset->rcdev.nr_resets = desc->num_resets;
	223	reset->regmap = regmap;
	224	reset->reset_map = desc->resets;
49fc825f SB	225
	226	ret = reset_controller_register(&reset->rcdev);
	227	if (ret)
94c51f40 SB	228	return ret;
	229
	230	devm_add_action(dev, qcom_cc_reset_unregister, &reset->rcdev);
49fc825f	231
5e5cc241	232	if (desc->gdscs && desc->num_gdscs) {
3c53f5e2 RN	233	ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs,
3c53f5e2 RN	234	&reset->rcdev, regmap);
5e5cc241	235	if (ret)
94c51f40	236	return ret;
5e5cc241 RN	237	}
5e5cc241 RN	238
94c51f40 SB	239	devm_add_action(dev, qcom_cc_gdsc_unregister, dev);
	240
	241
5e5cc241	242	return 0;
49fc825f	243	}
5b6b7490 SB	244	EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
	245
	246	int qcom_cc_probe(struct platform_device pdev, const struct qcom_cc_desc desc)
	247	{
	248	struct regmap *regmap;
	249
	250	regmap = qcom_cc_map(pdev, desc);
	251	if (IS_ERR(regmap))
	252	return PTR_ERR(regmap);
	253
	254	return qcom_cc_really_probe(pdev, desc, regmap);
	255	}
49fc825f SB	256	EXPORT_SYMBOL_GPL(qcom_cc_probe);
49fc825f SB	257
169f05e8	258	MODULE_LICENSE("GPL v2");