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24d8fba4 KG |
1 | /* |
2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/reset-controller.h> | |
24 | ||
25 | #include <dt-bindings/clock/qcom,gcc-ipq806x.h> | |
26 | #include <dt-bindings/reset/qcom,gcc-ipq806x.h> | |
27 | ||
28 | #include "common.h" | |
29 | #include "clk-regmap.h" | |
30 | #include "clk-pll.h" | |
31 | #include "clk-rcg.h" | |
32 | #include "clk-branch.h" | |
33 | #include "reset.h" | |
34 | ||
dc1b3f65 AG |
35 | static struct clk_pll pll0 = { |
36 | .l_reg = 0x30c4, | |
37 | .m_reg = 0x30c8, | |
38 | .n_reg = 0x30cc, | |
39 | .config_reg = 0x30d4, | |
40 | .mode_reg = 0x30c0, | |
41 | .status_reg = 0x30d8, | |
42 | .status_bit = 16, | |
43 | .clkr.hw.init = &(struct clk_init_data){ | |
44 | .name = "pll0", | |
45 | .parent_names = (const char *[]){ "pxo" }, | |
46 | .num_parents = 1, | |
47 | .ops = &clk_pll_ops, | |
48 | }, | |
49 | }; | |
50 | ||
51 | static struct clk_regmap pll0_vote = { | |
52 | .enable_reg = 0x34c0, | |
53 | .enable_mask = BIT(0), | |
54 | .hw.init = &(struct clk_init_data){ | |
55 | .name = "pll0_vote", | |
56 | .parent_names = (const char *[]){ "pll0" }, | |
57 | .num_parents = 1, | |
58 | .ops = &clk_pll_vote_ops, | |
59 | }, | |
60 | }; | |
61 | ||
24d8fba4 KG |
62 | static struct clk_pll pll3 = { |
63 | .l_reg = 0x3164, | |
64 | .m_reg = 0x3168, | |
65 | .n_reg = 0x316c, | |
66 | .config_reg = 0x3174, | |
67 | .mode_reg = 0x3160, | |
68 | .status_reg = 0x3178, | |
69 | .status_bit = 16, | |
70 | .clkr.hw.init = &(struct clk_init_data){ | |
71 | .name = "pll3", | |
72 | .parent_names = (const char *[]){ "pxo" }, | |
73 | .num_parents = 1, | |
74 | .ops = &clk_pll_ops, | |
75 | }, | |
76 | }; | |
77 | ||
c99e515a RN |
78 | static struct clk_regmap pll4_vote = { |
79 | .enable_reg = 0x34c0, | |
80 | .enable_mask = BIT(4), | |
81 | .hw.init = &(struct clk_init_data){ | |
82 | .name = "pll4_vote", | |
83 | .parent_names = (const char *[]){ "pll4" }, | |
84 | .num_parents = 1, | |
85 | .ops = &clk_pll_vote_ops, | |
86 | }, | |
87 | }; | |
88 | ||
24d8fba4 KG |
89 | static struct clk_pll pll8 = { |
90 | .l_reg = 0x3144, | |
91 | .m_reg = 0x3148, | |
92 | .n_reg = 0x314c, | |
93 | .config_reg = 0x3154, | |
94 | .mode_reg = 0x3140, | |
95 | .status_reg = 0x3158, | |
96 | .status_bit = 16, | |
97 | .clkr.hw.init = &(struct clk_init_data){ | |
98 | .name = "pll8", | |
99 | .parent_names = (const char *[]){ "pxo" }, | |
100 | .num_parents = 1, | |
101 | .ops = &clk_pll_ops, | |
102 | }, | |
103 | }; | |
104 | ||
105 | static struct clk_regmap pll8_vote = { | |
106 | .enable_reg = 0x34c0, | |
107 | .enable_mask = BIT(8), | |
108 | .hw.init = &(struct clk_init_data){ | |
109 | .name = "pll8_vote", | |
110 | .parent_names = (const char *[]){ "pll8" }, | |
111 | .num_parents = 1, | |
112 | .ops = &clk_pll_vote_ops, | |
113 | }, | |
114 | }; | |
115 | ||
116 | static struct clk_pll pll14 = { | |
117 | .l_reg = 0x31c4, | |
118 | .m_reg = 0x31c8, | |
119 | .n_reg = 0x31cc, | |
120 | .config_reg = 0x31d4, | |
121 | .mode_reg = 0x31c0, | |
122 | .status_reg = 0x31d8, | |
123 | .status_bit = 16, | |
124 | .clkr.hw.init = &(struct clk_init_data){ | |
125 | .name = "pll14", | |
126 | .parent_names = (const char *[]){ "pxo" }, | |
127 | .num_parents = 1, | |
128 | .ops = &clk_pll_ops, | |
129 | }, | |
130 | }; | |
131 | ||
132 | static struct clk_regmap pll14_vote = { | |
133 | .enable_reg = 0x34c0, | |
134 | .enable_mask = BIT(14), | |
135 | .hw.init = &(struct clk_init_data){ | |
136 | .name = "pll14_vote", | |
137 | .parent_names = (const char *[]){ "pll14" }, | |
138 | .num_parents = 1, | |
139 | .ops = &clk_pll_vote_ops, | |
140 | }, | |
141 | }; | |
142 | ||
293d2e97 GD |
143 | enum { |
144 | P_PXO, | |
145 | P_PLL8, | |
146 | P_PLL3, | |
147 | P_PLL0, | |
148 | P_CXO, | |
149 | }; | |
24d8fba4 | 150 | |
293d2e97 GD |
151 | static const struct parent_map gcc_pxo_pll8_map[] = { |
152 | { P_PXO, 0 }, | |
153 | { P_PLL8, 3 } | |
24d8fba4 KG |
154 | }; |
155 | ||
156 | static const char *gcc_pxo_pll8[] = { | |
157 | "pxo", | |
158 | "pll8_vote", | |
159 | }; | |
160 | ||
293d2e97 GD |
161 | static const struct parent_map gcc_pxo_pll8_cxo_map[] = { |
162 | { P_PXO, 0 }, | |
163 | { P_PLL8, 3 }, | |
164 | { P_CXO, 5 } | |
24d8fba4 KG |
165 | }; |
166 | ||
167 | static const char *gcc_pxo_pll8_cxo[] = { | |
168 | "pxo", | |
169 | "pll8_vote", | |
170 | "cxo", | |
171 | }; | |
172 | ||
293d2e97 GD |
173 | static const struct parent_map gcc_pxo_pll3_map[] = { |
174 | { P_PXO, 0 }, | |
175 | { P_PLL3, 1 } | |
24d8fba4 KG |
176 | }; |
177 | ||
293d2e97 GD |
178 | static const struct parent_map gcc_pxo_pll3_sata_map[] = { |
179 | { P_PXO, 0 }, | |
180 | { P_PLL3, 6 } | |
24d8fba4 KG |
181 | }; |
182 | ||
183 | static const char *gcc_pxo_pll3[] = { | |
184 | "pxo", | |
185 | "pll3", | |
186 | }; | |
187 | ||
293d2e97 GD |
188 | static const struct parent_map gcc_pxo_pll8_pll0[] = { |
189 | { P_PXO, 0 }, | |
190 | { P_PLL8, 3 }, | |
191 | { P_PLL0, 2 } | |
24d8fba4 KG |
192 | }; |
193 | ||
194 | static const char *gcc_pxo_pll8_pll0_map[] = { | |
195 | "pxo", | |
196 | "pll8_vote", | |
dc1b3f65 | 197 | "pll0_vote", |
24d8fba4 KG |
198 | }; |
199 | ||
200 | static struct freq_tbl clk_tbl_gsbi_uart[] = { | |
201 | { 1843200, P_PLL8, 2, 6, 625 }, | |
202 | { 3686400, P_PLL8, 2, 12, 625 }, | |
203 | { 7372800, P_PLL8, 2, 24, 625 }, | |
204 | { 14745600, P_PLL8, 2, 48, 625 }, | |
205 | { 16000000, P_PLL8, 4, 1, 6 }, | |
206 | { 24000000, P_PLL8, 4, 1, 4 }, | |
207 | { 32000000, P_PLL8, 4, 1, 3 }, | |
208 | { 40000000, P_PLL8, 1, 5, 48 }, | |
209 | { 46400000, P_PLL8, 1, 29, 240 }, | |
210 | { 48000000, P_PLL8, 4, 1, 2 }, | |
211 | { 51200000, P_PLL8, 1, 2, 15 }, | |
212 | { 56000000, P_PLL8, 1, 7, 48 }, | |
213 | { 58982400, P_PLL8, 1, 96, 625 }, | |
214 | { 64000000, P_PLL8, 2, 1, 3 }, | |
215 | { } | |
216 | }; | |
217 | ||
218 | static struct clk_rcg gsbi1_uart_src = { | |
219 | .ns_reg = 0x29d4, | |
220 | .md_reg = 0x29d0, | |
221 | .mn = { | |
222 | .mnctr_en_bit = 8, | |
223 | .mnctr_reset_bit = 7, | |
224 | .mnctr_mode_shift = 5, | |
225 | .n_val_shift = 16, | |
226 | .m_val_shift = 16, | |
227 | .width = 16, | |
228 | }, | |
229 | .p = { | |
230 | .pre_div_shift = 3, | |
231 | .pre_div_width = 2, | |
232 | }, | |
233 | .s = { | |
234 | .src_sel_shift = 0, | |
235 | .parent_map = gcc_pxo_pll8_map, | |
236 | }, | |
237 | .freq_tbl = clk_tbl_gsbi_uart, | |
238 | .clkr = { | |
239 | .enable_reg = 0x29d4, | |
240 | .enable_mask = BIT(11), | |
241 | .hw.init = &(struct clk_init_data){ | |
242 | .name = "gsbi1_uart_src", | |
243 | .parent_names = gcc_pxo_pll8, | |
244 | .num_parents = 2, | |
245 | .ops = &clk_rcg_ops, | |
246 | .flags = CLK_SET_PARENT_GATE, | |
247 | }, | |
248 | }, | |
249 | }; | |
250 | ||
251 | static struct clk_branch gsbi1_uart_clk = { | |
252 | .halt_reg = 0x2fcc, | |
253 | .halt_bit = 12, | |
254 | .clkr = { | |
255 | .enable_reg = 0x29d4, | |
256 | .enable_mask = BIT(9), | |
257 | .hw.init = &(struct clk_init_data){ | |
258 | .name = "gsbi1_uart_clk", | |
259 | .parent_names = (const char *[]){ | |
260 | "gsbi1_uart_src", | |
261 | }, | |
262 | .num_parents = 1, | |
263 | .ops = &clk_branch_ops, | |
264 | .flags = CLK_SET_RATE_PARENT, | |
265 | }, | |
266 | }, | |
267 | }; | |
268 | ||
269 | static struct clk_rcg gsbi2_uart_src = { | |
270 | .ns_reg = 0x29f4, | |
271 | .md_reg = 0x29f0, | |
272 | .mn = { | |
273 | .mnctr_en_bit = 8, | |
274 | .mnctr_reset_bit = 7, | |
275 | .mnctr_mode_shift = 5, | |
276 | .n_val_shift = 16, | |
277 | .m_val_shift = 16, | |
278 | .width = 16, | |
279 | }, | |
280 | .p = { | |
281 | .pre_div_shift = 3, | |
282 | .pre_div_width = 2, | |
283 | }, | |
284 | .s = { | |
285 | .src_sel_shift = 0, | |
286 | .parent_map = gcc_pxo_pll8_map, | |
287 | }, | |
288 | .freq_tbl = clk_tbl_gsbi_uart, | |
289 | .clkr = { | |
290 | .enable_reg = 0x29f4, | |
291 | .enable_mask = BIT(11), | |
292 | .hw.init = &(struct clk_init_data){ | |
293 | .name = "gsbi2_uart_src", | |
294 | .parent_names = gcc_pxo_pll8, | |
295 | .num_parents = 2, | |
296 | .ops = &clk_rcg_ops, | |
297 | .flags = CLK_SET_PARENT_GATE, | |
298 | }, | |
299 | }, | |
300 | }; | |
301 | ||
302 | static struct clk_branch gsbi2_uart_clk = { | |
303 | .halt_reg = 0x2fcc, | |
304 | .halt_bit = 8, | |
305 | .clkr = { | |
306 | .enable_reg = 0x29f4, | |
307 | .enable_mask = BIT(9), | |
308 | .hw.init = &(struct clk_init_data){ | |
309 | .name = "gsbi2_uart_clk", | |
310 | .parent_names = (const char *[]){ | |
311 | "gsbi2_uart_src", | |
312 | }, | |
313 | .num_parents = 1, | |
314 | .ops = &clk_branch_ops, | |
315 | .flags = CLK_SET_RATE_PARENT, | |
316 | }, | |
317 | }, | |
318 | }; | |
319 | ||
320 | static struct clk_rcg gsbi4_uart_src = { | |
321 | .ns_reg = 0x2a34, | |
322 | .md_reg = 0x2a30, | |
323 | .mn = { | |
324 | .mnctr_en_bit = 8, | |
325 | .mnctr_reset_bit = 7, | |
326 | .mnctr_mode_shift = 5, | |
327 | .n_val_shift = 16, | |
328 | .m_val_shift = 16, | |
329 | .width = 16, | |
330 | }, | |
331 | .p = { | |
332 | .pre_div_shift = 3, | |
333 | .pre_div_width = 2, | |
334 | }, | |
335 | .s = { | |
336 | .src_sel_shift = 0, | |
337 | .parent_map = gcc_pxo_pll8_map, | |
338 | }, | |
339 | .freq_tbl = clk_tbl_gsbi_uart, | |
340 | .clkr = { | |
341 | .enable_reg = 0x2a34, | |
342 | .enable_mask = BIT(11), | |
343 | .hw.init = &(struct clk_init_data){ | |
344 | .name = "gsbi4_uart_src", | |
345 | .parent_names = gcc_pxo_pll8, | |
346 | .num_parents = 2, | |
347 | .ops = &clk_rcg_ops, | |
348 | .flags = CLK_SET_PARENT_GATE, | |
349 | }, | |
350 | }, | |
351 | }; | |
352 | ||
353 | static struct clk_branch gsbi4_uart_clk = { | |
354 | .halt_reg = 0x2fd0, | |
355 | .halt_bit = 26, | |
356 | .clkr = { | |
357 | .enable_reg = 0x2a34, | |
358 | .enable_mask = BIT(9), | |
359 | .hw.init = &(struct clk_init_data){ | |
360 | .name = "gsbi4_uart_clk", | |
361 | .parent_names = (const char *[]){ | |
362 | "gsbi4_uart_src", | |
363 | }, | |
364 | .num_parents = 1, | |
365 | .ops = &clk_branch_ops, | |
366 | .flags = CLK_SET_RATE_PARENT, | |
367 | }, | |
368 | }, | |
369 | }; | |
370 | ||
371 | static struct clk_rcg gsbi5_uart_src = { | |
372 | .ns_reg = 0x2a54, | |
373 | .md_reg = 0x2a50, | |
374 | .mn = { | |
375 | .mnctr_en_bit = 8, | |
376 | .mnctr_reset_bit = 7, | |
377 | .mnctr_mode_shift = 5, | |
378 | .n_val_shift = 16, | |
379 | .m_val_shift = 16, | |
380 | .width = 16, | |
381 | }, | |
382 | .p = { | |
383 | .pre_div_shift = 3, | |
384 | .pre_div_width = 2, | |
385 | }, | |
386 | .s = { | |
387 | .src_sel_shift = 0, | |
388 | .parent_map = gcc_pxo_pll8_map, | |
389 | }, | |
390 | .freq_tbl = clk_tbl_gsbi_uart, | |
391 | .clkr = { | |
392 | .enable_reg = 0x2a54, | |
393 | .enable_mask = BIT(11), | |
394 | .hw.init = &(struct clk_init_data){ | |
395 | .name = "gsbi5_uart_src", | |
396 | .parent_names = gcc_pxo_pll8, | |
397 | .num_parents = 2, | |
398 | .ops = &clk_rcg_ops, | |
399 | .flags = CLK_SET_PARENT_GATE, | |
400 | }, | |
401 | }, | |
402 | }; | |
403 | ||
404 | static struct clk_branch gsbi5_uart_clk = { | |
405 | .halt_reg = 0x2fd0, | |
406 | .halt_bit = 22, | |
407 | .clkr = { | |
408 | .enable_reg = 0x2a54, | |
409 | .enable_mask = BIT(9), | |
410 | .hw.init = &(struct clk_init_data){ | |
411 | .name = "gsbi5_uart_clk", | |
412 | .parent_names = (const char *[]){ | |
413 | "gsbi5_uart_src", | |
414 | }, | |
415 | .num_parents = 1, | |
416 | .ops = &clk_branch_ops, | |
417 | .flags = CLK_SET_RATE_PARENT, | |
418 | }, | |
419 | }, | |
420 | }; | |
421 | ||
422 | static struct clk_rcg gsbi6_uart_src = { | |
423 | .ns_reg = 0x2a74, | |
424 | .md_reg = 0x2a70, | |
425 | .mn = { | |
426 | .mnctr_en_bit = 8, | |
427 | .mnctr_reset_bit = 7, | |
428 | .mnctr_mode_shift = 5, | |
429 | .n_val_shift = 16, | |
430 | .m_val_shift = 16, | |
431 | .width = 16, | |
432 | }, | |
433 | .p = { | |
434 | .pre_div_shift = 3, | |
435 | .pre_div_width = 2, | |
436 | }, | |
437 | .s = { | |
438 | .src_sel_shift = 0, | |
439 | .parent_map = gcc_pxo_pll8_map, | |
440 | }, | |
441 | .freq_tbl = clk_tbl_gsbi_uart, | |
442 | .clkr = { | |
443 | .enable_reg = 0x2a74, | |
444 | .enable_mask = BIT(11), | |
445 | .hw.init = &(struct clk_init_data){ | |
446 | .name = "gsbi6_uart_src", | |
447 | .parent_names = gcc_pxo_pll8, | |
448 | .num_parents = 2, | |
449 | .ops = &clk_rcg_ops, | |
450 | .flags = CLK_SET_PARENT_GATE, | |
451 | }, | |
452 | }, | |
453 | }; | |
454 | ||
455 | static struct clk_branch gsbi6_uart_clk = { | |
456 | .halt_reg = 0x2fd0, | |
457 | .halt_bit = 18, | |
458 | .clkr = { | |
459 | .enable_reg = 0x2a74, | |
460 | .enable_mask = BIT(9), | |
461 | .hw.init = &(struct clk_init_data){ | |
462 | .name = "gsbi6_uart_clk", | |
463 | .parent_names = (const char *[]){ | |
464 | "gsbi6_uart_src", | |
465 | }, | |
466 | .num_parents = 1, | |
467 | .ops = &clk_branch_ops, | |
468 | .flags = CLK_SET_RATE_PARENT, | |
469 | }, | |
470 | }, | |
471 | }; | |
472 | ||
473 | static struct clk_rcg gsbi7_uart_src = { | |
474 | .ns_reg = 0x2a94, | |
475 | .md_reg = 0x2a90, | |
476 | .mn = { | |
477 | .mnctr_en_bit = 8, | |
478 | .mnctr_reset_bit = 7, | |
479 | .mnctr_mode_shift = 5, | |
480 | .n_val_shift = 16, | |
481 | .m_val_shift = 16, | |
482 | .width = 16, | |
483 | }, | |
484 | .p = { | |
485 | .pre_div_shift = 3, | |
486 | .pre_div_width = 2, | |
487 | }, | |
488 | .s = { | |
489 | .src_sel_shift = 0, | |
490 | .parent_map = gcc_pxo_pll8_map, | |
491 | }, | |
492 | .freq_tbl = clk_tbl_gsbi_uart, | |
493 | .clkr = { | |
494 | .enable_reg = 0x2a94, | |
495 | .enable_mask = BIT(11), | |
496 | .hw.init = &(struct clk_init_data){ | |
497 | .name = "gsbi7_uart_src", | |
498 | .parent_names = gcc_pxo_pll8, | |
499 | .num_parents = 2, | |
500 | .ops = &clk_rcg_ops, | |
501 | .flags = CLK_SET_PARENT_GATE, | |
502 | }, | |
503 | }, | |
504 | }; | |
505 | ||
506 | static struct clk_branch gsbi7_uart_clk = { | |
507 | .halt_reg = 0x2fd0, | |
508 | .halt_bit = 14, | |
509 | .clkr = { | |
510 | .enable_reg = 0x2a94, | |
511 | .enable_mask = BIT(9), | |
512 | .hw.init = &(struct clk_init_data){ | |
513 | .name = "gsbi7_uart_clk", | |
514 | .parent_names = (const char *[]){ | |
515 | "gsbi7_uart_src", | |
516 | }, | |
517 | .num_parents = 1, | |
518 | .ops = &clk_branch_ops, | |
519 | .flags = CLK_SET_RATE_PARENT, | |
520 | }, | |
521 | }, | |
522 | }; | |
523 | ||
524 | static struct freq_tbl clk_tbl_gsbi_qup[] = { | |
525 | { 1100000, P_PXO, 1, 2, 49 }, | |
526 | { 5400000, P_PXO, 1, 1, 5 }, | |
527 | { 10800000, P_PXO, 1, 2, 5 }, | |
528 | { 15060000, P_PLL8, 1, 2, 51 }, | |
529 | { 24000000, P_PLL8, 4, 1, 4 }, | |
0bf0ff82 | 530 | { 25000000, P_PXO, 1, 0, 0 }, |
24d8fba4 | 531 | { 25600000, P_PLL8, 1, 1, 15 }, |
24d8fba4 KG |
532 | { 48000000, P_PLL8, 4, 1, 2 }, |
533 | { 51200000, P_PLL8, 1, 2, 15 }, | |
534 | { } | |
535 | }; | |
536 | ||
537 | static struct clk_rcg gsbi1_qup_src = { | |
538 | .ns_reg = 0x29cc, | |
539 | .md_reg = 0x29c8, | |
540 | .mn = { | |
541 | .mnctr_en_bit = 8, | |
542 | .mnctr_reset_bit = 7, | |
543 | .mnctr_mode_shift = 5, | |
544 | .n_val_shift = 16, | |
545 | .m_val_shift = 16, | |
546 | .width = 8, | |
547 | }, | |
548 | .p = { | |
549 | .pre_div_shift = 3, | |
550 | .pre_div_width = 2, | |
551 | }, | |
552 | .s = { | |
553 | .src_sel_shift = 0, | |
554 | .parent_map = gcc_pxo_pll8_map, | |
555 | }, | |
556 | .freq_tbl = clk_tbl_gsbi_qup, | |
557 | .clkr = { | |
558 | .enable_reg = 0x29cc, | |
559 | .enable_mask = BIT(11), | |
560 | .hw.init = &(struct clk_init_data){ | |
561 | .name = "gsbi1_qup_src", | |
562 | .parent_names = gcc_pxo_pll8, | |
563 | .num_parents = 2, | |
564 | .ops = &clk_rcg_ops, | |
565 | .flags = CLK_SET_PARENT_GATE, | |
566 | }, | |
567 | }, | |
568 | }; | |
569 | ||
570 | static struct clk_branch gsbi1_qup_clk = { | |
571 | .halt_reg = 0x2fcc, | |
572 | .halt_bit = 11, | |
573 | .clkr = { | |
574 | .enable_reg = 0x29cc, | |
575 | .enable_mask = BIT(9), | |
576 | .hw.init = &(struct clk_init_data){ | |
577 | .name = "gsbi1_qup_clk", | |
578 | .parent_names = (const char *[]){ "gsbi1_qup_src" }, | |
579 | .num_parents = 1, | |
580 | .ops = &clk_branch_ops, | |
581 | .flags = CLK_SET_RATE_PARENT, | |
582 | }, | |
583 | }, | |
584 | }; | |
585 | ||
586 | static struct clk_rcg gsbi2_qup_src = { | |
587 | .ns_reg = 0x29ec, | |
588 | .md_reg = 0x29e8, | |
589 | .mn = { | |
590 | .mnctr_en_bit = 8, | |
591 | .mnctr_reset_bit = 7, | |
592 | .mnctr_mode_shift = 5, | |
593 | .n_val_shift = 16, | |
594 | .m_val_shift = 16, | |
595 | .width = 8, | |
596 | }, | |
597 | .p = { | |
598 | .pre_div_shift = 3, | |
599 | .pre_div_width = 2, | |
600 | }, | |
601 | .s = { | |
602 | .src_sel_shift = 0, | |
603 | .parent_map = gcc_pxo_pll8_map, | |
604 | }, | |
605 | .freq_tbl = clk_tbl_gsbi_qup, | |
606 | .clkr = { | |
607 | .enable_reg = 0x29ec, | |
608 | .enable_mask = BIT(11), | |
609 | .hw.init = &(struct clk_init_data){ | |
610 | .name = "gsbi2_qup_src", | |
611 | .parent_names = gcc_pxo_pll8, | |
612 | .num_parents = 2, | |
613 | .ops = &clk_rcg_ops, | |
614 | .flags = CLK_SET_PARENT_GATE, | |
615 | }, | |
616 | }, | |
617 | }; | |
618 | ||
619 | static struct clk_branch gsbi2_qup_clk = { | |
620 | .halt_reg = 0x2fcc, | |
621 | .halt_bit = 6, | |
622 | .clkr = { | |
623 | .enable_reg = 0x29ec, | |
624 | .enable_mask = BIT(9), | |
625 | .hw.init = &(struct clk_init_data){ | |
626 | .name = "gsbi2_qup_clk", | |
627 | .parent_names = (const char *[]){ "gsbi2_qup_src" }, | |
628 | .num_parents = 1, | |
629 | .ops = &clk_branch_ops, | |
630 | .flags = CLK_SET_RATE_PARENT, | |
631 | }, | |
632 | }, | |
633 | }; | |
634 | ||
635 | static struct clk_rcg gsbi4_qup_src = { | |
636 | .ns_reg = 0x2a2c, | |
637 | .md_reg = 0x2a28, | |
638 | .mn = { | |
639 | .mnctr_en_bit = 8, | |
640 | .mnctr_reset_bit = 7, | |
641 | .mnctr_mode_shift = 5, | |
642 | .n_val_shift = 16, | |
643 | .m_val_shift = 16, | |
644 | .width = 8, | |
645 | }, | |
646 | .p = { | |
647 | .pre_div_shift = 3, | |
648 | .pre_div_width = 2, | |
649 | }, | |
650 | .s = { | |
651 | .src_sel_shift = 0, | |
652 | .parent_map = gcc_pxo_pll8_map, | |
653 | }, | |
654 | .freq_tbl = clk_tbl_gsbi_qup, | |
655 | .clkr = { | |
656 | .enable_reg = 0x2a2c, | |
657 | .enable_mask = BIT(11), | |
658 | .hw.init = &(struct clk_init_data){ | |
659 | .name = "gsbi4_qup_src", | |
660 | .parent_names = gcc_pxo_pll8, | |
661 | .num_parents = 2, | |
662 | .ops = &clk_rcg_ops, | |
663 | .flags = CLK_SET_PARENT_GATE, | |
664 | }, | |
665 | }, | |
666 | }; | |
667 | ||
668 | static struct clk_branch gsbi4_qup_clk = { | |
669 | .halt_reg = 0x2fd0, | |
670 | .halt_bit = 24, | |
671 | .clkr = { | |
672 | .enable_reg = 0x2a2c, | |
673 | .enable_mask = BIT(9), | |
674 | .hw.init = &(struct clk_init_data){ | |
675 | .name = "gsbi4_qup_clk", | |
676 | .parent_names = (const char *[]){ "gsbi4_qup_src" }, | |
677 | .num_parents = 1, | |
678 | .ops = &clk_branch_ops, | |
679 | .flags = CLK_SET_RATE_PARENT, | |
680 | }, | |
681 | }, | |
682 | }; | |
683 | ||
684 | static struct clk_rcg gsbi5_qup_src = { | |
685 | .ns_reg = 0x2a4c, | |
686 | .md_reg = 0x2a48, | |
687 | .mn = { | |
688 | .mnctr_en_bit = 8, | |
689 | .mnctr_reset_bit = 7, | |
690 | .mnctr_mode_shift = 5, | |
691 | .n_val_shift = 16, | |
692 | .m_val_shift = 16, | |
693 | .width = 8, | |
694 | }, | |
695 | .p = { | |
696 | .pre_div_shift = 3, | |
697 | .pre_div_width = 2, | |
698 | }, | |
699 | .s = { | |
700 | .src_sel_shift = 0, | |
701 | .parent_map = gcc_pxo_pll8_map, | |
702 | }, | |
703 | .freq_tbl = clk_tbl_gsbi_qup, | |
704 | .clkr = { | |
705 | .enable_reg = 0x2a4c, | |
706 | .enable_mask = BIT(11), | |
707 | .hw.init = &(struct clk_init_data){ | |
708 | .name = "gsbi5_qup_src", | |
709 | .parent_names = gcc_pxo_pll8, | |
710 | .num_parents = 2, | |
711 | .ops = &clk_rcg_ops, | |
712 | .flags = CLK_SET_PARENT_GATE, | |
713 | }, | |
714 | }, | |
715 | }; | |
716 | ||
717 | static struct clk_branch gsbi5_qup_clk = { | |
718 | .halt_reg = 0x2fd0, | |
719 | .halt_bit = 20, | |
720 | .clkr = { | |
721 | .enable_reg = 0x2a4c, | |
722 | .enable_mask = BIT(9), | |
723 | .hw.init = &(struct clk_init_data){ | |
724 | .name = "gsbi5_qup_clk", | |
725 | .parent_names = (const char *[]){ "gsbi5_qup_src" }, | |
726 | .num_parents = 1, | |
727 | .ops = &clk_branch_ops, | |
728 | .flags = CLK_SET_RATE_PARENT, | |
729 | }, | |
730 | }, | |
731 | }; | |
732 | ||
733 | static struct clk_rcg gsbi6_qup_src = { | |
734 | .ns_reg = 0x2a6c, | |
735 | .md_reg = 0x2a68, | |
736 | .mn = { | |
737 | .mnctr_en_bit = 8, | |
738 | .mnctr_reset_bit = 7, | |
739 | .mnctr_mode_shift = 5, | |
740 | .n_val_shift = 16, | |
741 | .m_val_shift = 16, | |
742 | .width = 8, | |
743 | }, | |
744 | .p = { | |
745 | .pre_div_shift = 3, | |
746 | .pre_div_width = 2, | |
747 | }, | |
748 | .s = { | |
749 | .src_sel_shift = 0, | |
750 | .parent_map = gcc_pxo_pll8_map, | |
751 | }, | |
752 | .freq_tbl = clk_tbl_gsbi_qup, | |
753 | .clkr = { | |
754 | .enable_reg = 0x2a6c, | |
755 | .enable_mask = BIT(11), | |
756 | .hw.init = &(struct clk_init_data){ | |
757 | .name = "gsbi6_qup_src", | |
758 | .parent_names = gcc_pxo_pll8, | |
759 | .num_parents = 2, | |
760 | .ops = &clk_rcg_ops, | |
761 | .flags = CLK_SET_PARENT_GATE, | |
762 | }, | |
763 | }, | |
764 | }; | |
765 | ||
766 | static struct clk_branch gsbi6_qup_clk = { | |
767 | .halt_reg = 0x2fd0, | |
768 | .halt_bit = 16, | |
769 | .clkr = { | |
770 | .enable_reg = 0x2a6c, | |
771 | .enable_mask = BIT(9), | |
772 | .hw.init = &(struct clk_init_data){ | |
773 | .name = "gsbi6_qup_clk", | |
774 | .parent_names = (const char *[]){ "gsbi6_qup_src" }, | |
775 | .num_parents = 1, | |
776 | .ops = &clk_branch_ops, | |
777 | .flags = CLK_SET_RATE_PARENT, | |
778 | }, | |
779 | }, | |
780 | }; | |
781 | ||
782 | static struct clk_rcg gsbi7_qup_src = { | |
783 | .ns_reg = 0x2a8c, | |
784 | .md_reg = 0x2a88, | |
785 | .mn = { | |
786 | .mnctr_en_bit = 8, | |
787 | .mnctr_reset_bit = 7, | |
788 | .mnctr_mode_shift = 5, | |
789 | .n_val_shift = 16, | |
790 | .m_val_shift = 16, | |
791 | .width = 8, | |
792 | }, | |
793 | .p = { | |
794 | .pre_div_shift = 3, | |
795 | .pre_div_width = 2, | |
796 | }, | |
797 | .s = { | |
798 | .src_sel_shift = 0, | |
799 | .parent_map = gcc_pxo_pll8_map, | |
800 | }, | |
801 | .freq_tbl = clk_tbl_gsbi_qup, | |
802 | .clkr = { | |
803 | .enable_reg = 0x2a8c, | |
804 | .enable_mask = BIT(11), | |
805 | .hw.init = &(struct clk_init_data){ | |
806 | .name = "gsbi7_qup_src", | |
807 | .parent_names = gcc_pxo_pll8, | |
808 | .num_parents = 2, | |
809 | .ops = &clk_rcg_ops, | |
810 | .flags = CLK_SET_PARENT_GATE, | |
811 | }, | |
812 | }, | |
813 | }; | |
814 | ||
815 | static struct clk_branch gsbi7_qup_clk = { | |
816 | .halt_reg = 0x2fd0, | |
817 | .halt_bit = 12, | |
818 | .clkr = { | |
819 | .enable_reg = 0x2a8c, | |
820 | .enable_mask = BIT(9), | |
821 | .hw.init = &(struct clk_init_data){ | |
822 | .name = "gsbi7_qup_clk", | |
823 | .parent_names = (const char *[]){ "gsbi7_qup_src" }, | |
824 | .num_parents = 1, | |
825 | .ops = &clk_branch_ops, | |
826 | .flags = CLK_SET_RATE_PARENT, | |
827 | }, | |
828 | }, | |
829 | }; | |
830 | ||
831 | static struct clk_branch gsbi1_h_clk = { | |
832 | .hwcg_reg = 0x29c0, | |
833 | .hwcg_bit = 6, | |
834 | .halt_reg = 0x2fcc, | |
835 | .halt_bit = 13, | |
836 | .clkr = { | |
837 | .enable_reg = 0x29c0, | |
838 | .enable_mask = BIT(4), | |
839 | .hw.init = &(struct clk_init_data){ | |
840 | .name = "gsbi1_h_clk", | |
841 | .ops = &clk_branch_ops, | |
842 | .flags = CLK_IS_ROOT, | |
843 | }, | |
844 | }, | |
845 | }; | |
846 | ||
847 | static struct clk_branch gsbi2_h_clk = { | |
848 | .hwcg_reg = 0x29e0, | |
849 | .hwcg_bit = 6, | |
850 | .halt_reg = 0x2fcc, | |
851 | .halt_bit = 9, | |
852 | .clkr = { | |
853 | .enable_reg = 0x29e0, | |
854 | .enable_mask = BIT(4), | |
855 | .hw.init = &(struct clk_init_data){ | |
856 | .name = "gsbi2_h_clk", | |
857 | .ops = &clk_branch_ops, | |
858 | .flags = CLK_IS_ROOT, | |
859 | }, | |
860 | }, | |
861 | }; | |
862 | ||
863 | static struct clk_branch gsbi4_h_clk = { | |
864 | .hwcg_reg = 0x2a20, | |
865 | .hwcg_bit = 6, | |
866 | .halt_reg = 0x2fd0, | |
867 | .halt_bit = 27, | |
868 | .clkr = { | |
869 | .enable_reg = 0x2a20, | |
870 | .enable_mask = BIT(4), | |
871 | .hw.init = &(struct clk_init_data){ | |
872 | .name = "gsbi4_h_clk", | |
873 | .ops = &clk_branch_ops, | |
874 | .flags = CLK_IS_ROOT, | |
875 | }, | |
876 | }, | |
877 | }; | |
878 | ||
879 | static struct clk_branch gsbi5_h_clk = { | |
880 | .hwcg_reg = 0x2a40, | |
881 | .hwcg_bit = 6, | |
882 | .halt_reg = 0x2fd0, | |
883 | .halt_bit = 23, | |
884 | .clkr = { | |
885 | .enable_reg = 0x2a40, | |
886 | .enable_mask = BIT(4), | |
887 | .hw.init = &(struct clk_init_data){ | |
888 | .name = "gsbi5_h_clk", | |
889 | .ops = &clk_branch_ops, | |
890 | .flags = CLK_IS_ROOT, | |
891 | }, | |
892 | }, | |
893 | }; | |
894 | ||
895 | static struct clk_branch gsbi6_h_clk = { | |
896 | .hwcg_reg = 0x2a60, | |
897 | .hwcg_bit = 6, | |
898 | .halt_reg = 0x2fd0, | |
899 | .halt_bit = 19, | |
900 | .clkr = { | |
901 | .enable_reg = 0x2a60, | |
902 | .enable_mask = BIT(4), | |
903 | .hw.init = &(struct clk_init_data){ | |
904 | .name = "gsbi6_h_clk", | |
905 | .ops = &clk_branch_ops, | |
906 | .flags = CLK_IS_ROOT, | |
907 | }, | |
908 | }, | |
909 | }; | |
910 | ||
911 | static struct clk_branch gsbi7_h_clk = { | |
912 | .hwcg_reg = 0x2a80, | |
913 | .hwcg_bit = 6, | |
914 | .halt_reg = 0x2fd0, | |
915 | .halt_bit = 15, | |
916 | .clkr = { | |
917 | .enable_reg = 0x2a80, | |
918 | .enable_mask = BIT(4), | |
919 | .hw.init = &(struct clk_init_data){ | |
920 | .name = "gsbi7_h_clk", | |
921 | .ops = &clk_branch_ops, | |
922 | .flags = CLK_IS_ROOT, | |
923 | }, | |
924 | }, | |
925 | }; | |
926 | ||
927 | static const struct freq_tbl clk_tbl_gp[] = { | |
928 | { 12500000, P_PXO, 2, 0, 0 }, | |
929 | { 25000000, P_PXO, 1, 0, 0 }, | |
930 | { 64000000, P_PLL8, 2, 1, 3 }, | |
931 | { 76800000, P_PLL8, 1, 1, 5 }, | |
932 | { 96000000, P_PLL8, 4, 0, 0 }, | |
933 | { 128000000, P_PLL8, 3, 0, 0 }, | |
934 | { 192000000, P_PLL8, 2, 0, 0 }, | |
935 | { } | |
936 | }; | |
937 | ||
938 | static struct clk_rcg gp0_src = { | |
939 | .ns_reg = 0x2d24, | |
940 | .md_reg = 0x2d00, | |
941 | .mn = { | |
942 | .mnctr_en_bit = 8, | |
943 | .mnctr_reset_bit = 7, | |
944 | .mnctr_mode_shift = 5, | |
945 | .n_val_shift = 16, | |
946 | .m_val_shift = 16, | |
947 | .width = 8, | |
948 | }, | |
949 | .p = { | |
950 | .pre_div_shift = 3, | |
951 | .pre_div_width = 2, | |
952 | }, | |
953 | .s = { | |
954 | .src_sel_shift = 0, | |
955 | .parent_map = gcc_pxo_pll8_cxo_map, | |
956 | }, | |
957 | .freq_tbl = clk_tbl_gp, | |
958 | .clkr = { | |
959 | .enable_reg = 0x2d24, | |
960 | .enable_mask = BIT(11), | |
961 | .hw.init = &(struct clk_init_data){ | |
962 | .name = "gp0_src", | |
963 | .parent_names = gcc_pxo_pll8_cxo, | |
964 | .num_parents = 3, | |
965 | .ops = &clk_rcg_ops, | |
966 | .flags = CLK_SET_PARENT_GATE, | |
967 | }, | |
968 | } | |
969 | }; | |
970 | ||
971 | static struct clk_branch gp0_clk = { | |
972 | .halt_reg = 0x2fd8, | |
973 | .halt_bit = 7, | |
974 | .clkr = { | |
975 | .enable_reg = 0x2d24, | |
976 | .enable_mask = BIT(9), | |
977 | .hw.init = &(struct clk_init_data){ | |
978 | .name = "gp0_clk", | |
979 | .parent_names = (const char *[]){ "gp0_src" }, | |
980 | .num_parents = 1, | |
981 | .ops = &clk_branch_ops, | |
982 | .flags = CLK_SET_RATE_PARENT, | |
983 | }, | |
984 | }, | |
985 | }; | |
986 | ||
987 | static struct clk_rcg gp1_src = { | |
988 | .ns_reg = 0x2d44, | |
989 | .md_reg = 0x2d40, | |
990 | .mn = { | |
991 | .mnctr_en_bit = 8, | |
992 | .mnctr_reset_bit = 7, | |
993 | .mnctr_mode_shift = 5, | |
994 | .n_val_shift = 16, | |
995 | .m_val_shift = 16, | |
996 | .width = 8, | |
997 | }, | |
998 | .p = { | |
999 | .pre_div_shift = 3, | |
1000 | .pre_div_width = 2, | |
1001 | }, | |
1002 | .s = { | |
1003 | .src_sel_shift = 0, | |
1004 | .parent_map = gcc_pxo_pll8_cxo_map, | |
1005 | }, | |
1006 | .freq_tbl = clk_tbl_gp, | |
1007 | .clkr = { | |
1008 | .enable_reg = 0x2d44, | |
1009 | .enable_mask = BIT(11), | |
1010 | .hw.init = &(struct clk_init_data){ | |
1011 | .name = "gp1_src", | |
1012 | .parent_names = gcc_pxo_pll8_cxo, | |
1013 | .num_parents = 3, | |
1014 | .ops = &clk_rcg_ops, | |
1015 | .flags = CLK_SET_RATE_GATE, | |
1016 | }, | |
1017 | } | |
1018 | }; | |
1019 | ||
1020 | static struct clk_branch gp1_clk = { | |
1021 | .halt_reg = 0x2fd8, | |
1022 | .halt_bit = 6, | |
1023 | .clkr = { | |
1024 | .enable_reg = 0x2d44, | |
1025 | .enable_mask = BIT(9), | |
1026 | .hw.init = &(struct clk_init_data){ | |
1027 | .name = "gp1_clk", | |
1028 | .parent_names = (const char *[]){ "gp1_src" }, | |
1029 | .num_parents = 1, | |
1030 | .ops = &clk_branch_ops, | |
1031 | .flags = CLK_SET_RATE_PARENT, | |
1032 | }, | |
1033 | }, | |
1034 | }; | |
1035 | ||
1036 | static struct clk_rcg gp2_src = { | |
1037 | .ns_reg = 0x2d64, | |
1038 | .md_reg = 0x2d60, | |
1039 | .mn = { | |
1040 | .mnctr_en_bit = 8, | |
1041 | .mnctr_reset_bit = 7, | |
1042 | .mnctr_mode_shift = 5, | |
1043 | .n_val_shift = 16, | |
1044 | .m_val_shift = 16, | |
1045 | .width = 8, | |
1046 | }, | |
1047 | .p = { | |
1048 | .pre_div_shift = 3, | |
1049 | .pre_div_width = 2, | |
1050 | }, | |
1051 | .s = { | |
1052 | .src_sel_shift = 0, | |
1053 | .parent_map = gcc_pxo_pll8_cxo_map, | |
1054 | }, | |
1055 | .freq_tbl = clk_tbl_gp, | |
1056 | .clkr = { | |
1057 | .enable_reg = 0x2d64, | |
1058 | .enable_mask = BIT(11), | |
1059 | .hw.init = &(struct clk_init_data){ | |
1060 | .name = "gp2_src", | |
1061 | .parent_names = gcc_pxo_pll8_cxo, | |
1062 | .num_parents = 3, | |
1063 | .ops = &clk_rcg_ops, | |
1064 | .flags = CLK_SET_RATE_GATE, | |
1065 | }, | |
1066 | } | |
1067 | }; | |
1068 | ||
1069 | static struct clk_branch gp2_clk = { | |
1070 | .halt_reg = 0x2fd8, | |
1071 | .halt_bit = 5, | |
1072 | .clkr = { | |
1073 | .enable_reg = 0x2d64, | |
1074 | .enable_mask = BIT(9), | |
1075 | .hw.init = &(struct clk_init_data){ | |
1076 | .name = "gp2_clk", | |
1077 | .parent_names = (const char *[]){ "gp2_src" }, | |
1078 | .num_parents = 1, | |
1079 | .ops = &clk_branch_ops, | |
1080 | .flags = CLK_SET_RATE_PARENT, | |
1081 | }, | |
1082 | }, | |
1083 | }; | |
1084 | ||
1085 | static struct clk_branch pmem_clk = { | |
1086 | .hwcg_reg = 0x25a0, | |
1087 | .hwcg_bit = 6, | |
1088 | .halt_reg = 0x2fc8, | |
1089 | .halt_bit = 20, | |
1090 | .clkr = { | |
1091 | .enable_reg = 0x25a0, | |
1092 | .enable_mask = BIT(4), | |
1093 | .hw.init = &(struct clk_init_data){ | |
1094 | .name = "pmem_clk", | |
1095 | .ops = &clk_branch_ops, | |
1096 | .flags = CLK_IS_ROOT, | |
1097 | }, | |
1098 | }, | |
1099 | }; | |
1100 | ||
1101 | static struct clk_rcg prng_src = { | |
1102 | .ns_reg = 0x2e80, | |
1103 | .p = { | |
1104 | .pre_div_shift = 3, | |
1105 | .pre_div_width = 4, | |
1106 | }, | |
1107 | .s = { | |
1108 | .src_sel_shift = 0, | |
1109 | .parent_map = gcc_pxo_pll8_map, | |
1110 | }, | |
1111 | .clkr = { | |
1112 | .hw.init = &(struct clk_init_data){ | |
1113 | .name = "prng_src", | |
1114 | .parent_names = gcc_pxo_pll8, | |
1115 | .num_parents = 2, | |
1116 | .ops = &clk_rcg_ops, | |
1117 | }, | |
1118 | }, | |
1119 | }; | |
1120 | ||
1121 | static struct clk_branch prng_clk = { | |
1122 | .halt_reg = 0x2fd8, | |
1123 | .halt_check = BRANCH_HALT_VOTED, | |
1124 | .halt_bit = 10, | |
1125 | .clkr = { | |
1126 | .enable_reg = 0x3080, | |
1127 | .enable_mask = BIT(10), | |
1128 | .hw.init = &(struct clk_init_data){ | |
1129 | .name = "prng_clk", | |
1130 | .parent_names = (const char *[]){ "prng_src" }, | |
1131 | .num_parents = 1, | |
1132 | .ops = &clk_branch_ops, | |
1133 | }, | |
1134 | }, | |
1135 | }; | |
1136 | ||
1137 | static const struct freq_tbl clk_tbl_sdc[] = { | |
d8210e28 | 1138 | { 200000, P_PXO, 2, 2, 125 }, |
24d8fba4 KG |
1139 | { 400000, P_PLL8, 4, 1, 240 }, |
1140 | { 16000000, P_PLL8, 4, 1, 6 }, | |
1141 | { 17070000, P_PLL8, 1, 2, 45 }, | |
1142 | { 20210000, P_PLL8, 1, 1, 19 }, | |
1143 | { 24000000, P_PLL8, 4, 1, 4 }, | |
1144 | { 48000000, P_PLL8, 4, 1, 2 }, | |
1145 | { 64000000, P_PLL8, 3, 1, 2 }, | |
1146 | { 96000000, P_PLL8, 4, 0, 0 }, | |
1147 | { 192000000, P_PLL8, 2, 0, 0 }, | |
1148 | { } | |
1149 | }; | |
1150 | ||
1151 | static struct clk_rcg sdc1_src = { | |
1152 | .ns_reg = 0x282c, | |
1153 | .md_reg = 0x2828, | |
1154 | .mn = { | |
1155 | .mnctr_en_bit = 8, | |
1156 | .mnctr_reset_bit = 7, | |
1157 | .mnctr_mode_shift = 5, | |
1158 | .n_val_shift = 16, | |
1159 | .m_val_shift = 16, | |
1160 | .width = 8, | |
1161 | }, | |
1162 | .p = { | |
1163 | .pre_div_shift = 3, | |
1164 | .pre_div_width = 2, | |
1165 | }, | |
1166 | .s = { | |
1167 | .src_sel_shift = 0, | |
1168 | .parent_map = gcc_pxo_pll8_map, | |
1169 | }, | |
1170 | .freq_tbl = clk_tbl_sdc, | |
1171 | .clkr = { | |
1172 | .enable_reg = 0x282c, | |
1173 | .enable_mask = BIT(11), | |
1174 | .hw.init = &(struct clk_init_data){ | |
1175 | .name = "sdc1_src", | |
1176 | .parent_names = gcc_pxo_pll8, | |
1177 | .num_parents = 2, | |
1178 | .ops = &clk_rcg_ops, | |
1179 | .flags = CLK_SET_RATE_GATE, | |
1180 | }, | |
1181 | } | |
1182 | }; | |
1183 | ||
1184 | static struct clk_branch sdc1_clk = { | |
1185 | .halt_reg = 0x2fc8, | |
1186 | .halt_bit = 6, | |
1187 | .clkr = { | |
1188 | .enable_reg = 0x282c, | |
1189 | .enable_mask = BIT(9), | |
1190 | .hw.init = &(struct clk_init_data){ | |
1191 | .name = "sdc1_clk", | |
1192 | .parent_names = (const char *[]){ "sdc1_src" }, | |
1193 | .num_parents = 1, | |
1194 | .ops = &clk_branch_ops, | |
1195 | .flags = CLK_SET_RATE_PARENT, | |
1196 | }, | |
1197 | }, | |
1198 | }; | |
1199 | ||
1200 | static struct clk_rcg sdc3_src = { | |
1201 | .ns_reg = 0x286c, | |
1202 | .md_reg = 0x2868, | |
1203 | .mn = { | |
1204 | .mnctr_en_bit = 8, | |
1205 | .mnctr_reset_bit = 7, | |
1206 | .mnctr_mode_shift = 5, | |
1207 | .n_val_shift = 16, | |
1208 | .m_val_shift = 16, | |
1209 | .width = 8, | |
1210 | }, | |
1211 | .p = { | |
1212 | .pre_div_shift = 3, | |
1213 | .pre_div_width = 2, | |
1214 | }, | |
1215 | .s = { | |
1216 | .src_sel_shift = 0, | |
1217 | .parent_map = gcc_pxo_pll8_map, | |
1218 | }, | |
1219 | .freq_tbl = clk_tbl_sdc, | |
1220 | .clkr = { | |
1221 | .enable_reg = 0x286c, | |
1222 | .enable_mask = BIT(11), | |
1223 | .hw.init = &(struct clk_init_data){ | |
1224 | .name = "sdc3_src", | |
1225 | .parent_names = gcc_pxo_pll8, | |
1226 | .num_parents = 2, | |
1227 | .ops = &clk_rcg_ops, | |
1228 | .flags = CLK_SET_RATE_GATE, | |
1229 | }, | |
1230 | } | |
1231 | }; | |
1232 | ||
1233 | static struct clk_branch sdc3_clk = { | |
1234 | .halt_reg = 0x2fc8, | |
1235 | .halt_bit = 4, | |
1236 | .clkr = { | |
1237 | .enable_reg = 0x286c, | |
1238 | .enable_mask = BIT(9), | |
1239 | .hw.init = &(struct clk_init_data){ | |
1240 | .name = "sdc3_clk", | |
1241 | .parent_names = (const char *[]){ "sdc3_src" }, | |
1242 | .num_parents = 1, | |
1243 | .ops = &clk_branch_ops, | |
1244 | .flags = CLK_SET_RATE_PARENT, | |
1245 | }, | |
1246 | }, | |
1247 | }; | |
1248 | ||
1249 | static struct clk_branch sdc1_h_clk = { | |
1250 | .hwcg_reg = 0x2820, | |
1251 | .hwcg_bit = 6, | |
1252 | .halt_reg = 0x2fc8, | |
1253 | .halt_bit = 11, | |
1254 | .clkr = { | |
1255 | .enable_reg = 0x2820, | |
1256 | .enable_mask = BIT(4), | |
1257 | .hw.init = &(struct clk_init_data){ | |
1258 | .name = "sdc1_h_clk", | |
1259 | .ops = &clk_branch_ops, | |
1260 | .flags = CLK_IS_ROOT, | |
1261 | }, | |
1262 | }, | |
1263 | }; | |
1264 | ||
1265 | static struct clk_branch sdc3_h_clk = { | |
1266 | .hwcg_reg = 0x2860, | |
1267 | .hwcg_bit = 6, | |
1268 | .halt_reg = 0x2fc8, | |
1269 | .halt_bit = 9, | |
1270 | .clkr = { | |
1271 | .enable_reg = 0x2860, | |
1272 | .enable_mask = BIT(4), | |
1273 | .hw.init = &(struct clk_init_data){ | |
1274 | .name = "sdc3_h_clk", | |
1275 | .ops = &clk_branch_ops, | |
1276 | .flags = CLK_IS_ROOT, | |
1277 | }, | |
1278 | }, | |
1279 | }; | |
1280 | ||
1281 | static const struct freq_tbl clk_tbl_tsif_ref[] = { | |
1282 | { 105000, P_PXO, 1, 1, 256 }, | |
1283 | { } | |
1284 | }; | |
1285 | ||
1286 | static struct clk_rcg tsif_ref_src = { | |
1287 | .ns_reg = 0x2710, | |
1288 | .md_reg = 0x270c, | |
1289 | .mn = { | |
1290 | .mnctr_en_bit = 8, | |
1291 | .mnctr_reset_bit = 7, | |
1292 | .mnctr_mode_shift = 5, | |
1293 | .n_val_shift = 16, | |
1294 | .m_val_shift = 16, | |
1295 | .width = 16, | |
1296 | }, | |
1297 | .p = { | |
1298 | .pre_div_shift = 3, | |
1299 | .pre_div_width = 2, | |
1300 | }, | |
1301 | .s = { | |
1302 | .src_sel_shift = 0, | |
1303 | .parent_map = gcc_pxo_pll8_map, | |
1304 | }, | |
1305 | .freq_tbl = clk_tbl_tsif_ref, | |
1306 | .clkr = { | |
1307 | .enable_reg = 0x2710, | |
1308 | .enable_mask = BIT(11), | |
1309 | .hw.init = &(struct clk_init_data){ | |
1310 | .name = "tsif_ref_src", | |
1311 | .parent_names = gcc_pxo_pll8, | |
1312 | .num_parents = 2, | |
1313 | .ops = &clk_rcg_ops, | |
1314 | .flags = CLK_SET_RATE_GATE, | |
1315 | }, | |
1316 | } | |
1317 | }; | |
1318 | ||
1319 | static struct clk_branch tsif_ref_clk = { | |
1320 | .halt_reg = 0x2fd4, | |
1321 | .halt_bit = 5, | |
1322 | .clkr = { | |
1323 | .enable_reg = 0x2710, | |
1324 | .enable_mask = BIT(9), | |
1325 | .hw.init = &(struct clk_init_data){ | |
1326 | .name = "tsif_ref_clk", | |
1327 | .parent_names = (const char *[]){ "tsif_ref_src" }, | |
1328 | .num_parents = 1, | |
1329 | .ops = &clk_branch_ops, | |
1330 | .flags = CLK_SET_RATE_PARENT, | |
1331 | }, | |
1332 | }, | |
1333 | }; | |
1334 | ||
1335 | static struct clk_branch tsif_h_clk = { | |
1336 | .hwcg_reg = 0x2700, | |
1337 | .hwcg_bit = 6, | |
1338 | .halt_reg = 0x2fd4, | |
1339 | .halt_bit = 7, | |
1340 | .clkr = { | |
1341 | .enable_reg = 0x2700, | |
1342 | .enable_mask = BIT(4), | |
1343 | .hw.init = &(struct clk_init_data){ | |
1344 | .name = "tsif_h_clk", | |
1345 | .ops = &clk_branch_ops, | |
1346 | .flags = CLK_IS_ROOT, | |
1347 | }, | |
1348 | }, | |
1349 | }; | |
1350 | ||
1351 | static struct clk_branch dma_bam_h_clk = { | |
1352 | .hwcg_reg = 0x25c0, | |
1353 | .hwcg_bit = 6, | |
1354 | .halt_reg = 0x2fc8, | |
1355 | .halt_bit = 12, | |
1356 | .clkr = { | |
1357 | .enable_reg = 0x25c0, | |
1358 | .enable_mask = BIT(4), | |
1359 | .hw.init = &(struct clk_init_data){ | |
1360 | .name = "dma_bam_h_clk", | |
1361 | .ops = &clk_branch_ops, | |
1362 | .flags = CLK_IS_ROOT, | |
1363 | }, | |
1364 | }, | |
1365 | }; | |
1366 | ||
1367 | static struct clk_branch adm0_clk = { | |
1368 | .halt_reg = 0x2fdc, | |
1369 | .halt_check = BRANCH_HALT_VOTED, | |
1370 | .halt_bit = 12, | |
1371 | .clkr = { | |
1372 | .enable_reg = 0x3080, | |
1373 | .enable_mask = BIT(2), | |
1374 | .hw.init = &(struct clk_init_data){ | |
1375 | .name = "adm0_clk", | |
1376 | .ops = &clk_branch_ops, | |
1377 | .flags = CLK_IS_ROOT, | |
1378 | }, | |
1379 | }, | |
1380 | }; | |
1381 | ||
1382 | static struct clk_branch adm0_pbus_clk = { | |
1383 | .hwcg_reg = 0x2208, | |
1384 | .hwcg_bit = 6, | |
1385 | .halt_reg = 0x2fdc, | |
1386 | .halt_check = BRANCH_HALT_VOTED, | |
1387 | .halt_bit = 11, | |
1388 | .clkr = { | |
1389 | .enable_reg = 0x3080, | |
1390 | .enable_mask = BIT(3), | |
1391 | .hw.init = &(struct clk_init_data){ | |
1392 | .name = "adm0_pbus_clk", | |
1393 | .ops = &clk_branch_ops, | |
1394 | .flags = CLK_IS_ROOT, | |
1395 | }, | |
1396 | }, | |
1397 | }; | |
1398 | ||
1399 | static struct clk_branch pmic_arb0_h_clk = { | |
1400 | .halt_reg = 0x2fd8, | |
1401 | .halt_check = BRANCH_HALT_VOTED, | |
1402 | .halt_bit = 22, | |
1403 | .clkr = { | |
1404 | .enable_reg = 0x3080, | |
1405 | .enable_mask = BIT(8), | |
1406 | .hw.init = &(struct clk_init_data){ | |
1407 | .name = "pmic_arb0_h_clk", | |
1408 | .ops = &clk_branch_ops, | |
1409 | .flags = CLK_IS_ROOT, | |
1410 | }, | |
1411 | }, | |
1412 | }; | |
1413 | ||
1414 | static struct clk_branch pmic_arb1_h_clk = { | |
1415 | .halt_reg = 0x2fd8, | |
1416 | .halt_check = BRANCH_HALT_VOTED, | |
1417 | .halt_bit = 21, | |
1418 | .clkr = { | |
1419 | .enable_reg = 0x3080, | |
1420 | .enable_mask = BIT(9), | |
1421 | .hw.init = &(struct clk_init_data){ | |
1422 | .name = "pmic_arb1_h_clk", | |
1423 | .ops = &clk_branch_ops, | |
1424 | .flags = CLK_IS_ROOT, | |
1425 | }, | |
1426 | }, | |
1427 | }; | |
1428 | ||
1429 | static struct clk_branch pmic_ssbi2_clk = { | |
1430 | .halt_reg = 0x2fd8, | |
1431 | .halt_check = BRANCH_HALT_VOTED, | |
1432 | .halt_bit = 23, | |
1433 | .clkr = { | |
1434 | .enable_reg = 0x3080, | |
1435 | .enable_mask = BIT(7), | |
1436 | .hw.init = &(struct clk_init_data){ | |
1437 | .name = "pmic_ssbi2_clk", | |
1438 | .ops = &clk_branch_ops, | |
1439 | .flags = CLK_IS_ROOT, | |
1440 | }, | |
1441 | }, | |
1442 | }; | |
1443 | ||
1444 | static struct clk_branch rpm_msg_ram_h_clk = { | |
1445 | .hwcg_reg = 0x27e0, | |
1446 | .hwcg_bit = 6, | |
1447 | .halt_reg = 0x2fd8, | |
1448 | .halt_check = BRANCH_HALT_VOTED, | |
1449 | .halt_bit = 12, | |
1450 | .clkr = { | |
1451 | .enable_reg = 0x3080, | |
1452 | .enable_mask = BIT(6), | |
1453 | .hw.init = &(struct clk_init_data){ | |
1454 | .name = "rpm_msg_ram_h_clk", | |
1455 | .ops = &clk_branch_ops, | |
1456 | .flags = CLK_IS_ROOT, | |
1457 | }, | |
1458 | }, | |
1459 | }; | |
1460 | ||
1461 | static const struct freq_tbl clk_tbl_pcie_ref[] = { | |
1462 | { 100000000, P_PLL3, 12, 0, 0 }, | |
1463 | { } | |
1464 | }; | |
1465 | ||
1466 | static struct clk_rcg pcie_ref_src = { | |
1467 | .ns_reg = 0x3860, | |
1468 | .p = { | |
1469 | .pre_div_shift = 3, | |
1470 | .pre_div_width = 4, | |
1471 | }, | |
1472 | .s = { | |
1473 | .src_sel_shift = 0, | |
1474 | .parent_map = gcc_pxo_pll3_map, | |
1475 | }, | |
1476 | .freq_tbl = clk_tbl_pcie_ref, | |
1477 | .clkr = { | |
1478 | .enable_reg = 0x3860, | |
1479 | .enable_mask = BIT(11), | |
1480 | .hw.init = &(struct clk_init_data){ | |
1481 | .name = "pcie_ref_src", | |
1482 | .parent_names = gcc_pxo_pll3, | |
1483 | .num_parents = 2, | |
1484 | .ops = &clk_rcg_ops, | |
1485 | .flags = CLK_SET_RATE_GATE, | |
1486 | }, | |
1487 | }, | |
1488 | }; | |
1489 | ||
1490 | static struct clk_branch pcie_ref_src_clk = { | |
1491 | .halt_reg = 0x2fdc, | |
1492 | .halt_bit = 30, | |
1493 | .clkr = { | |
1494 | .enable_reg = 0x3860, | |
1495 | .enable_mask = BIT(9), | |
1496 | .hw.init = &(struct clk_init_data){ | |
1497 | .name = "pcie_ref_src_clk", | |
1498 | .parent_names = (const char *[]){ "pcie_ref_src" }, | |
1499 | .num_parents = 1, | |
1500 | .ops = &clk_branch_ops, | |
1501 | .flags = CLK_SET_RATE_PARENT, | |
1502 | }, | |
1503 | }, | |
1504 | }; | |
1505 | ||
1506 | static struct clk_branch pcie_a_clk = { | |
1507 | .halt_reg = 0x2fc0, | |
1508 | .halt_bit = 13, | |
1509 | .clkr = { | |
1510 | .enable_reg = 0x22c0, | |
1511 | .enable_mask = BIT(4), | |
1512 | .hw.init = &(struct clk_init_data){ | |
1513 | .name = "pcie_a_clk", | |
1514 | .ops = &clk_branch_ops, | |
1515 | .flags = CLK_IS_ROOT, | |
1516 | }, | |
1517 | }, | |
1518 | }; | |
1519 | ||
1520 | static struct clk_branch pcie_aux_clk = { | |
1521 | .halt_reg = 0x2fdc, | |
1522 | .halt_bit = 31, | |
1523 | .clkr = { | |
1524 | .enable_reg = 0x22c8, | |
1525 | .enable_mask = BIT(4), | |
1526 | .hw.init = &(struct clk_init_data){ | |
1527 | .name = "pcie_aux_clk", | |
1528 | .ops = &clk_branch_ops, | |
1529 | .flags = CLK_IS_ROOT, | |
1530 | }, | |
1531 | }, | |
1532 | }; | |
1533 | ||
1534 | static struct clk_branch pcie_h_clk = { | |
1535 | .halt_reg = 0x2fd4, | |
1536 | .halt_bit = 8, | |
1537 | .clkr = { | |
1538 | .enable_reg = 0x22cc, | |
1539 | .enable_mask = BIT(4), | |
1540 | .hw.init = &(struct clk_init_data){ | |
1541 | .name = "pcie_h_clk", | |
1542 | .ops = &clk_branch_ops, | |
1543 | .flags = CLK_IS_ROOT, | |
1544 | }, | |
1545 | }, | |
1546 | }; | |
1547 | ||
1548 | static struct clk_branch pcie_phy_clk = { | |
1549 | .halt_reg = 0x2fdc, | |
1550 | .halt_bit = 29, | |
1551 | .clkr = { | |
1552 | .enable_reg = 0x22d0, | |
1553 | .enable_mask = BIT(4), | |
1554 | .hw.init = &(struct clk_init_data){ | |
1555 | .name = "pcie_phy_clk", | |
1556 | .ops = &clk_branch_ops, | |
1557 | .flags = CLK_IS_ROOT, | |
1558 | }, | |
1559 | }, | |
1560 | }; | |
1561 | ||
1562 | static struct clk_rcg pcie1_ref_src = { | |
1563 | .ns_reg = 0x3aa0, | |
1564 | .p = { | |
1565 | .pre_div_shift = 3, | |
1566 | .pre_div_width = 4, | |
1567 | }, | |
1568 | .s = { | |
1569 | .src_sel_shift = 0, | |
1570 | .parent_map = gcc_pxo_pll3_map, | |
1571 | }, | |
1572 | .freq_tbl = clk_tbl_pcie_ref, | |
1573 | .clkr = { | |
1574 | .enable_reg = 0x3aa0, | |
1575 | .enable_mask = BIT(11), | |
1576 | .hw.init = &(struct clk_init_data){ | |
1577 | .name = "pcie1_ref_src", | |
1578 | .parent_names = gcc_pxo_pll3, | |
1579 | .num_parents = 2, | |
1580 | .ops = &clk_rcg_ops, | |
1581 | .flags = CLK_SET_RATE_GATE, | |
1582 | }, | |
1583 | }, | |
1584 | }; | |
1585 | ||
1586 | static struct clk_branch pcie1_ref_src_clk = { | |
1587 | .halt_reg = 0x2fdc, | |
1588 | .halt_bit = 27, | |
1589 | .clkr = { | |
1590 | .enable_reg = 0x3aa0, | |
1591 | .enable_mask = BIT(9), | |
1592 | .hw.init = &(struct clk_init_data){ | |
1593 | .name = "pcie1_ref_src_clk", | |
1594 | .parent_names = (const char *[]){ "pcie1_ref_src" }, | |
1595 | .num_parents = 1, | |
1596 | .ops = &clk_branch_ops, | |
1597 | .flags = CLK_SET_RATE_PARENT, | |
1598 | }, | |
1599 | }, | |
1600 | }; | |
1601 | ||
1602 | static struct clk_branch pcie1_a_clk = { | |
1603 | .halt_reg = 0x2fc0, | |
1604 | .halt_bit = 10, | |
1605 | .clkr = { | |
1606 | .enable_reg = 0x3a80, | |
1607 | .enable_mask = BIT(4), | |
1608 | .hw.init = &(struct clk_init_data){ | |
1609 | .name = "pcie1_a_clk", | |
1610 | .ops = &clk_branch_ops, | |
1611 | .flags = CLK_IS_ROOT, | |
1612 | }, | |
1613 | }, | |
1614 | }; | |
1615 | ||
1616 | static struct clk_branch pcie1_aux_clk = { | |
1617 | .halt_reg = 0x2fdc, | |
1618 | .halt_bit = 28, | |
1619 | .clkr = { | |
1620 | .enable_reg = 0x3a88, | |
1621 | .enable_mask = BIT(4), | |
1622 | .hw.init = &(struct clk_init_data){ | |
1623 | .name = "pcie1_aux_clk", | |
1624 | .ops = &clk_branch_ops, | |
1625 | .flags = CLK_IS_ROOT, | |
1626 | }, | |
1627 | }, | |
1628 | }; | |
1629 | ||
1630 | static struct clk_branch pcie1_h_clk = { | |
1631 | .halt_reg = 0x2fd4, | |
1632 | .halt_bit = 9, | |
1633 | .clkr = { | |
1634 | .enable_reg = 0x3a8c, | |
1635 | .enable_mask = BIT(4), | |
1636 | .hw.init = &(struct clk_init_data){ | |
1637 | .name = "pcie1_h_clk", | |
1638 | .ops = &clk_branch_ops, | |
1639 | .flags = CLK_IS_ROOT, | |
1640 | }, | |
1641 | }, | |
1642 | }; | |
1643 | ||
1644 | static struct clk_branch pcie1_phy_clk = { | |
1645 | .halt_reg = 0x2fdc, | |
1646 | .halt_bit = 26, | |
1647 | .clkr = { | |
1648 | .enable_reg = 0x3a90, | |
1649 | .enable_mask = BIT(4), | |
1650 | .hw.init = &(struct clk_init_data){ | |
1651 | .name = "pcie1_phy_clk", | |
1652 | .ops = &clk_branch_ops, | |
1653 | .flags = CLK_IS_ROOT, | |
1654 | }, | |
1655 | }, | |
1656 | }; | |
1657 | ||
1658 | static struct clk_rcg pcie2_ref_src = { | |
1659 | .ns_reg = 0x3ae0, | |
1660 | .p = { | |
1661 | .pre_div_shift = 3, | |
1662 | .pre_div_width = 4, | |
1663 | }, | |
1664 | .s = { | |
1665 | .src_sel_shift = 0, | |
1666 | .parent_map = gcc_pxo_pll3_map, | |
1667 | }, | |
1668 | .freq_tbl = clk_tbl_pcie_ref, | |
1669 | .clkr = { | |
1670 | .enable_reg = 0x3ae0, | |
1671 | .enable_mask = BIT(11), | |
1672 | .hw.init = &(struct clk_init_data){ | |
1673 | .name = "pcie2_ref_src", | |
1674 | .parent_names = gcc_pxo_pll3, | |
1675 | .num_parents = 2, | |
1676 | .ops = &clk_rcg_ops, | |
1677 | .flags = CLK_SET_RATE_GATE, | |
1678 | }, | |
1679 | }, | |
1680 | }; | |
1681 | ||
1682 | static struct clk_branch pcie2_ref_src_clk = { | |
1683 | .halt_reg = 0x2fdc, | |
1684 | .halt_bit = 24, | |
1685 | .clkr = { | |
1686 | .enable_reg = 0x3ae0, | |
1687 | .enable_mask = BIT(9), | |
1688 | .hw.init = &(struct clk_init_data){ | |
1689 | .name = "pcie2_ref_src_clk", | |
1690 | .parent_names = (const char *[]){ "pcie2_ref_src" }, | |
1691 | .num_parents = 1, | |
1692 | .ops = &clk_branch_ops, | |
1693 | .flags = CLK_SET_RATE_PARENT, | |
1694 | }, | |
1695 | }, | |
1696 | }; | |
1697 | ||
1698 | static struct clk_branch pcie2_a_clk = { | |
1699 | .halt_reg = 0x2fc0, | |
1700 | .halt_bit = 9, | |
1701 | .clkr = { | |
1702 | .enable_reg = 0x3ac0, | |
1703 | .enable_mask = BIT(4), | |
1704 | .hw.init = &(struct clk_init_data){ | |
1705 | .name = "pcie2_a_clk", | |
1706 | .ops = &clk_branch_ops, | |
1707 | .flags = CLK_IS_ROOT, | |
1708 | }, | |
1709 | }, | |
1710 | }; | |
1711 | ||
1712 | static struct clk_branch pcie2_aux_clk = { | |
1713 | .halt_reg = 0x2fdc, | |
1714 | .halt_bit = 25, | |
1715 | .clkr = { | |
1716 | .enable_reg = 0x3ac8, | |
1717 | .enable_mask = BIT(4), | |
1718 | .hw.init = &(struct clk_init_data){ | |
1719 | .name = "pcie2_aux_clk", | |
1720 | .ops = &clk_branch_ops, | |
1721 | .flags = CLK_IS_ROOT, | |
1722 | }, | |
1723 | }, | |
1724 | }; | |
1725 | ||
1726 | static struct clk_branch pcie2_h_clk = { | |
1727 | .halt_reg = 0x2fd4, | |
1728 | .halt_bit = 10, | |
1729 | .clkr = { | |
1730 | .enable_reg = 0x3acc, | |
1731 | .enable_mask = BIT(4), | |
1732 | .hw.init = &(struct clk_init_data){ | |
1733 | .name = "pcie2_h_clk", | |
1734 | .ops = &clk_branch_ops, | |
1735 | .flags = CLK_IS_ROOT, | |
1736 | }, | |
1737 | }, | |
1738 | }; | |
1739 | ||
1740 | static struct clk_branch pcie2_phy_clk = { | |
1741 | .halt_reg = 0x2fdc, | |
1742 | .halt_bit = 23, | |
1743 | .clkr = { | |
1744 | .enable_reg = 0x3ad0, | |
1745 | .enable_mask = BIT(4), | |
1746 | .hw.init = &(struct clk_init_data){ | |
1747 | .name = "pcie2_phy_clk", | |
1748 | .ops = &clk_branch_ops, | |
1749 | .flags = CLK_IS_ROOT, | |
1750 | }, | |
1751 | }, | |
1752 | }; | |
1753 | ||
1754 | static const struct freq_tbl clk_tbl_sata_ref[] = { | |
1755 | { 100000000, P_PLL3, 12, 0, 0 }, | |
1756 | { } | |
1757 | }; | |
1758 | ||
1759 | static struct clk_rcg sata_ref_src = { | |
1760 | .ns_reg = 0x2c08, | |
1761 | .p = { | |
1762 | .pre_div_shift = 3, | |
1763 | .pre_div_width = 4, | |
1764 | }, | |
1765 | .s = { | |
1766 | .src_sel_shift = 0, | |
1767 | .parent_map = gcc_pxo_pll3_sata_map, | |
1768 | }, | |
1769 | .freq_tbl = clk_tbl_sata_ref, | |
1770 | .clkr = { | |
1771 | .enable_reg = 0x2c08, | |
1772 | .enable_mask = BIT(7), | |
1773 | .hw.init = &(struct clk_init_data){ | |
1774 | .name = "sata_ref_src", | |
1775 | .parent_names = gcc_pxo_pll3, | |
1776 | .num_parents = 2, | |
1777 | .ops = &clk_rcg_ops, | |
1778 | .flags = CLK_SET_RATE_GATE, | |
1779 | }, | |
1780 | }, | |
1781 | }; | |
1782 | ||
1783 | static struct clk_branch sata_rxoob_clk = { | |
1784 | .halt_reg = 0x2fdc, | |
1785 | .halt_bit = 20, | |
1786 | .clkr = { | |
1787 | .enable_reg = 0x2c0c, | |
1788 | .enable_mask = BIT(4), | |
1789 | .hw.init = &(struct clk_init_data){ | |
1790 | .name = "sata_rxoob_clk", | |
1791 | .parent_names = (const char *[]){ "sata_ref_src" }, | |
1792 | .num_parents = 1, | |
1793 | .ops = &clk_branch_ops, | |
1794 | .flags = CLK_SET_RATE_PARENT, | |
1795 | }, | |
1796 | }, | |
1797 | }; | |
1798 | ||
1799 | static struct clk_branch sata_pmalive_clk = { | |
1800 | .halt_reg = 0x2fdc, | |
1801 | .halt_bit = 19, | |
1802 | .clkr = { | |
1803 | .enable_reg = 0x2c10, | |
1804 | .enable_mask = BIT(4), | |
1805 | .hw.init = &(struct clk_init_data){ | |
1806 | .name = "sata_pmalive_clk", | |
1807 | .parent_names = (const char *[]){ "sata_ref_src" }, | |
1808 | .num_parents = 1, | |
1809 | .ops = &clk_branch_ops, | |
1810 | .flags = CLK_SET_RATE_PARENT, | |
1811 | }, | |
1812 | }, | |
1813 | }; | |
1814 | ||
1815 | static struct clk_branch sata_phy_ref_clk = { | |
1816 | .halt_reg = 0x2fdc, | |
1817 | .halt_bit = 18, | |
1818 | .clkr = { | |
1819 | .enable_reg = 0x2c14, | |
1820 | .enable_mask = BIT(4), | |
1821 | .hw.init = &(struct clk_init_data){ | |
1822 | .name = "sata_phy_ref_clk", | |
1823 | .parent_names = (const char *[]){ "pxo" }, | |
1824 | .num_parents = 1, | |
1825 | .ops = &clk_branch_ops, | |
1826 | }, | |
1827 | }, | |
1828 | }; | |
1829 | ||
1830 | static struct clk_branch sata_a_clk = { | |
1831 | .halt_reg = 0x2fc0, | |
1832 | .halt_bit = 12, | |
1833 | .clkr = { | |
1834 | .enable_reg = 0x2c20, | |
1835 | .enable_mask = BIT(4), | |
1836 | .hw.init = &(struct clk_init_data){ | |
1837 | .name = "sata_a_clk", | |
1838 | .ops = &clk_branch_ops, | |
1839 | .flags = CLK_IS_ROOT, | |
1840 | }, | |
1841 | }, | |
1842 | }; | |
1843 | ||
1844 | static struct clk_branch sata_h_clk = { | |
1845 | .halt_reg = 0x2fdc, | |
1846 | .halt_bit = 21, | |
1847 | .clkr = { | |
1848 | .enable_reg = 0x2c00, | |
1849 | .enable_mask = BIT(4), | |
1850 | .hw.init = &(struct clk_init_data){ | |
1851 | .name = "sata_h_clk", | |
1852 | .ops = &clk_branch_ops, | |
1853 | .flags = CLK_IS_ROOT, | |
1854 | }, | |
1855 | }, | |
1856 | }; | |
1857 | ||
1858 | static struct clk_branch sfab_sata_s_h_clk = { | |
1859 | .halt_reg = 0x2fc4, | |
1860 | .halt_bit = 14, | |
1861 | .clkr = { | |
1862 | .enable_reg = 0x2480, | |
1863 | .enable_mask = BIT(4), | |
1864 | .hw.init = &(struct clk_init_data){ | |
1865 | .name = "sfab_sata_s_h_clk", | |
1866 | .ops = &clk_branch_ops, | |
1867 | .flags = CLK_IS_ROOT, | |
1868 | }, | |
1869 | }, | |
1870 | }; | |
1871 | ||
1872 | static struct clk_branch sata_phy_cfg_clk = { | |
1873 | .halt_reg = 0x2fcc, | |
1874 | .halt_bit = 14, | |
1875 | .clkr = { | |
1876 | .enable_reg = 0x2c40, | |
1877 | .enable_mask = BIT(4), | |
1878 | .hw.init = &(struct clk_init_data){ | |
1879 | .name = "sata_phy_cfg_clk", | |
1880 | .ops = &clk_branch_ops, | |
1881 | .flags = CLK_IS_ROOT, | |
1882 | }, | |
1883 | }, | |
1884 | }; | |
1885 | ||
1886 | static const struct freq_tbl clk_tbl_usb30_master[] = { | |
1887 | { 125000000, P_PLL0, 1, 5, 32 }, | |
1888 | { } | |
1889 | }; | |
1890 | ||
1891 | static struct clk_rcg usb30_master_clk_src = { | |
1892 | .ns_reg = 0x3b2c, | |
1893 | .md_reg = 0x3b28, | |
1894 | .mn = { | |
1895 | .mnctr_en_bit = 8, | |
1896 | .mnctr_reset_bit = 7, | |
1897 | .mnctr_mode_shift = 5, | |
1898 | .n_val_shift = 16, | |
1899 | .m_val_shift = 16, | |
1900 | .width = 8, | |
1901 | }, | |
1902 | .p = { | |
1903 | .pre_div_shift = 3, | |
1904 | .pre_div_width = 2, | |
1905 | }, | |
1906 | .s = { | |
1907 | .src_sel_shift = 0, | |
1908 | .parent_map = gcc_pxo_pll8_pll0, | |
1909 | }, | |
1910 | .freq_tbl = clk_tbl_usb30_master, | |
1911 | .clkr = { | |
1912 | .enable_reg = 0x3b2c, | |
1913 | .enable_mask = BIT(11), | |
1914 | .hw.init = &(struct clk_init_data){ | |
1915 | .name = "usb30_master_ref_src", | |
1916 | .parent_names = gcc_pxo_pll8_pll0_map, | |
1917 | .num_parents = 3, | |
1918 | .ops = &clk_rcg_ops, | |
1919 | .flags = CLK_SET_RATE_GATE, | |
1920 | }, | |
1921 | }, | |
1922 | }; | |
1923 | ||
1924 | static struct clk_branch usb30_0_branch_clk = { | |
1925 | .halt_reg = 0x2fc4, | |
1926 | .halt_bit = 22, | |
1927 | .clkr = { | |
1928 | .enable_reg = 0x3b24, | |
1929 | .enable_mask = BIT(4), | |
1930 | .hw.init = &(struct clk_init_data){ | |
1931 | .name = "usb30_0_branch_clk", | |
1932 | .parent_names = (const char *[]){ "usb30_master_ref_src", }, | |
1933 | .num_parents = 1, | |
1934 | .ops = &clk_branch_ops, | |
1935 | .flags = CLK_SET_RATE_PARENT, | |
1936 | }, | |
1937 | }, | |
1938 | }; | |
1939 | ||
1940 | static struct clk_branch usb30_1_branch_clk = { | |
1941 | .halt_reg = 0x2fc4, | |
1942 | .halt_bit = 17, | |
1943 | .clkr = { | |
1944 | .enable_reg = 0x3b34, | |
1945 | .enable_mask = BIT(4), | |
1946 | .hw.init = &(struct clk_init_data){ | |
1947 | .name = "usb30_1_branch_clk", | |
1948 | .parent_names = (const char *[]){ "usb30_master_ref_src", }, | |
1949 | .num_parents = 1, | |
1950 | .ops = &clk_branch_ops, | |
1951 | .flags = CLK_SET_RATE_PARENT, | |
1952 | }, | |
1953 | }, | |
1954 | }; | |
1955 | ||
1956 | static const struct freq_tbl clk_tbl_usb30_utmi[] = { | |
1957 | { 60000000, P_PLL8, 1, 5, 32 }, | |
1958 | { } | |
1959 | }; | |
1960 | ||
1961 | static struct clk_rcg usb30_utmi_clk = { | |
1962 | .ns_reg = 0x3b44, | |
1963 | .md_reg = 0x3b40, | |
1964 | .mn = { | |
1965 | .mnctr_en_bit = 8, | |
1966 | .mnctr_reset_bit = 7, | |
1967 | .mnctr_mode_shift = 5, | |
1968 | .n_val_shift = 16, | |
1969 | .m_val_shift = 16, | |
1970 | .width = 8, | |
1971 | }, | |
1972 | .p = { | |
1973 | .pre_div_shift = 3, | |
1974 | .pre_div_width = 2, | |
1975 | }, | |
1976 | .s = { | |
1977 | .src_sel_shift = 0, | |
1978 | .parent_map = gcc_pxo_pll8_pll0, | |
1979 | }, | |
1980 | .freq_tbl = clk_tbl_usb30_utmi, | |
1981 | .clkr = { | |
1982 | .enable_reg = 0x3b44, | |
1983 | .enable_mask = BIT(11), | |
1984 | .hw.init = &(struct clk_init_data){ | |
1985 | .name = "usb30_utmi_clk", | |
1986 | .parent_names = gcc_pxo_pll8_pll0_map, | |
1987 | .num_parents = 3, | |
1988 | .ops = &clk_rcg_ops, | |
1989 | .flags = CLK_SET_RATE_GATE, | |
1990 | }, | |
1991 | }, | |
1992 | }; | |
1993 | ||
1994 | static struct clk_branch usb30_0_utmi_clk_ctl = { | |
1995 | .halt_reg = 0x2fc4, | |
1996 | .halt_bit = 21, | |
1997 | .clkr = { | |
1998 | .enable_reg = 0x3b48, | |
1999 | .enable_mask = BIT(4), | |
2000 | .hw.init = &(struct clk_init_data){ | |
2001 | .name = "usb30_0_utmi_clk_ctl", | |
2002 | .parent_names = (const char *[]){ "usb30_utmi_clk", }, | |
2003 | .num_parents = 1, | |
2004 | .ops = &clk_branch_ops, | |
2005 | .flags = CLK_SET_RATE_PARENT, | |
2006 | }, | |
2007 | }, | |
2008 | }; | |
2009 | ||
2010 | static struct clk_branch usb30_1_utmi_clk_ctl = { | |
2011 | .halt_reg = 0x2fc4, | |
2012 | .halt_bit = 15, | |
2013 | .clkr = { | |
2014 | .enable_reg = 0x3b4c, | |
2015 | .enable_mask = BIT(4), | |
2016 | .hw.init = &(struct clk_init_data){ | |
2017 | .name = "usb30_1_utmi_clk_ctl", | |
2018 | .parent_names = (const char *[]){ "usb30_utmi_clk", }, | |
2019 | .num_parents = 1, | |
2020 | .ops = &clk_branch_ops, | |
2021 | .flags = CLK_SET_RATE_PARENT, | |
2022 | }, | |
2023 | }, | |
2024 | }; | |
2025 | ||
2026 | static const struct freq_tbl clk_tbl_usb[] = { | |
2027 | { 60000000, P_PLL8, 1, 5, 32 }, | |
2028 | { } | |
2029 | }; | |
2030 | ||
2031 | static struct clk_rcg usb_hs1_xcvr_clk_src = { | |
2032 | .ns_reg = 0x290C, | |
2033 | .md_reg = 0x2908, | |
2034 | .mn = { | |
2035 | .mnctr_en_bit = 8, | |
2036 | .mnctr_reset_bit = 7, | |
2037 | .mnctr_mode_shift = 5, | |
2038 | .n_val_shift = 16, | |
2039 | .m_val_shift = 16, | |
2040 | .width = 8, | |
2041 | }, | |
2042 | .p = { | |
2043 | .pre_div_shift = 3, | |
2044 | .pre_div_width = 2, | |
2045 | }, | |
2046 | .s = { | |
2047 | .src_sel_shift = 0, | |
2048 | .parent_map = gcc_pxo_pll8_pll0, | |
2049 | }, | |
2050 | .freq_tbl = clk_tbl_usb, | |
2051 | .clkr = { | |
2052 | .enable_reg = 0x2968, | |
2053 | .enable_mask = BIT(11), | |
2054 | .hw.init = &(struct clk_init_data){ | |
2055 | .name = "usb_hs1_xcvr_src", | |
2056 | .parent_names = gcc_pxo_pll8_pll0_map, | |
2057 | .num_parents = 3, | |
2058 | .ops = &clk_rcg_ops, | |
2059 | .flags = CLK_SET_RATE_GATE, | |
2060 | }, | |
2061 | }, | |
2062 | }; | |
2063 | ||
2064 | static struct clk_branch usb_hs1_xcvr_clk = { | |
2065 | .halt_reg = 0x2fcc, | |
2066 | .halt_bit = 17, | |
2067 | .clkr = { | |
2068 | .enable_reg = 0x290c, | |
2069 | .enable_mask = BIT(9), | |
2070 | .hw.init = &(struct clk_init_data){ | |
2071 | .name = "usb_hs1_xcvr_clk", | |
2072 | .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, | |
2073 | .num_parents = 1, | |
2074 | .ops = &clk_branch_ops, | |
2075 | .flags = CLK_SET_RATE_PARENT, | |
2076 | }, | |
2077 | }, | |
2078 | }; | |
2079 | ||
2080 | static struct clk_branch usb_hs1_h_clk = { | |
2081 | .hwcg_reg = 0x2900, | |
2082 | .hwcg_bit = 6, | |
2083 | .halt_reg = 0x2fc8, | |
2084 | .halt_bit = 1, | |
2085 | .clkr = { | |
2086 | .enable_reg = 0x2900, | |
2087 | .enable_mask = BIT(4), | |
2088 | .hw.init = &(struct clk_init_data){ | |
2089 | .name = "usb_hs1_h_clk", | |
2090 | .ops = &clk_branch_ops, | |
2091 | .flags = CLK_IS_ROOT, | |
2092 | }, | |
2093 | }, | |
2094 | }; | |
2095 | ||
2096 | static struct clk_rcg usb_fs1_xcvr_clk_src = { | |
2097 | .ns_reg = 0x2968, | |
2098 | .md_reg = 0x2964, | |
2099 | .mn = { | |
2100 | .mnctr_en_bit = 8, | |
2101 | .mnctr_reset_bit = 7, | |
2102 | .mnctr_mode_shift = 5, | |
2103 | .n_val_shift = 16, | |
2104 | .m_val_shift = 16, | |
2105 | .width = 8, | |
2106 | }, | |
2107 | .p = { | |
2108 | .pre_div_shift = 3, | |
2109 | .pre_div_width = 2, | |
2110 | }, | |
2111 | .s = { | |
2112 | .src_sel_shift = 0, | |
2113 | .parent_map = gcc_pxo_pll8_pll0, | |
2114 | }, | |
2115 | .freq_tbl = clk_tbl_usb, | |
2116 | .clkr = { | |
2117 | .enable_reg = 0x2968, | |
2118 | .enable_mask = BIT(11), | |
2119 | .hw.init = &(struct clk_init_data){ | |
2120 | .name = "usb_fs1_xcvr_src", | |
2121 | .parent_names = gcc_pxo_pll8_pll0_map, | |
2122 | .num_parents = 3, | |
2123 | .ops = &clk_rcg_ops, | |
2124 | .flags = CLK_SET_RATE_GATE, | |
2125 | }, | |
2126 | }, | |
2127 | }; | |
2128 | ||
2129 | static struct clk_branch usb_fs1_xcvr_clk = { | |
2130 | .halt_reg = 0x2fcc, | |
2131 | .halt_bit = 17, | |
2132 | .clkr = { | |
2133 | .enable_reg = 0x2968, | |
2134 | .enable_mask = BIT(9), | |
2135 | .hw.init = &(struct clk_init_data){ | |
2136 | .name = "usb_fs1_xcvr_clk", | |
2137 | .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, | |
2138 | .num_parents = 1, | |
2139 | .ops = &clk_branch_ops, | |
2140 | .flags = CLK_SET_RATE_PARENT, | |
2141 | }, | |
2142 | }, | |
2143 | }; | |
2144 | ||
2145 | static struct clk_branch usb_fs1_sys_clk = { | |
2146 | .halt_reg = 0x2fcc, | |
2147 | .halt_bit = 18, | |
2148 | .clkr = { | |
2149 | .enable_reg = 0x296c, | |
2150 | .enable_mask = BIT(4), | |
2151 | .hw.init = &(struct clk_init_data){ | |
2152 | .name = "usb_fs1_sys_clk", | |
2153 | .parent_names = (const char *[]){ "usb_fs1_xcvr_src", }, | |
2154 | .num_parents = 1, | |
2155 | .ops = &clk_branch_ops, | |
2156 | .flags = CLK_SET_RATE_PARENT, | |
2157 | }, | |
2158 | }, | |
2159 | }; | |
2160 | ||
2161 | static struct clk_branch usb_fs1_h_clk = { | |
2162 | .halt_reg = 0x2fcc, | |
2163 | .halt_bit = 19, | |
2164 | .clkr = { | |
2165 | .enable_reg = 0x2960, | |
2166 | .enable_mask = BIT(4), | |
2167 | .hw.init = &(struct clk_init_data){ | |
2168 | .name = "usb_fs1_h_clk", | |
2169 | .ops = &clk_branch_ops, | |
2170 | .flags = CLK_IS_ROOT, | |
2171 | }, | |
2172 | }, | |
2173 | }; | |
2174 | ||
2175 | static struct clk_regmap *gcc_ipq806x_clks[] = { | |
dc1b3f65 AG |
2176 | [PLL0] = &pll0.clkr, |
2177 | [PLL0_VOTE] = &pll0_vote, | |
24d8fba4 | 2178 | [PLL3] = &pll3.clkr, |
c99e515a | 2179 | [PLL4_VOTE] = &pll4_vote, |
24d8fba4 KG |
2180 | [PLL8] = &pll8.clkr, |
2181 | [PLL8_VOTE] = &pll8_vote, | |
2182 | [PLL14] = &pll14.clkr, | |
2183 | [PLL14_VOTE] = &pll14_vote, | |
2184 | [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr, | |
2185 | [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr, | |
2186 | [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr, | |
2187 | [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr, | |
2188 | [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr, | |
2189 | [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr, | |
2190 | [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr, | |
2191 | [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr, | |
2192 | [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr, | |
2193 | [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr, | |
2194 | [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, | |
2195 | [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, | |
2196 | [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr, | |
2197 | [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr, | |
2198 | [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr, | |
2199 | [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr, | |
2200 | [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr, | |
2201 | [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr, | |
2202 | [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr, | |
2203 | [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr, | |
2204 | [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr, | |
2205 | [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr, | |
2206 | [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, | |
2207 | [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, | |
2208 | [GP0_SRC] = &gp0_src.clkr, | |
2209 | [GP0_CLK] = &gp0_clk.clkr, | |
2210 | [GP1_SRC] = &gp1_src.clkr, | |
2211 | [GP1_CLK] = &gp1_clk.clkr, | |
2212 | [GP2_SRC] = &gp2_src.clkr, | |
2213 | [GP2_CLK] = &gp2_clk.clkr, | |
2214 | [PMEM_A_CLK] = &pmem_clk.clkr, | |
2215 | [PRNG_SRC] = &prng_src.clkr, | |
2216 | [PRNG_CLK] = &prng_clk.clkr, | |
2217 | [SDC1_SRC] = &sdc1_src.clkr, | |
2218 | [SDC1_CLK] = &sdc1_clk.clkr, | |
2219 | [SDC3_SRC] = &sdc3_src.clkr, | |
2220 | [SDC3_CLK] = &sdc3_clk.clkr, | |
2221 | [TSIF_REF_SRC] = &tsif_ref_src.clkr, | |
2222 | [TSIF_REF_CLK] = &tsif_ref_clk.clkr, | |
2223 | [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr, | |
2224 | [GSBI1_H_CLK] = &gsbi1_h_clk.clkr, | |
2225 | [GSBI2_H_CLK] = &gsbi2_h_clk.clkr, | |
2226 | [GSBI4_H_CLK] = &gsbi4_h_clk.clkr, | |
2227 | [GSBI5_H_CLK] = &gsbi5_h_clk.clkr, | |
2228 | [GSBI6_H_CLK] = &gsbi6_h_clk.clkr, | |
2229 | [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, | |
2230 | [TSIF_H_CLK] = &tsif_h_clk.clkr, | |
2231 | [SDC1_H_CLK] = &sdc1_h_clk.clkr, | |
2232 | [SDC3_H_CLK] = &sdc3_h_clk.clkr, | |
2233 | [ADM0_CLK] = &adm0_clk.clkr, | |
2234 | [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr, | |
2235 | [PCIE_A_CLK] = &pcie_a_clk.clkr, | |
2236 | [PCIE_AUX_CLK] = &pcie_aux_clk.clkr, | |
2237 | [PCIE_H_CLK] = &pcie_h_clk.clkr, | |
2238 | [PCIE_PHY_CLK] = &pcie_phy_clk.clkr, | |
2239 | [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr, | |
2240 | [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr, | |
2241 | [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr, | |
2242 | [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr, | |
2243 | [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr, | |
2244 | [SATA_H_CLK] = &sata_h_clk.clkr, | |
2245 | [SATA_CLK_SRC] = &sata_ref_src.clkr, | |
2246 | [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr, | |
2247 | [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr, | |
2248 | [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr, | |
2249 | [SATA_A_CLK] = &sata_a_clk.clkr, | |
2250 | [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr, | |
2251 | [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr, | |
2252 | [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr, | |
2253 | [PCIE_1_A_CLK] = &pcie1_a_clk.clkr, | |
2254 | [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr, | |
2255 | [PCIE_1_H_CLK] = &pcie1_h_clk.clkr, | |
2256 | [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr, | |
2257 | [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr, | |
2258 | [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr, | |
2259 | [PCIE_2_A_CLK] = &pcie2_a_clk.clkr, | |
2260 | [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr, | |
2261 | [PCIE_2_H_CLK] = &pcie2_h_clk.clkr, | |
2262 | [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr, | |
2263 | [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr, | |
2264 | [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr, | |
2265 | [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr, | |
2266 | [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr, | |
2267 | [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr, | |
2268 | [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr, | |
2269 | [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr, | |
2270 | [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr, | |
2271 | [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr, | |
2272 | [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr, | |
2273 | [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr, | |
2274 | [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr, | |
2275 | [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr, | |
2276 | [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr, | |
2277 | [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr, | |
2278 | }; | |
2279 | ||
2280 | static const struct qcom_reset_map gcc_ipq806x_resets[] = { | |
2281 | [QDSS_STM_RESET] = { 0x2060, 6 }, | |
2282 | [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 }, | |
2283 | [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 }, | |
2284 | [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 }, | |
2285 | [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 }, | |
2286 | [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 }, | |
2287 | [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 }, | |
2288 | [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 }, | |
2289 | [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 }, | |
2290 | [ADM0_C2_RESET] = { 0x220c, 4 }, | |
2291 | [ADM0_C1_RESET] = { 0x220c, 3 }, | |
2292 | [ADM0_C0_RESET] = { 0x220c, 2 }, | |
2293 | [ADM0_PBUS_RESET] = { 0x220c, 1 }, | |
2294 | [ADM0_RESET] = { 0x220c, 0 }, | |
2295 | [QDSS_CLKS_SW_RESET] = { 0x2260, 5 }, | |
2296 | [QDSS_POR_RESET] = { 0x2260, 4 }, | |
2297 | [QDSS_TSCTR_RESET] = { 0x2260, 3 }, | |
2298 | [QDSS_HRESET_RESET] = { 0x2260, 2 }, | |
2299 | [QDSS_AXI_RESET] = { 0x2260, 1 }, | |
2300 | [QDSS_DBG_RESET] = { 0x2260, 0 }, | |
2301 | [SFAB_PCIE_M_RESET] = { 0x22d8, 1 }, | |
2302 | [SFAB_PCIE_S_RESET] = { 0x22d8, 0 }, | |
2303 | [PCIE_EXT_RESET] = { 0x22dc, 6 }, | |
2304 | [PCIE_PHY_RESET] = { 0x22dc, 5 }, | |
2305 | [PCIE_PCI_RESET] = { 0x22dc, 4 }, | |
2306 | [PCIE_POR_RESET] = { 0x22dc, 3 }, | |
2307 | [PCIE_HCLK_RESET] = { 0x22dc, 2 }, | |
2308 | [PCIE_ACLK_RESET] = { 0x22dc, 0 }, | |
2309 | [SFAB_LPASS_RESET] = { 0x23a0, 7 }, | |
2310 | [SFAB_AFAB_M_RESET] = { 0x23e0, 7 }, | |
2311 | [AFAB_SFAB_M0_RESET] = { 0x2420, 7 }, | |
2312 | [AFAB_SFAB_M1_RESET] = { 0x2424, 7 }, | |
2313 | [SFAB_SATA_S_RESET] = { 0x2480, 7 }, | |
2314 | [SFAB_DFAB_M_RESET] = { 0x2500, 7 }, | |
2315 | [DFAB_SFAB_M_RESET] = { 0x2520, 7 }, | |
2316 | [DFAB_SWAY0_RESET] = { 0x2540, 7 }, | |
2317 | [DFAB_SWAY1_RESET] = { 0x2544, 7 }, | |
2318 | [DFAB_ARB0_RESET] = { 0x2560, 7 }, | |
2319 | [DFAB_ARB1_RESET] = { 0x2564, 7 }, | |
2320 | [PPSS_PROC_RESET] = { 0x2594, 1 }, | |
2321 | [PPSS_RESET] = { 0x2594, 0 }, | |
2322 | [DMA_BAM_RESET] = { 0x25c0, 7 }, | |
2323 | [SPS_TIC_H_RESET] = { 0x2600, 7 }, | |
2324 | [SFAB_CFPB_M_RESET] = { 0x2680, 7 }, | |
2325 | [SFAB_CFPB_S_RESET] = { 0x26c0, 7 }, | |
2326 | [TSIF_H_RESET] = { 0x2700, 7 }, | |
2327 | [CE1_H_RESET] = { 0x2720, 7 }, | |
2328 | [CE1_CORE_RESET] = { 0x2724, 7 }, | |
2329 | [CE1_SLEEP_RESET] = { 0x2728, 7 }, | |
2330 | [CE2_H_RESET] = { 0x2740, 7 }, | |
2331 | [CE2_CORE_RESET] = { 0x2744, 7 }, | |
2332 | [SFAB_SFPB_M_RESET] = { 0x2780, 7 }, | |
2333 | [SFAB_SFPB_S_RESET] = { 0x27a0, 7 }, | |
2334 | [RPM_PROC_RESET] = { 0x27c0, 7 }, | |
2335 | [PMIC_SSBI2_RESET] = { 0x280c, 12 }, | |
2336 | [SDC1_RESET] = { 0x2830, 0 }, | |
2337 | [SDC2_RESET] = { 0x2850, 0 }, | |
2338 | [SDC3_RESET] = { 0x2870, 0 }, | |
2339 | [SDC4_RESET] = { 0x2890, 0 }, | |
2340 | [USB_HS1_RESET] = { 0x2910, 0 }, | |
2341 | [USB_HSIC_RESET] = { 0x2934, 0 }, | |
2342 | [USB_FS1_XCVR_RESET] = { 0x2974, 1 }, | |
2343 | [USB_FS1_RESET] = { 0x2974, 0 }, | |
2344 | [GSBI1_RESET] = { 0x29dc, 0 }, | |
2345 | [GSBI2_RESET] = { 0x29fc, 0 }, | |
2346 | [GSBI3_RESET] = { 0x2a1c, 0 }, | |
2347 | [GSBI4_RESET] = { 0x2a3c, 0 }, | |
2348 | [GSBI5_RESET] = { 0x2a5c, 0 }, | |
2349 | [GSBI6_RESET] = { 0x2a7c, 0 }, | |
2350 | [GSBI7_RESET] = { 0x2a9c, 0 }, | |
2351 | [SPDM_RESET] = { 0x2b6c, 0 }, | |
2352 | [SEC_CTRL_RESET] = { 0x2b80, 7 }, | |
2353 | [TLMM_H_RESET] = { 0x2ba0, 7 }, | |
2354 | [SFAB_SATA_M_RESET] = { 0x2c18, 0 }, | |
2355 | [SATA_RESET] = { 0x2c1c, 0 }, | |
2356 | [TSSC_RESET] = { 0x2ca0, 7 }, | |
2357 | [PDM_RESET] = { 0x2cc0, 12 }, | |
2358 | [MPM_H_RESET] = { 0x2da0, 7 }, | |
2359 | [MPM_RESET] = { 0x2da4, 0 }, | |
2360 | [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 }, | |
2361 | [PRNG_RESET] = { 0x2e80, 12 }, | |
2362 | [SFAB_CE3_M_RESET] = { 0x36c8, 1 }, | |
2363 | [SFAB_CE3_S_RESET] = { 0x36c8, 0 }, | |
2364 | [CE3_SLEEP_RESET] = { 0x36d0, 7 }, | |
2365 | [PCIE_1_M_RESET] = { 0x3a98, 1 }, | |
2366 | [PCIE_1_S_RESET] = { 0x3a98, 0 }, | |
2367 | [PCIE_1_EXT_RESET] = { 0x3a9c, 6 }, | |
2368 | [PCIE_1_PHY_RESET] = { 0x3a9c, 5 }, | |
2369 | [PCIE_1_PCI_RESET] = { 0x3a9c, 4 }, | |
2370 | [PCIE_1_POR_RESET] = { 0x3a9c, 3 }, | |
2371 | [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 }, | |
2372 | [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 }, | |
2373 | [PCIE_2_M_RESET] = { 0x3ad8, 1 }, | |
2374 | [PCIE_2_S_RESET] = { 0x3ad8, 0 }, | |
2375 | [PCIE_2_EXT_RESET] = { 0x3adc, 6 }, | |
2376 | [PCIE_2_PHY_RESET] = { 0x3adc, 5 }, | |
2377 | [PCIE_2_PCI_RESET] = { 0x3adc, 4 }, | |
2378 | [PCIE_2_POR_RESET] = { 0x3adc, 3 }, | |
2379 | [PCIE_2_HCLK_RESET] = { 0x3adc, 2 }, | |
2380 | [PCIE_2_ACLK_RESET] = { 0x3adc, 0 }, | |
2381 | [SFAB_USB30_S_RESET] = { 0x3b54, 1 }, | |
2382 | [SFAB_USB30_M_RESET] = { 0x3b54, 0 }, | |
2383 | [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 }, | |
2384 | [USB30_0_MASTER_RESET] = { 0x3b50, 4 }, | |
2385 | [USB30_0_SLEEP_RESET] = { 0x3b50, 3 }, | |
2386 | [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 }, | |
2387 | [USB30_0_POWERON_RESET] = { 0x3b50, 1 }, | |
2388 | [USB30_0_PHY_RESET] = { 0x3b50, 0 }, | |
2389 | [USB30_1_MASTER_RESET] = { 0x3b58, 4 }, | |
2390 | [USB30_1_SLEEP_RESET] = { 0x3b58, 3 }, | |
2391 | [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 }, | |
2392 | [USB30_1_POWERON_RESET] = { 0x3b58, 1 }, | |
2393 | [USB30_1_PHY_RESET] = { 0x3b58, 0 }, | |
2394 | [NSSFB0_RESET] = { 0x3b60, 6 }, | |
2395 | [NSSFB1_RESET] = { 0x3b60, 7 }, | |
2396 | }; | |
2397 | ||
2398 | static const struct regmap_config gcc_ipq806x_regmap_config = { | |
2399 | .reg_bits = 32, | |
2400 | .reg_stride = 4, | |
2401 | .val_bits = 32, | |
2402 | .max_register = 0x3e40, | |
2403 | .fast_io = true, | |
2404 | }; | |
2405 | ||
2406 | static const struct qcom_cc_desc gcc_ipq806x_desc = { | |
2407 | .config = &gcc_ipq806x_regmap_config, | |
2408 | .clks = gcc_ipq806x_clks, | |
2409 | .num_clks = ARRAY_SIZE(gcc_ipq806x_clks), | |
2410 | .resets = gcc_ipq806x_resets, | |
2411 | .num_resets = ARRAY_SIZE(gcc_ipq806x_resets), | |
2412 | }; | |
2413 | ||
2414 | static const struct of_device_id gcc_ipq806x_match_table[] = { | |
2415 | { .compatible = "qcom,gcc-ipq8064" }, | |
2416 | { } | |
2417 | }; | |
2418 | MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table); | |
2419 | ||
2420 | static int gcc_ipq806x_probe(struct platform_device *pdev) | |
2421 | { | |
2422 | struct clk *clk; | |
2423 | struct device *dev = &pdev->dev; | |
2424 | ||
2425 | /* Temporary until RPM clocks supported */ | |
2426 | clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000); | |
2427 | if (IS_ERR(clk)) | |
2428 | return PTR_ERR(clk); | |
2429 | ||
2430 | clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000); | |
2431 | if (IS_ERR(clk)) | |
2432 | return PTR_ERR(clk); | |
2433 | ||
2434 | return qcom_cc_probe(pdev, &gcc_ipq806x_desc); | |
2435 | } | |
2436 | ||
2437 | static int gcc_ipq806x_remove(struct platform_device *pdev) | |
2438 | { | |
2439 | qcom_cc_remove(pdev); | |
2440 | return 0; | |
2441 | } | |
2442 | ||
2443 | static struct platform_driver gcc_ipq806x_driver = { | |
2444 | .probe = gcc_ipq806x_probe, | |
2445 | .remove = gcc_ipq806x_remove, | |
2446 | .driver = { | |
2447 | .name = "gcc-ipq806x", | |
24d8fba4 KG |
2448 | .of_match_table = gcc_ipq806x_match_table, |
2449 | }, | |
2450 | }; | |
2451 | ||
2452 | static int __init gcc_ipq806x_init(void) | |
2453 | { | |
2454 | return platform_driver_register(&gcc_ipq806x_driver); | |
2455 | } | |
2456 | core_initcall(gcc_ipq806x_init); | |
2457 | ||
2458 | static void __exit gcc_ipq806x_exit(void) | |
2459 | { | |
2460 | platform_driver_unregister(&gcc_ipq806x_driver); | |
2461 | } | |
2462 | module_exit(gcc_ipq806x_exit); | |
2463 | ||
2464 | MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver"); | |
2465 | MODULE_LICENSE("GPL v2"); | |
2466 | MODULE_ALIAS("platform:gcc-ipq806x"); |