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5190c08b XZ |
1 | /* |
2 | * Copyright (c) 2014 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
5 | * Copyright (c) 2015 Rockchip Electronics Co. Ltd. | |
6 | * Author: Xing Zheng <zhengxing@rock-chips.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
18 | ||
19 | #include <linux/clk-provider.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_address.h> | |
22 | #include <linux/syscore_ops.h> | |
23 | #include <dt-bindings/clock/rk3036-cru.h> | |
24 | #include "clk.h" | |
25 | ||
26 | #define RK3036_GRF_SOC_STATUS0 0x14c | |
27 | ||
28 | enum rk3036_plls { | |
29 | apll, dpll, gpll, | |
30 | }; | |
31 | ||
32 | static struct rockchip_pll_rate_table rk3036_pll_rates[] = { | |
33 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ | |
34 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), | |
35 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), | |
36 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), | |
37 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), | |
38 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), | |
39 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), | |
40 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), | |
41 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), | |
42 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), | |
43 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), | |
44 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), | |
45 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), | |
46 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), | |
47 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), | |
48 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), | |
49 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), | |
50 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), | |
51 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), | |
52 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), | |
53 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), | |
54 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), | |
55 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), | |
56 | RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), | |
57 | RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), | |
58 | RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), | |
59 | RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), | |
60 | RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), | |
61 | RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), | |
62 | RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), | |
63 | RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), | |
64 | RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), | |
65 | RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), | |
66 | RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), | |
67 | RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), | |
68 | RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), | |
69 | RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), | |
70 | RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), | |
71 | RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), | |
72 | RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), | |
73 | RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), | |
74 | RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), | |
75 | RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), | |
76 | { /* sentinel */ }, | |
77 | }; | |
78 | ||
79 | #define RK3036_DIV_CPU_MASK 0x1f | |
80 | #define RK3036_DIV_CPU_SHIFT 8 | |
81 | ||
82 | #define RK3036_DIV_PERI_MASK 0xf | |
83 | #define RK3036_DIV_PERI_SHIFT 0 | |
84 | #define RK3036_DIV_ACLK_MASK 0x7 | |
85 | #define RK3036_DIV_ACLK_SHIFT 4 | |
86 | #define RK3036_DIV_HCLK_MASK 0x3 | |
87 | #define RK3036_DIV_HCLK_SHIFT 8 | |
88 | #define RK3036_DIV_PCLK_MASK 0x7 | |
89 | #define RK3036_DIV_PCLK_SHIFT 12 | |
90 | ||
91 | #define RK3036_CLKSEL1(_core_periph_div) \ | |
92 | { \ | |
93 | .reg = RK2928_CLKSEL_CON(1), \ | |
94 | .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \ | |
95 | RK3036_DIV_PERI_SHIFT) \ | |
96 | } | |
97 | ||
98 | #define RK3036_CPUCLK_RATE(_prate, _core_periph_div) \ | |
99 | { \ | |
100 | .prate = _prate, \ | |
101 | .divs = { \ | |
102 | RK3036_CLKSEL1(_core_periph_div), \ | |
103 | }, \ | |
104 | } | |
105 | ||
106 | static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = { | |
107 | RK3036_CPUCLK_RATE(816000000, 4), | |
108 | RK3036_CPUCLK_RATE(600000000, 4), | |
109 | RK3036_CPUCLK_RATE(312000000, 4), | |
110 | }; | |
111 | ||
112 | static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = { | |
113 | .core_reg = RK2928_CLKSEL_CON(0), | |
114 | .div_core_shift = 0, | |
115 | .div_core_mask = 0x1f, | |
116 | .mux_core_shift = 7, | |
117 | }; | |
118 | ||
119 | PNAME(mux_pll_p) = { "xin24m", "xin24m" }; | |
120 | ||
121 | PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; | |
122 | PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" }; | |
123 | PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; | |
124 | PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; | |
125 | PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" }; | |
126 | ||
127 | PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll" "usb480m" }; | |
128 | ||
129 | PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" }; | |
130 | PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; | |
131 | PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" }; | |
132 | PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" }; | |
133 | PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; | |
134 | PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; | |
135 | PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; | |
136 | PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" }; | |
137 | PNAME(mux_dclk_p) = { "dclk_lcdc", "dclk_cru" }; | |
138 | ||
139 | static struct rockchip_pll_clock rk3036_pll_clks[] __initdata = { | |
140 | [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), | |
141 | RK2928_MODE_CON, 0, 5, 0, rk3036_pll_rates), | |
142 | [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), | |
143 | RK2928_MODE_CON, 4, 4, 0, NULL), | |
144 | [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), | |
145 | RK2928_MODE_CON, 12, 6, ROCKCHIP_PLL_SYNC_RATE, rk3036_pll_rates), | |
146 | }; | |
147 | ||
148 | #define MFLAGS CLK_MUX_HIWORD_MASK | |
149 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK | |
150 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) | |
151 | ||
152 | static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { | |
153 | /* | |
154 | * Clock-Architecture Diagram 1 | |
155 | */ | |
156 | ||
157 | GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED, | |
158 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
159 | ||
160 | /* | |
161 | * Clock-Architecture Diagram 2 | |
162 | */ | |
163 | ||
164 | GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, | |
165 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
166 | GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, | |
167 | RK2928_CLKGATE_CON(0), 8, GFLAGS), | |
168 | COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, | |
169 | RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), | |
170 | ||
171 | COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, | |
172 | RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
173 | RK2928_CLKGATE_CON(0), 7, GFLAGS), | |
174 | COMPOSITE_NOMUX(0, "aclk_core_pre", "armclk", CLK_IGNORE_UNUSED, | |
175 | RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
176 | RK2928_CLKGATE_CON(0), 7, GFLAGS), | |
177 | ||
178 | GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), | |
179 | GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
180 | COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0, | |
181 | RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS), | |
182 | GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED, | |
183 | RK2928_CLKGATE_CON(0), 3, GFLAGS), | |
184 | COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED, | |
185 | RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
186 | RK2928_CLKGATE_CON(0), 5, GFLAGS), | |
187 | COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED, | |
188 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
189 | RK2928_CLKGATE_CON(0), 4, GFLAGS), | |
190 | ||
191 | COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0, | |
192 | RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS, | |
193 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
194 | ||
195 | GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, | |
196 | RK2928_CLKGATE_CON(2), 1, GFLAGS), | |
197 | DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED, | |
198 | RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), | |
199 | GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0, | |
200 | RK2928_CLKGATE_CON(2), 3, GFLAGS), | |
201 | DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED, | |
202 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), | |
203 | GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0, | |
204 | RK2928_CLKGATE_CON(2), 2, GFLAGS), | |
205 | ||
206 | COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED, | |
207 | RK2928_CLKSEL_CON(2), 4, 1, DFLAGS, | |
208 | RK2928_CLKGATE_CON(1), 0, GFLAGS), | |
209 | COMPOSITE_NODIV(SCLK_TIMER1, "sclk_timer1", mux_timer_p, CLK_IGNORE_UNUSED, | |
210 | RK2928_CLKSEL_CON(2), 5, 1, DFLAGS, | |
211 | RK2928_CLKGATE_CON(1), 1, GFLAGS), | |
212 | COMPOSITE_NODIV(SCLK_TIMER2, "sclk_timer2", mux_timer_p, CLK_IGNORE_UNUSED, | |
213 | RK2928_CLKSEL_CON(2), 6, 1, DFLAGS, | |
214 | RK2928_CLKGATE_CON(2), 4, GFLAGS), | |
215 | COMPOSITE_NODIV(SCLK_TIMER3, "sclk_timer3", mux_timer_p, CLK_IGNORE_UNUSED, | |
216 | RK2928_CLKSEL_CON(2), 7, 1, DFLAGS, | |
217 | RK2928_CLKGATE_CON(2), 5, GFLAGS), | |
218 | ||
219 | MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, | |
220 | RK2928_CLKSEL_CON(13), 10, 2, MFLAGS), | |
221 | COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0, | |
222 | RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, | |
223 | RK2928_CLKGATE_CON(1), 8, GFLAGS), | |
224 | COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0, | |
225 | RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, | |
226 | RK2928_CLKGATE_CON(1), 8, GFLAGS), | |
227 | COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0, | |
228 | RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, | |
229 | RK2928_CLKGATE_CON(1), 8, GFLAGS), | |
230 | COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, | |
231 | RK2928_CLKSEL_CON(17), 0, | |
232 | RK2928_CLKGATE_CON(1), 9, GFLAGS), | |
233 | COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, | |
234 | RK2928_CLKSEL_CON(18), 0, | |
235 | RK2928_CLKGATE_CON(1), 11, GFLAGS), | |
236 | COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, | |
237 | RK2928_CLKSEL_CON(19), 0, | |
238 | RK2928_CLKGATE_CON(1), 13, GFLAGS), | |
239 | MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, | |
240 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), | |
241 | MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, | |
242 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), | |
243 | MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, | |
244 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), | |
245 | ||
246 | COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0, | |
247 | RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
248 | RK2928_CLKGATE_CON(3), 11, GFLAGS), | |
249 | ||
250 | COMPOSITE(0, "aclk_hvec", mux_pll_src_3plls_p, 0, | |
251 | RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS, | |
252 | RK2928_CLKGATE_CON(10), 6, GFLAGS), | |
253 | ||
254 | COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0, | |
255 | RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
256 | RK2928_CLKGATE_CON(1), 4, GFLAGS), | |
257 | COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0, | |
258 | RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, | |
259 | RK2928_CLKGATE_CON(0), 11, GFLAGS), | |
260 | COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0, | |
261 | RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS, | |
262 | RK2928_CLKGATE_CON(3), 2, GFLAGS), | |
263 | ||
264 | COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0, | |
265 | RK2928_CLKSEL_CON(12), 8, 2, DFLAGS, | |
266 | RK2928_CLKGATE_CON(2), 11, GFLAGS), | |
267 | DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0, | |
268 | RK2928_CLKSEL_CON(11), 0, 7, DFLAGS), | |
269 | ||
270 | COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, | |
271 | RK2928_CLKSEL_CON(12), 10, 2, DFLAGS, | |
272 | RK2928_CLKGATE_CON(2), 13, GFLAGS), | |
273 | DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, | |
274 | RK2928_CLKSEL_CON(11), 8, 7, DFLAGS), | |
275 | ||
276 | COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0, | |
277 | RK2928_CLKSEL_CON(12), 12, 2, MFLAGS, 0, 7, DFLAGS, | |
278 | RK2928_CLKGATE_CON(2), 14, GFLAGS), | |
279 | ||
280 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3036_SDMMC_CON0, 1), | |
281 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3036_SDMMC_CON1, 0), | |
282 | ||
283 | MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3036_SDIO_CON0, 1), | |
284 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3036_SDIO_CON1, 0), | |
285 | ||
286 | MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1), | |
287 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0), | |
288 | ||
289 | COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0, | |
290 | RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS, | |
291 | RK2928_CLKGATE_CON(0), 9, GFLAGS), | |
292 | COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, | |
293 | RK2928_CLKSEL_CON(7), 0, | |
294 | RK2928_CLKGATE_CON(0), 10, GFLAGS), | |
295 | MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, | |
296 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), | |
297 | COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0, | |
298 | RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, | |
299 | RK2928_CLKGATE_CON(0), 13, GFLAGS), | |
300 | GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT, | |
301 | RK2928_CLKGATE_CON(0), 14, GFLAGS), | |
302 | ||
303 | COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0, | |
304 | RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS, | |
305 | RK2928_CLKGATE_CON(2), 10, GFLAGS), | |
306 | COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0, | |
307 | RK2928_CLKSEL_CON(9), 0, | |
308 | RK2928_CLKGATE_CON(2), 12, GFLAGS), | |
309 | MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0, | |
310 | RK2928_CLKSEL_CON(5), 8, 2, MFLAGS), | |
311 | ||
312 | GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED, | |
313 | RK2928_CLKGATE_CON(1), 5, GFLAGS), | |
314 | ||
315 | COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0, | |
316 | RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS, | |
317 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
318 | ||
319 | COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0, | |
320 | RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS, | |
321 | RK2928_CLKGATE_CON(2), 9, GFLAGS), | |
322 | ||
323 | COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0, | |
324 | RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS, | |
325 | RK2928_CLKGATE_CON(10), 4, GFLAGS), | |
326 | ||
327 | COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, | |
328 | RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, | |
329 | RK2928_CLKGATE_CON(10), 5, GFLAGS), | |
330 | ||
331 | COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0, | |
332 | RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS), | |
333 | MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, | |
334 | RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), | |
335 | ||
336 | COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0, | |
337 | RK2928_CLKSEL_CON(21), 9, 5, DFLAGS, | |
338 | RK2928_CLKGATE_CON(2), 6, GFLAGS), | |
339 | ||
340 | MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0, | |
341 | RK2928_CLKSEL_CON(31), 0, 1, MFLAGS), | |
342 | ||
343 | /* | |
344 | * Clock-Architecture Diagram 3 | |
345 | */ | |
346 | ||
347 | /* aclk_cpu gates */ | |
348 | GATE(0, "sclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), | |
349 | GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), | |
350 | ||
351 | /* hclk_cpu gates */ | |
352 | GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 6, GFLAGS), | |
353 | ||
354 | /* pclk_cpu gates */ | |
355 | GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), | |
356 | GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), | |
357 | GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), | |
358 | GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), | |
359 | ||
360 | /* aclk_vio gates */ | |
2abc02fc | 361 | GATE(ACLK_VIO, "aclk_vio", "aclk_disp1_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 13, GFLAGS), |
5190c08b XZ |
362 | GATE(ACLK_LCDC, "aclk_lcdc", "aclk_disp1_pre", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), |
363 | ||
364 | GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS), | |
365 | GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), | |
366 | ||
367 | /* hclk_video gates */ | |
368 | GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS), | |
369 | ||
370 | /* xin24m gates */ | |
371 | GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK2928_CLKGATE_CON(10), 0, GFLAGS), | |
372 | GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK2928_CLKGATE_CON(10), 1, GFLAGS), | |
373 | ||
374 | /* aclk_peri gates */ | |
375 | GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), | |
376 | GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), | |
377 | GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), | |
378 | GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 15, GFLAGS), | |
379 | ||
380 | /* hclk_peri gates */ | |
381 | GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), | |
382 | GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 13, GFLAGS), | |
383 | GATE(0, "hclk_peri_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 14, GFLAGS), | |
384 | GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), | |
385 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), | |
386 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), | |
387 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), | |
388 | GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), | |
389 | GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), | |
390 | GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), | |
391 | GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), | |
392 | GATE(0, "hclk_mac", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 15, GFLAGS), | |
393 | ||
394 | /* pclk_peri gates */ | |
395 | GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), | |
396 | GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS), | |
397 | GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), | |
398 | GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), | |
399 | GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), | |
400 | GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), | |
401 | GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), | |
402 | GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), | |
403 | GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), | |
404 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), | |
405 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), | |
406 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), | |
407 | GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), | |
408 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), | |
409 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), | |
410 | }; | |
411 | ||
412 | static const char *const rk3036_critical_clocks[] __initconst = { | |
413 | "aclk_cpu", | |
414 | "aclk_peri", | |
415 | "hclk_peri", | |
416 | "pclk_peri", | |
417 | }; | |
418 | ||
419 | static void __init rk3036_clk_init(struct device_node *np) | |
420 | { | |
421 | void __iomem *reg_base; | |
422 | struct clk *clk; | |
423 | ||
424 | reg_base = of_iomap(np, 0); | |
425 | if (!reg_base) { | |
426 | pr_err("%s: could not map cru region\n", __func__); | |
427 | return; | |
428 | } | |
429 | ||
430 | rockchip_clk_init(np, reg_base, CLK_NR_CLKS); | |
431 | ||
432 | /* xin12m is created by an cru-internal divider */ | |
433 | clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); | |
434 | if (IS_ERR(clk)) | |
435 | pr_warn("%s: could not register clock xin12m: %ld\n", | |
436 | __func__, PTR_ERR(clk)); | |
437 | ||
438 | clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); | |
439 | if (IS_ERR(clk)) | |
440 | pr_warn("%s: could not register clock usb480m: %ld\n", | |
441 | __func__, PTR_ERR(clk)); | |
442 | ||
443 | clk = clk_register_fixed_factor(NULL, "ddrphy", "ddrphy2x", 0, 1, 2); | |
444 | if (IS_ERR(clk)) | |
445 | pr_warn("%s: could not register clock ddrphy: %ld\n", | |
446 | __func__, PTR_ERR(clk)); | |
447 | ||
448 | clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre", | |
449 | "aclk_vcodec", 0, 1, 4); | |
450 | if (IS_ERR(clk)) | |
451 | pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n", | |
452 | __func__, PTR_ERR(clk)); | |
453 | ||
454 | clk = clk_register_fixed_factor(NULL, "sclk_macref_out", | |
455 | "hclk_peri_src", 0, 1, 2); | |
456 | if (IS_ERR(clk)) | |
457 | pr_warn("%s: could not register clock sclk_macref_out: %ld\n", | |
458 | __func__, PTR_ERR(clk)); | |
459 | ||
460 | rockchip_clk_register_plls(rk3036_pll_clks, | |
461 | ARRAY_SIZE(rk3036_pll_clks), | |
462 | RK3036_GRF_SOC_STATUS0); | |
463 | rockchip_clk_register_branches(rk3036_clk_branches, | |
464 | ARRAY_SIZE(rk3036_clk_branches)); | |
465 | rockchip_clk_protect_critical(rk3036_critical_clocks, | |
466 | ARRAY_SIZE(rk3036_critical_clocks)); | |
467 | ||
468 | rockchip_clk_register_armclk(ARMCLK, "armclk", | |
469 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), | |
470 | &rk3036_cpuclk_data, rk3036_cpuclk_rates, | |
471 | ARRAY_SIZE(rk3036_cpuclk_rates)); | |
472 | ||
473 | rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), | |
474 | ROCKCHIP_SOFTRST_HIWORD_MASK); | |
475 | ||
dfff24bd | 476 | rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL); |
5190c08b XZ |
477 | } |
478 | CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init); |