[deliverable/linux.git] / drivers / clk / rockchip / clk.h

/*
 * Copyright (c) 2014 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
 * Author: Xing Zheng <zhengxing@rock-chips.com>
 *
 * based on
 *
 * samsung/clk.h
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Copyright (c) 2013 Linaro Ltd.
 * Author: Thomas Abraham <thomas.ab@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef CLK_ROCKCHIP_CLK_H
#define CLK_ROCKCHIP_CLK_H

#include <linux/io.h>

struct clk;

#define HIWORD_UPDATE(val, mask, shift) \
		((val) << (shift) | (mask) << ((shift) + 16))

/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
#define RK2928_PLL_CON(x)		((x) * 0x4)
#define RK2928_MODE_CON		0x40
#define RK2928_CLKSEL_CON(x)	((x) * 0x4 + 0x44)
#define RK2928_CLKGATE_CON(x)	((x) * 0x4 + 0xd0)
#define RK2928_GLB_SRST_FST		0x100
#define RK2928_GLB_SRST_SND		0x104
#define RK2928_SOFTRST_CON(x)	((x) * 0x4 + 0x110)
#define RK2928_MISC_CON		0x134

#define RK3036_SDMMC_CON0		0x144
#define RK3036_SDMMC_CON1		0x148
#define RK3036_SDIO_CON0		0x14c
#define RK3036_SDIO_CON1		0x150
#define RK3036_EMMC_CON0		0x154
#define RK3036_EMMC_CON1		0x158

#define RK3228_GLB_SRST_FST		0x1f0
#define RK3228_GLB_SRST_SND		0x1f4
#define RK3228_SDMMC_CON0		0x1c0
#define RK3228_SDMMC_CON1		0x1c4
#define RK3228_SDIO_CON0		0x1c8
#define RK3228_SDIO_CON1		0x1cc
#define RK3228_EMMC_CON0		0x1d8
#define RK3228_EMMC_CON1		0x1dc

#define RK3288_PLL_CON(x)		RK2928_PLL_CON(x)
#define RK3288_MODE_CON			0x50
#define RK3288_CLKSEL_CON(x)		((x) * 0x4 + 0x60)
#define RK3288_CLKGATE_CON(x)		((x) * 0x4 + 0x160)
#define RK3288_GLB_SRST_FST		0x1b0
#define RK3288_GLB_SRST_SND		0x1b4
#define RK3288_SOFTRST_CON(x)		((x) * 0x4 + 0x1b8)
#define RK3288_MISC_CON			0x1e8
#define RK3288_SDMMC_CON0		0x200
#define RK3288_SDMMC_CON1		0x204
#define RK3288_SDIO0_CON0		0x208
#define RK3288_SDIO0_CON1		0x20c
#define RK3288_SDIO1_CON0		0x210
#define RK3288_SDIO1_CON1		0x214
#define RK3288_EMMC_CON0		0x218
#define RK3288_EMMC_CON1		0x21c

#define RK3368_PLL_CON(x)		RK2928_PLL_CON(x)
#define RK3368_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
#define RK3368_CLKGATE_CON(x)		((x) * 0x4 + 0x200)
#define RK3368_GLB_SRST_FST		0x280
#define RK3368_GLB_SRST_SND		0x284
#define RK3368_SOFTRST_CON(x)		((x) * 0x4 + 0x300)
#define RK3368_MISC_CON			0x380
#define RK3368_SDMMC_CON0		0x400
#define RK3368_SDMMC_CON1		0x404
#define RK3368_SDIO0_CON0		0x408
#define RK3368_SDIO0_CON1		0x40c
#define RK3368_SDIO1_CON0		0x410
#define RK3368_SDIO1_CON1		0x414
#define RK3368_EMMC_CON0		0x418
#define RK3368_EMMC_CON1		0x41c

enum rockchip_pll_type {
	pll_rk3036,
	pll_rk3066,
};

#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,	\
			_postdiv2, _dsmpd, _frac)		\
{								\
	.rate	= _rate##U,					\
	.fbdiv = _fbdiv,					\
	.postdiv1 = _postdiv1,					\
	.refdiv = _refdiv,					\
	.postdiv2 = _postdiv2,					\
	.dsmpd = _dsmpd,					\
	.frac = _frac,						\
}

#define RK3066_PLL_RATE(_rate, _nr, _nf, _no)	\
{						\
	.rate	= _rate##U,			\
	.nr = _nr,				\
	.nf = _nf,				\
	.no = _no,				\
	.nb = ((_nf) < 2) ? 1 : (_nf) >> 1,	\
}

#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb)		\
{								\
	.rate	= _rate##U,					\
	.nr = _nr,						\
	.nf = _nf,						\
	.no = _no,						\
	.nb = _nb,						\
}

struct rockchip_pll_rate_table {
	unsigned long rate;
	unsigned int nr;
	unsigned int nf;
	unsigned int no;
	unsigned int nb;
	/* for RK3036 */
	unsigned int fbdiv;
	unsigned int postdiv1;
	unsigned int refdiv;
	unsigned int postdiv2;
	unsigned int dsmpd;
	unsigned int frac;
};

/**
 * struct rockchip_pll_clock: information about pll clock
 * @id: platform specific id of the clock.
 * @name: name of this pll clock.
 * @parent_name: name of the parent clock.
 * @flags: optional flags for basic clock.
 * @con_offset: offset of the register for configuring the PLL.
 * @mode_offset: offset of the register for configuring the PLL-mode.
 * @mode_shift: offset inside the mode-register for the mode of this pll.
 * @lock_shift: offset inside the lock register for the lock status.
 * @type: Type of PLL to be registered.
 * @pll_flags: hardware-specific flags
 * @rate_table: Table of usable pll rates
 *
 * Flags:
 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
 *	rate_table parameters and ajust them if necessary.
 */
struct rockchip_pll_clock {
	unsigned int		id;
	const char		*name;
	const char		*const *parent_names;
	u8			num_parents;
	unsigned long		flags;
	int			con_offset;
	int			mode_offset;
	int			mode_shift;
	int			lock_shift;
	enum rockchip_pll_type	type;
	u8			pll_flags;
	struct rockchip_pll_rate_table *rate_table;
};

#define ROCKCHIP_PLL_SYNC_RATE		BIT(0)

#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,	\
		_lshift, _pflags, _rtable)				\
	{								\
		.id		= _id,					\
		.type		= _type,				\
		.name		= _name,				\
		.parent_names	= _pnames,				\
		.num_parents	= ARRAY_SIZE(_pnames),			\
		.flags		= CLK_GET_RATE_NOCACHE | _flags,	\
		.con_offset	= _con,					\
		.mode_offset	= _mode,				\
		.mode_shift	= _mshift,				\
		.lock_shift	= _lshift,				\
		.pll_flags	= _pflags,				\
		.rate_table	= _rtable,				\
	}

struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
		const char *name, const char *const *parent_names,
		u8 num_parents, void __iomem *base, int con_offset,
		int grf_lock_offset, int lock_shift, int reg_mode,
		int mode_shift, struct rockchip_pll_rate_table *rate_table,
		u8 clk_pll_flags, spinlock_t *lock);

struct rockchip_cpuclk_clksel {
	int reg;
	u32 val;
};

#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	2
struct rockchip_cpuclk_rate_table {
	unsigned long prate;
	struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
};

/**
 * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
 * @core_reg:		register offset of the core settings register
 * @div_core_shift:	core divider offset used to divide the pll value
 * @div_core_mask:	core divider mask
 * @mux_core_shift:	offset of the core multiplexer
 */
struct rockchip_cpuclk_reg_data {
	int		core_reg;
	u8		div_core_shift;
	u32		div_core_mask;
	int		mux_core_reg;
	u8		mux_core_shift;
};

struct clk *rockchip_clk_register_cpuclk(const char *name,
			const char *const *parent_names, u8 num_parents,
			const struct rockchip_cpuclk_reg_data *reg_data,
			const struct rockchip_cpuclk_rate_table *rates,
			int nrates, void __iomem *reg_base, spinlock_t *lock);

struct clk *rockchip_clk_register_mmc(const char *name,
				const char *const *parent_names, u8 num_parents,
				void __iomem *reg, int shift);

#define ROCKCHIP_INVERTER_HIWORD_MASK	BIT(0)

struct clk *rockchip_clk_register_inverter(const char *name,
				const char *const *parent_names, u8 num_parents,
				void __iomem *reg, int shift, int flags,
				spinlock_t *lock);

#define PNAME(x) static const char *const x[] __initconst

enum rockchip_clk_branch_type {
	branch_composite,
	branch_mux,
	branch_divider,
	branch_fraction_divider,
	branch_gate,
	branch_mmc,
	branch_inverter,
};

struct rockchip_clk_branch {
	unsigned int			id;
	enum rockchip_clk_branch_type	branch_type;
	const char			*name;
	const char			*const *parent_names;
	u8				num_parents;
	unsigned long			flags;
	int				muxdiv_offset;
	u8				mux_shift;
	u8				mux_width;
	u8				mux_flags;
	u8				div_shift;
	u8				div_width;
	u8				div_flags;
	struct clk_div_table		*div_table;
	int				gate_offset;
	u8				gate_shift;
	u8				gate_flags;
};

#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
		  df, go, gs, gf)				\
	{							\
		.id		= _id,				\
		.branch_type	= branch_composite,		\
		.name		= cname,			\
		.parent_names	= pnames,			\
		.num_parents	= ARRAY_SIZE(pnames),		\
		.flags		= f,				\
		.muxdiv_offset	= mo,				\
		.mux_shift	= ms,				\
		.mux_width	= mw,				\
		.mux_flags	= mf,				\
		.div_shift	= ds,				\
		.div_width	= dw,				\
		.div_flags	= df,				\
		.gate_offset	= go,				\
		.gate_shift	= gs,				\
		.gate_flags	= gf,				\
	}

#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df,	\
			go, gs, gf)				\
	{							\
		.id		= _id,				\
		.branch_type	= branch_composite,		\
		.name		= cname,			\
		.parent_names	= (const char *[]){ pname },	\
		.num_parents	= 1,				\
		.flags		= f,				\
		.muxdiv_offset	= mo,				\
		.div_shift	= ds,				\
		.div_width	= dw,				\
		.div_flags	= df,				\
		.gate_offset	= go,				\
		.gate_shift	= gs,				\
		.gate_flags	= gf,				\
	}

#define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
			       df, dt, go, gs, gf)		\
	{							\
		.id		= _id,				\
		.branch_type	= branch_composite,		\
		.name		= cname,			\
		.parent_names	= (const char *[]){ pname },	\
		.num_parents	= 1,				\
		.flags		= f,				\
		.muxdiv_offset	= mo,				\
		.div_shift	= ds,				\
		.div_width	= dw,				\
		.div_flags	= df,				\
		.div_table	= dt,				\
		.gate_offset	= go,				\
		.gate_shift	= gs,				\
		.gate_flags	= gf,				\
	}

#define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf,	\
			go, gs, gf)				\
	{							\
		.id		= _id,				\
		.branch_type	= branch_composite,		\
		.name		= cname,			\
		.parent_names	= pnames,			\
		.num_parents	= ARRAY_SIZE(pnames),		\
		.flags		= f,				\
		.muxdiv_offset	= mo,				\
		.mux_shift	= ms,				\
		.mux_width	= mw,				\
		.mux_flags	= mf,				\
		.gate_offset	= go,				\
		.gate_shift	= gs,				\
		.gate_flags	= gf,				\
	}

#define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf,	\
			 ds, dw, df)				\
	{							\
		.id		= _id,				\
		.branch_type	= branch_composite,		\
		.name		= cname,			\
		.parent_names	= pnames,			\
		.num_parents	= ARRAY_SIZE(pnames),		\
		.flags		= f,				\
		.muxdiv_offset	= mo,				\
		.mux_shift	= ms,				\
		.mux_width	= mw,				\
		.mux_flags	= mf,				\
		.div_shift	= ds,				\
		.div_width	= dw,				\
		.div_flags	= df,				\
		.gate_offset	= -1,				\
	}

#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,	\
				mw, mf, ds, dw, df, dt)		\
	{							\
		.id		= _id,				\
		.branch_type	= branch_composite,		\
		.name		= cname,			\
		.parent_names	= pnames,			\
		.num_parents	= ARRAY_SIZE(pnames),		\
		.flags		= f,				\
		.muxdiv_offset	= mo,				\
		.mux_shift	= ms,				\
		.mux_width	= mw,				\
		.mux_flags	= mf,				\
		.div_shift	= ds,				\
		.div_width	= dw,				\
		.div_flags	= df,				\
		.div_table	= dt,				\
		.gate_offset	= -1,				\
	}

#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
	{							\
		.id		= _id,				\
		.branch_type	= branch_fraction_divider,	\
		.name		= cname,			\
		.parent_names	= (const char *[]){ pname },	\
		.num_parents	= 1,				\
		.flags		= f,				\
		.muxdiv_offset	= mo,				\
		.div_shift	= 16,				\
		.div_width	= 16,				\
		.div_flags	= df,				\
		.gate_offset	= go,				\
		.gate_shift	= gs,				\
		.gate_flags	= gf,				\
	}

#define MUX(_id, cname, pnames, f, o, s, w, mf)			\
	{							\
		.id		= _id,				\
		.branch_type	= branch_mux,			\
		.name		= cname,			\
		.parent_names	= pnames,			\
		.num_parents	= ARRAY_SIZE(pnames),		\
		.flags		= f,				\
		.muxdiv_offset	= o,				\
		.mux_shift	= s,				\
		.mux_width	= w,				\
		.mux_flags	= mf,				\
		.gate_offset	= -1,				\
	}

#define DIV(_id, cname, pname, f, o, s, w, df)			\
	{							\
		.id		= _id,				\
		.branch_type	= branch_divider,		\
		.name		= cname,			\
		.parent_names	= (const char *[]){ pname },	\
		.num_parents	= 1,				\
		.flags		= f,				\
		.muxdiv_offset	= o,				\
		.div_shift	= s,				\
		.div_width	= w,				\
		.div_flags	= df,				\
		.gate_offset	= -1,				\
	}

#define DIVTBL(_id, cname, pname, f, o, s, w, df, dt)		\
	{							\
		.id		= _id,				\
		.branch_type	= branch_divider,		\
		.name		= cname,			\
		.parent_names	= (const char *[]){ pname },	\
		.num_parents	= 1,				\
		.flags		= f,				\
		.muxdiv_offset	= o,				\
		.div_shift	= s,				\
		.div_width	= w,				\
		.div_flags	= df,				\
		.div_table	= dt,				\
	}

#define GATE(_id, cname, pname, f, o, b, gf)			\
	{							\
		.id		= _id,				\
		.branch_type	= branch_gate,			\
		.name		= cname,			\
		.parent_names	= (const char *[]){ pname },	\
		.num_parents	= 1,				\
		.flags		= f,				\
		.gate_offset	= o,				\
		.gate_shift	= b,				\
		.gate_flags	= gf,				\
	}

#define MMC(_id, cname, pname, offset, shift)			\
	{							\
		.id		= _id,				\
		.branch_type	= branch_mmc,			\
		.name		= cname,			\
		.parent_names	= (const char *[]){ pname },	\
		.num_parents	= 1,				\
		.muxdiv_offset	= offset,			\
		.div_shift	= shift,			\
	}

#define INVERTER(_id, cname, pname, io, is, if)			\
	{							\
		.id		= _id,				\
		.branch_type	= branch_inverter,		\
		.name		= cname,			\
		.parent_names	= (const char *[]){ pname },	\
		.num_parents	= 1,				\
		.muxdiv_offset	= io,				\
		.div_shift	= is,				\
		.div_flags	= if,				\
	}

void rockchip_clk_init(struct device_node *np, void __iomem *base,
		       unsigned long nr_clks);
struct regmap *rockchip_clk_get_grf(void);
void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
				    unsigned int nr_clk);
void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
				unsigned int nr_pll, int grf_lock_offset);
void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
			const char *const *parent_names, u8 num_parents,
			const struct rockchip_cpuclk_reg_data *reg_data,
			const struct rockchip_cpuclk_rate_table *rates,
			int nrates);
void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));

#define ROCKCHIP_SOFTRST_HIWORD_MASK	BIT(0)

#ifdef CONFIG_RESET_CONTROLLER
void rockchip_register_softrst(struct device_node *np,
			       unsigned int num_regs,
			       void __iomem *base, u8 flags);
#else
static inline void rockchip_register_softrst(struct device_node *np,
			       unsigned int num_regs,
			       void __iomem *base, u8 flags)
{
}
#endif

#endif
Commit	Line	Data
a245fecb HS	1	/*
	2	* Copyright (c) 2014 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
9c4d6e55 XZ	5	* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
	6	* Author: Xing Zheng <zhengxing@rock-chips.com>
	7	*
a245fecb HS	8	* based on
	9	*
	10	* samsung/clk.h
	11	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	12	* Copyright (c) 2013 Linaro Ltd.
	13	* Author: Thomas Abraham <thomas.ab@samsung.com>
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License as published by
	17	* the Free Software Foundation; either version 2 of the License, or
	18	* (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*/
	25
	26	#ifndef CLK_ROCKCHIP_CLK_H
	27	#define CLK_ROCKCHIP_CLK_H
	28
	29	#include <linux/io.h>
f684ff8b SB	30
f684ff8b SB	31	struct clk;
a245fecb HS	32
	33	#define HIWORD_UPDATE(val, mask, shift) \
	34	((val) << (shift) \| (mask) << ((shift) + 16))
	35
307a2e9a	36	/* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
2d7884a7	37	#define RK2928_PLL_CON(x) ((x) * 0x4)
a245fecb	38	#define RK2928_MODE_CON 0x40
2d7884a7 HS	39	#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
2d7884a7 HS	40	#define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
a245fecb HS	41	#define RK2928_GLB_SRST_FST 0x100
a245fecb HS	42	#define RK2928_GLB_SRST_SND 0x104
2d7884a7	43	#define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
a245fecb HS	44	#define RK2928_MISC_CON 0x134
a245fecb HS	45
5190c08b XZ	46	#define RK3036_SDMMC_CON0 0x144
	47	#define RK3036_SDMMC_CON1 0x148
	48	#define RK3036_SDIO_CON0 0x14c
	49	#define RK3036_SDIO_CON1 0x150
	50	#define RK3036_EMMC_CON0 0x154
	51	#define RK3036_EMMC_CON1 0x158
	52
307a2e9a JC	53	#define RK3228_GLB_SRST_FST 0x1f0
	54	#define RK3228_GLB_SRST_SND 0x1f4
	55	#define RK3228_SDMMC_CON0 0x1c0
	56	#define RK3228_SDMMC_CON1 0x1c4
	57	#define RK3228_SDIO_CON0 0x1c8
	58	#define RK3228_SDIO_CON1 0x1cc
	59	#define RK3228_EMMC_CON0 0x1d8
	60	#define RK3228_EMMC_CON1 0x1dc
	61
b9e4ba54 HS	62	#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
b9e4ba54 HS	63	#define RK3288_MODE_CON 0x50
2d7884a7 HS	64	#define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
2d7884a7 HS	65	#define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
b9e4ba54 HS	66	#define RK3288_GLB_SRST_FST 0x1b0
b9e4ba54 HS	67	#define RK3288_GLB_SRST_SND 0x1b4
2d7884a7	68	#define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
b9e4ba54	69	#define RK3288_MISC_CON 0x1e8
89bf26cb AS	70	#define RK3288_SDMMC_CON0 0x200
	71	#define RK3288_SDMMC_CON1 0x204
	72	#define RK3288_SDIO0_CON0 0x208
	73	#define RK3288_SDIO0_CON1 0x20c
	74	#define RK3288_SDIO1_CON0 0x210
	75	#define RK3288_SDIO1_CON1 0x214
	76	#define RK3288_EMMC_CON0 0x218
	77	#define RK3288_EMMC_CON1 0x21c
b9e4ba54	78
3536c97a HS	79	#define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
	80	#define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
	81	#define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
	82	#define RK3368_GLB_SRST_FST 0x280
	83	#define RK3368_GLB_SRST_SND 0x284
	84	#define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
	85	#define RK3368_MISC_CON 0x380
	86	#define RK3368_SDMMC_CON0 0x400
	87	#define RK3368_SDMMC_CON1 0x404
	88	#define RK3368_SDIO0_CON0 0x408
	89	#define RK3368_SDIO0_CON1 0x40c
	90	#define RK3368_SDIO1_CON0 0x410
	91	#define RK3368_SDIO1_CON1 0x414
	92	#define RK3368_EMMC_CON0 0x418
	93	#define RK3368_EMMC_CON1 0x41c
	94
90c59025	95	enum rockchip_pll_type {
9c4d6e55	96	pll_rk3036,
90c59025 HS	97	pll_rk3066,
	98	};
	99
9c4d6e55 XZ	100	#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
	101	_postdiv2, _dsmpd, _frac) \
	102	{ \
	103	.rate = _rate##U, \
	104	.fbdiv = _fbdiv, \
	105	.postdiv1 = _postdiv1, \
	106	.refdiv = _refdiv, \
	107	.postdiv2 = _postdiv2, \
	108	.dsmpd = _dsmpd, \
	109	.frac = _frac, \
	110	}
	111
90c59025 HS	112	#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
	113	{ \
	114	.rate = _rate##U, \
	115	.nr = _nr, \
	116	.nf = _nf, \
	117	.no = _no, \
2bbfe001	118	.nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
90c59025 HS	119	}
90c59025 HS	120
2bbfe001	121	#define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
49ed9ee4 KY	122	{ \
	123	.rate = _rate##U, \
	124	.nr = _nr, \
	125	.nf = _nf, \
	126	.no = _no, \
2bbfe001	127	.nb = _nb, \
49ed9ee4 KY	128	}
49ed9ee4 KY	129
90c59025 HS	130	struct rockchip_pll_rate_table {
	131	unsigned long rate;
	132	unsigned int nr;
	133	unsigned int nf;
	134	unsigned int no;
2bbfe001	135	unsigned int nb;
9c4d6e55 XZ	136	/* for RK3036 */
	137	unsigned int fbdiv;
	138	unsigned int postdiv1;
	139	unsigned int refdiv;
	140	unsigned int postdiv2;
	141	unsigned int dsmpd;
	142	unsigned int frac;
90c59025 HS	143	};
	144
	145	/**
	146	* struct rockchip_pll_clock: information about pll clock
	147	* @id: platform specific id of the clock.
	148	* @name: name of this pll clock.
	149	* @parent_name: name of the parent clock.
	150	* @flags: optional flags for basic clock.
	151	* @con_offset: offset of the register for configuring the PLL.
	152	* @mode_offset: offset of the register for configuring the PLL-mode.
	153	* @mode_shift: offset inside the mode-register for the mode of this pll.
	154	* @lock_shift: offset inside the lock register for the lock status.
	155	* @type: Type of PLL to be registered.
4f8a7c54	156	* @pll_flags: hardware-specific flags
90c59025	157	* @rate_table: Table of usable pll rates
0bb66d3b HS	158	*
	159	* Flags:
	160	* ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
	161	* rate_table parameters and ajust them if necessary.
90c59025 HS	162	*/
	163	struct rockchip_pll_clock {
	164	unsigned int id;
	165	const char *name;
4a1caed3	166	const char const parent_names;
90c59025 HS	167	u8 num_parents;
	168	unsigned long flags;
	169	int con_offset;
	170	int mode_offset;
	171	int mode_shift;
	172	int lock_shift;
	173	enum rockchip_pll_type type;
4f8a7c54	174	u8 pll_flags;
90c59025 HS	175	struct rockchip_pll_rate_table *rate_table;
	176	};
	177
0bb66d3b HS	178	#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
0bb66d3b HS	179
90c59025	180	#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
4f8a7c54	181	_lshift, _pflags, _rtable) \
90c59025 HS	182	{ \
	183	.id = _id, \
	184	.type = _type, \
	185	.name = _name, \
	186	.parent_names = _pnames, \
	187	.num_parents = ARRAY_SIZE(_pnames), \
	188	.flags = CLK_GET_RATE_NOCACHE \| _flags, \
	189	.con_offset = _con, \
	190	.mode_offset = _mode, \
	191	.mode_shift = _mshift, \
	192	.lock_shift = _lshift, \
4f8a7c54	193	.pll_flags = _pflags, \
90c59025 HS	194	.rate_table = _rtable, \
	195	}
	196
	197	struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
4a1caed3 UKK	198	const char name, const char const *parent_names,
	199	u8 num_parents, void __iomem *base, int con_offset,
	200	int grf_lock_offset, int lock_shift, int reg_mode,
	201	int mode_shift, struct rockchip_pll_rate_table *rate_table,
4f8a7c54	202	u8 clk_pll_flags, spinlock_t *lock);
90c59025	203
f6fba5f6 HS	204	struct rockchip_cpuclk_clksel {
	205	int reg;
	206	u32 val;
	207	};
	208
	209	#define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
	210	struct rockchip_cpuclk_rate_table {
	211	unsigned long prate;
	212	struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
	213	};
	214
	215	/**
	216	* struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
	217	* @core_reg: register offset of the core settings register
	218	* @div_core_shift: core divider offset used to divide the pll value
	219	* @div_core_mask: core divider mask
	220	* @mux_core_shift: offset of the core multiplexer
	221	*/
	222	struct rockchip_cpuclk_reg_data {
	223	int core_reg;
	224	u8 div_core_shift;
	225	u32 div_core_mask;
	226	int mux_core_reg;
	227	u8 mux_core_shift;
	228	};
	229
	230	struct clk rockchip_clk_register_cpuclk(const char name,
4a1caed3	231	const char const parent_names, u8 num_parents,
f6fba5f6 HS	232	const struct rockchip_cpuclk_reg_data *reg_data,
	233	const struct rockchip_cpuclk_rate_table *rates,
	234	int nrates, void __iomem reg_base, spinlock_t lock);
	235
89bf26cb	236	struct clk rockchip_clk_register_mmc(const char name,
4a1caed3	237	const char const parent_names, u8 num_parents,
89bf26cb AS	238	void __iomem *reg, int shift);
89bf26cb AS	239
8a76f443 HS	240	#define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
	241
	242	struct clk rockchip_clk_register_inverter(const char name,
	243	const char const parent_names, u8 num_parents,
	244	void __iomem *reg, int shift, int flags,
	245	spinlock_t *lock);
	246
4a1caed3	247	#define PNAME(x) static const char *const x[] __initconst
a245fecb HS	248
	249	enum rockchip_clk_branch_type {
	250	branch_composite,
	251	branch_mux,
	252	branch_divider,
	253	branch_fraction_divider,
	254	branch_gate,
89bf26cb	255	branch_mmc,
8a76f443	256	branch_inverter,
a245fecb HS	257	};
	258
	259	struct rockchip_clk_branch {
	260	unsigned int id;
	261	enum rockchip_clk_branch_type branch_type;
	262	const char *name;
4a1caed3	263	const char const parent_names;
a245fecb HS	264	u8 num_parents;
	265	unsigned long flags;
	266	int muxdiv_offset;
	267	u8 mux_shift;
	268	u8 mux_width;
	269	u8 mux_flags;
	270	u8 div_shift;
	271	u8 div_width;
	272	u8 div_flags;
	273	struct clk_div_table *div_table;
	274	int gate_offset;
	275	u8 gate_shift;
	276	u8 gate_flags;
	277	};
	278
	279	#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
	280	df, go, gs, gf) \
	281	{ \
	282	.id = _id, \
	283	.branch_type = branch_composite, \
	284	.name = cname, \
	285	.parent_names = pnames, \
	286	.num_parents = ARRAY_SIZE(pnames), \
	287	.flags = f, \
	288	.muxdiv_offset = mo, \
	289	.mux_shift = ms, \
	290	.mux_width = mw, \
	291	.mux_flags = mf, \
	292	.div_shift = ds, \
	293	.div_width = dw, \
	294	.div_flags = df, \
	295	.gate_offset = go, \
	296	.gate_shift = gs, \
	297	.gate_flags = gf, \
	298	}
	299
	300	#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
	301	go, gs, gf) \
	302	{ \
	303	.id = _id, \
	304	.branch_type = branch_composite, \
	305	.name = cname, \
	306	.parent_names = (const char *[]){ pname }, \
	307	.num_parents = 1, \
	308	.flags = f, \
	309	.muxdiv_offset = mo, \
	310	.div_shift = ds, \
	311	.div_width = dw, \
	312	.div_flags = df, \
	313	.gate_offset = go, \
	314	.gate_shift = gs, \
	315	.gate_flags = gf, \
	316	}
	317
	318	#define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
	319	df, dt, go, gs, gf) \
	320	{ \
	321	.id = _id, \
	322	.branch_type = branch_composite, \
	323	.name = cname, \
	324	.parent_names = (const char *[]){ pname }, \
	325	.num_parents = 1, \
	326	.flags = f, \
	327	.muxdiv_offset = mo, \
328	.div_shift = ds, \
329	.div_width = dw, \
330	.div_flags = df, \
331	.div_table = dt, \
332	.gate_offset = go, \
333	.gate_shift = gs, \
334	.gate_flags = gf, \
335	}
336
337	#define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
338	go, gs, gf) \
339	{ \
340	.id = _id, \
341	.branch_type = branch_composite, \
342	.name = cname, \
343	.parent_names = pnames, \
344	.num_parents = ARRAY_SIZE(pnames), \
345	.flags = f, \
346	.muxdiv_offset = mo, \
347	.mux_shift = ms, \
348	.mux_width = mw, \
349	.mux_flags = mf, \
350	.gate_offset = go, \
351	.gate_shift = gs, \
352	.gate_flags = gf, \
353	}
354
355	#define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
356	ds, dw, df) \
357	{ \
358	.id = _id, \
359	.branch_type = branch_composite, \
360	.name = cname, \
361	.parent_names = pnames, \
362	.num_parents = ARRAY_SIZE(pnames), \
363	.flags = f, \
364	.muxdiv_offset = mo, \
365	.mux_shift = ms, \
366	.mux_width = mw, \
367	.mux_flags = mf, \
368	.div_shift = ds, \
369	.div_width = dw, \
370	.div_flags = df, \
371	.gate_offset = -1, \
372	}
373
6f085072 HS	374	#define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
	375	mw, mf, ds, dw, df, dt) \
	376	{ \
	377	.id = _id, \
	378	.branch_type = branch_composite, \
	379	.name = cname, \
	380	.parent_names = pnames, \
	381	.num_parents = ARRAY_SIZE(pnames), \
	382	.flags = f, \
	383	.muxdiv_offset = mo, \
	384	.mux_shift = ms, \
	385	.mux_width = mw, \
	386	.mux_flags = mf, \
	387	.div_shift = ds, \
	388	.div_width = dw, \
	389	.div_flags = df, \
	390	.div_table = dt, \
	391	.gate_offset = -1, \
	392	}
	393
a245fecb HS	394	#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
	395	{ \
	396	.id = _id, \
	397	.branch_type = branch_fraction_divider, \
	398	.name = cname, \
	399	.parent_names = (const char *[]){ pname }, \
	400	.num_parents = 1, \
	401	.flags = f, \
	402	.muxdiv_offset = mo, \
	403	.div_shift = 16, \
	404	.div_width = 16, \
	405	.div_flags = df, \
	406	.gate_offset = go, \
	407	.gate_shift = gs, \
	408	.gate_flags = gf, \
	409	}
	410
	411	#define MUX(_id, cname, pnames, f, o, s, w, mf) \
	412	{ \
	413	.id = _id, \
	414	.branch_type = branch_mux, \
	415	.name = cname, \
	416	.parent_names = pnames, \
	417	.num_parents = ARRAY_SIZE(pnames), \
	418	.flags = f, \
	419	.muxdiv_offset = o, \
	420	.mux_shift = s, \
	421	.mux_width = w, \
	422	.mux_flags = mf, \
	423	.gate_offset = -1, \
	424	}
	425
	426	#define DIV(_id, cname, pname, f, o, s, w, df) \
	427	{ \
	428	.id = _id, \
	429	.branch_type = branch_divider, \
	430	.name = cname, \
	431	.parent_names = (const char *[]){ pname }, \
	432	.num_parents = 1, \
	433	.flags = f, \
	434	.muxdiv_offset = o, \
	435	.div_shift = s, \
	436	.div_width = w, \
	437	.div_flags = df, \
	438	.gate_offset = -1, \
	439	}
	440
	441	#define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
	442	{ \
	443	.id = _id, \
	444	.branch_type = branch_divider, \
	445	.name = cname, \
	446	.parent_names = (const char *[]){ pname }, \
	447	.num_parents = 1, \
	448	.flags = f, \
	449	.muxdiv_offset = o, \
	450	.div_shift = s, \
	451	.div_width = w, \
	452	.div_flags = df, \
	453	.div_table = dt, \
	454	}
	455
	456	#define GATE(_id, cname, pname, f, o, b, gf) \
	457	{ \
458	.id = _id, \
459	.branch_type = branch_gate, \
460	.name = cname, \
461	.parent_names = (const char *[]){ pname }, \
462	.num_parents = 1, \
463	.flags = f, \
464	.gate_offset = o, \
465	.gate_shift = b, \
466	.gate_flags = gf, \
467	}
468
89bf26cb AS	469	#define MMC(_id, cname, pname, offset, shift) \
	470	{ \
	471	.id = _id, \
	472	.branch_type = branch_mmc, \
	473	.name = cname, \
	474	.parent_names = (const char *[]){ pname }, \
	475	.num_parents = 1, \
	476	.muxdiv_offset = offset, \
	477	.div_shift = shift, \
	478	}
a245fecb	479
8a76f443 HS	480	#define INVERTER(_id, cname, pname, io, is, if) \
	481	{ \
	482	.id = _id, \
	483	.branch_type = branch_inverter, \
	484	.name = cname, \
	485	.parent_names = (const char *[]){ pname }, \
	486	.num_parents = 1, \
	487	.muxdiv_offset = io, \
	488	.div_shift = is, \
	489	.div_flags = if, \
	490	}
	491
a245fecb HS	492	void rockchip_clk_init(struct device_node np, void __iomem base,
a245fecb HS	493	unsigned long nr_clks);
90c59025	494	struct regmap *rockchip_clk_get_grf(void);
a245fecb HS	495	void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
	496	void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
	497	unsigned int nr_clk);
90c59025 HS	498	void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
90c59025 HS	499	unsigned int nr_pll, int grf_lock_offset);
f6fba5f6	500	void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
4a1caed3	501	const char const parent_names, u8 num_parents,
f6fba5f6 HS	502	const struct rockchip_cpuclk_reg_data *reg_data,
	503	const struct rockchip_cpuclk_rate_table *rates,
	504	int nrates);
692d8328	505	void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
dfff24bd	506	void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));
a245fecb	507
85fa0c7f HS	508	#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
	509
	510	#ifdef CONFIG_RESET_CONTROLLER
	511	void rockchip_register_softrst(struct device_node *np,
	512	unsigned int num_regs,
	513	void __iomem *base, u8 flags);
	514	#else
	515	static inline void rockchip_register_softrst(struct device_node *np,
	516	unsigned int num_regs,
	517	void __iomem *base, u8 flags)
	518	{
	519	}
	520	#endif
	521
a245fecb	522	#endif