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e062b571 TA |
1 | /* |
2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
3 | * Copyright (c) 2013 Linaro Ltd. | |
4 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Common Clock Framework support for all Exynos4 SoCs. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/clkdev.h> | |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
18 | ||
e062b571 | 19 | #include "clk.h" |
e062b571 TA |
20 | |
21 | /* Exynos4 clock controller register offsets */ | |
22 | #define SRC_LEFTBUS 0x4200 | |
fb948f74 TF |
23 | #define DIV_LEFTBUS 0x4500 |
24 | #define GATE_IP_LEFTBUS 0x4800 | |
e062b571 | 25 | #define E4X12_GATE_IP_IMAGE 0x4930 |
fb948f74 TF |
26 | #define SRC_RIGHTBUS 0x8200 |
27 | #define DIV_RIGHTBUS 0x8500 | |
e062b571 TA |
28 | #define GATE_IP_RIGHTBUS 0x8800 |
29 | #define E4X12_GATE_IP_PERIR 0x8960 | |
6d7190f8 TF |
30 | #define EPLL_LOCK 0xc010 |
31 | #define VPLL_LOCK 0xc020 | |
32 | #define EPLL_CON0 0xc110 | |
33 | #define EPLL_CON1 0xc114 | |
34 | #define EPLL_CON2 0xc118 | |
35 | #define VPLL_CON0 0xc120 | |
36 | #define VPLL_CON1 0xc124 | |
37 | #define VPLL_CON2 0xc128 | |
e062b571 TA |
38 | #define SRC_TOP0 0xc210 |
39 | #define SRC_TOP1 0xc214 | |
40 | #define SRC_CAM 0xc220 | |
41 | #define SRC_TV 0xc224 | |
42 | #define SRC_MFC 0xcc28 | |
43 | #define SRC_G3D 0xc22c | |
44 | #define E4210_SRC_IMAGE 0xc230 | |
45 | #define SRC_LCD0 0xc234 | |
7406ee7c | 46 | #define E4210_SRC_LCD1 0xc238 |
15547015 | 47 | #define E4X12_SRC_ISP 0xc238 |
e062b571 TA |
48 | #define SRC_MAUDIO 0xc23c |
49 | #define SRC_FSYS 0xc240 | |
50 | #define SRC_PERIL0 0xc250 | |
51 | #define SRC_PERIL1 0xc254 | |
52 | #define E4X12_SRC_CAM1 0xc258 | |
fb948f74 | 53 | #define SRC_MASK_TOP 0xc310 |
e062b571 TA |
54 | #define SRC_MASK_CAM 0xc320 |
55 | #define SRC_MASK_TV 0xc324 | |
56 | #define SRC_MASK_LCD0 0xc334 | |
7406ee7c | 57 | #define E4210_SRC_MASK_LCD1 0xc338 |
15547015 | 58 | #define E4X12_SRC_MASK_ISP 0xc338 |
e062b571 TA |
59 | #define SRC_MASK_MAUDIO 0xc33c |
60 | #define SRC_MASK_FSYS 0xc340 | |
61 | #define SRC_MASK_PERIL0 0xc350 | |
62 | #define SRC_MASK_PERIL1 0xc354 | |
63 | #define DIV_TOP 0xc510 | |
64 | #define DIV_CAM 0xc520 | |
65 | #define DIV_TV 0xc524 | |
66 | #define DIV_MFC 0xc528 | |
67 | #define DIV_G3D 0xc52c | |
68 | #define DIV_IMAGE 0xc530 | |
69 | #define DIV_LCD0 0xc534 | |
70 | #define E4210_DIV_LCD1 0xc538 | |
71 | #define E4X12_DIV_ISP 0xc538 | |
72 | #define DIV_MAUDIO 0xc53c | |
73 | #define DIV_FSYS0 0xc540 | |
74 | #define DIV_FSYS1 0xc544 | |
75 | #define DIV_FSYS2 0xc548 | |
76 | #define DIV_FSYS3 0xc54c | |
77 | #define DIV_PERIL0 0xc550 | |
78 | #define DIV_PERIL1 0xc554 | |
79 | #define DIV_PERIL2 0xc558 | |
80 | #define DIV_PERIL3 0xc55c | |
81 | #define DIV_PERIL4 0xc560 | |
82 | #define DIV_PERIL5 0xc564 | |
83 | #define E4X12_DIV_CAM1 0xc568 | |
84 | #define GATE_SCLK_CAM 0xc820 | |
85 | #define GATE_IP_CAM 0xc920 | |
86 | #define GATE_IP_TV 0xc924 | |
87 | #define GATE_IP_MFC 0xc928 | |
88 | #define GATE_IP_G3D 0xc92c | |
89 | #define E4210_GATE_IP_IMAGE 0xc930 | |
90 | #define GATE_IP_LCD0 0xc934 | |
7406ee7c | 91 | #define E4210_GATE_IP_LCD1 0xc938 |
15547015 | 92 | #define E4X12_GATE_IP_ISP 0xc938 |
e062b571 TA |
93 | #define E4X12_GATE_IP_MAUDIO 0xc93c |
94 | #define GATE_IP_FSYS 0xc940 | |
95 | #define GATE_IP_GPS 0xc94c | |
96 | #define GATE_IP_PERIL 0xc950 | |
1f1f3267 | 97 | #define E4210_GATE_IP_PERIR 0xc960 |
fb948f74 | 98 | #define GATE_BLOCK 0xc970 |
160641e7 | 99 | #define E4X12_MPLL_LOCK 0x10008 |
e062b571 | 100 | #define E4X12_MPLL_CON0 0x10108 |
b950622b | 101 | #define SRC_DMC 0x10200 |
fb948f74 TF |
102 | #define SRC_MASK_DMC 0x10300 |
103 | #define DIV_DMC0 0x10500 | |
104 | #define DIV_DMC1 0x10504 | |
105 | #define GATE_IP_DMC 0x10900 | |
160641e7 | 106 | #define APLL_LOCK 0x14000 |
52b06016 | 107 | #define E4210_MPLL_LOCK 0x14008 |
e062b571 TA |
108 | #define APLL_CON0 0x14100 |
109 | #define E4210_MPLL_CON0 0x14108 | |
110 | #define SRC_CPU 0x14200 | |
111 | #define DIV_CPU0 0x14500 | |
fb948f74 TF |
112 | #define DIV_CPU1 0x14504 |
113 | #define GATE_SCLK_CPU 0x14800 | |
114 | #define GATE_IP_CPU 0x14900 | |
15547015 AH |
115 | #define E4X12_DIV_ISP0 0x18300 |
116 | #define E4X12_DIV_ISP1 0x18304 | |
1e25810b | 117 | #define E4X12_GATE_ISP0 0x18800 |
15547015 | 118 | #define E4X12_GATE_ISP1 0x18804 |
e062b571 TA |
119 | |
120 | /* the exynos4 soc type */ | |
121 | enum exynos4_soc { | |
122 | EXYNOS4210, | |
123 | EXYNOS4X12, | |
124 | }; | |
125 | ||
160641e7 YSB |
126 | /* list of PLLs to be registered */ |
127 | enum exynos4_plls { | |
128 | apll, mpll, epll, vpll, | |
129 | nr_plls /* number of PLLs */ | |
130 | }; | |
131 | ||
e062b571 TA |
132 | /* |
133 | * Let each supported clock get a unique id. This id is used to lookup the clock | |
134 | * for device tree based platforms. The clocks are categorized into three | |
135 | * sections: core, sclk gate and bus interface gate clocks. | |
136 | * | |
137 | * When adding a new clock to this list, it is advised to choose a clock | |
138 | * category and add it to the end of that category. That is because the the | |
139 | * device tree source file is referring to these ids and any change in the | |
140 | * sequence number of existing clocks will require corresponding change in the | |
141 | * device tree files. This limitation would go away when pre-processor support | |
142 | * for dtc would be available. | |
143 | */ | |
144 | enum exynos4_clks { | |
145 | none, | |
146 | ||
147 | /* core clocks */ | |
148 | xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll, | |
149 | sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100, | |
e77ba804 LM |
150 | aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core, |
151 | mout_apll, /* 20 */ | |
e062b571 TA |
152 | |
153 | /* gate for special clocks (sclk) */ | |
154 | sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0, | |
155 | sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac, | |
156 | sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0, | |
157 | sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4, | |
158 | sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4, | |
159 | sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, | |
160 | sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, | |
15547015 | 161 | sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, |
5cd644d8 | 162 | sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d, |
e062b571 TA |
163 | |
164 | /* gate clocks */ | |
165 | fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, | |
166 | smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi, | |
167 | smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d, | |
168 | smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1, | |
169 | mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0, | |
170 | sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie, | |
171 | onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3, | |
172 | uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, | |
173 | spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus, | |
174 | spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif, | |
1e25810b | 175 | audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0, |
15547015 AH |
176 | fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp, |
177 | gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, | |
178 | mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, | |
179 | asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, | |
9f271369 | 180 | spi1_isp_sclk, uart_isp_sclk, tmu_apbif, |
1e25810b SN |
181 | |
182 | /* mux clocks */ | |
183 | mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, | |
8e1ce839 | 184 | mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d, |
cdbf618a SN |
185 | aclk400_mcuisp, |
186 | ||
187 | /* div clocks */ | |
188 | div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200, | |
189 | div_aclk400_mcuisp, | |
e062b571 TA |
190 | |
191 | nr_clks, | |
192 | }; | |
193 | ||
194 | /* | |
195 | * list of controller registers to be saved and restored during a | |
196 | * suspend/resume cycle. | |
197 | */ | |
3c701c51 | 198 | static unsigned long exynos4210_clk_save[] __initdata = { |
6b5756e8 TF |
199 | E4210_SRC_IMAGE, |
200 | E4210_SRC_LCD1, | |
201 | E4210_SRC_MASK_LCD1, | |
202 | E4210_DIV_LCD1, | |
203 | E4210_GATE_IP_IMAGE, | |
204 | E4210_GATE_IP_LCD1, | |
205 | E4210_GATE_IP_PERIR, | |
206 | E4210_MPLL_CON0, | |
207 | }; | |
208 | ||
3c701c51 | 209 | static unsigned long exynos4x12_clk_save[] __initdata = { |
6b5756e8 TF |
210 | E4X12_GATE_IP_IMAGE, |
211 | E4X12_GATE_IP_PERIR, | |
212 | E4X12_SRC_CAM1, | |
213 | E4X12_DIV_ISP, | |
214 | E4X12_DIV_CAM1, | |
215 | E4X12_MPLL_CON0, | |
216 | }; | |
217 | ||
3c701c51 | 218 | static unsigned long exynos4_clk_regs[] __initdata = { |
e062b571 | 219 | SRC_LEFTBUS, |
fb948f74 TF |
220 | DIV_LEFTBUS, |
221 | GATE_IP_LEFTBUS, | |
222 | SRC_RIGHTBUS, | |
223 | DIV_RIGHTBUS, | |
e062b571 | 224 | GATE_IP_RIGHTBUS, |
fb948f74 TF |
225 | EPLL_CON0, |
226 | EPLL_CON1, | |
227 | EPLL_CON2, | |
228 | VPLL_CON0, | |
229 | VPLL_CON1, | |
230 | VPLL_CON2, | |
e062b571 TA |
231 | SRC_TOP0, |
232 | SRC_TOP1, | |
233 | SRC_CAM, | |
234 | SRC_TV, | |
235 | SRC_MFC, | |
236 | SRC_G3D, | |
e062b571 | 237 | SRC_LCD0, |
e062b571 TA |
238 | SRC_MAUDIO, |
239 | SRC_FSYS, | |
240 | SRC_PERIL0, | |
241 | SRC_PERIL1, | |
fb948f74 | 242 | SRC_MASK_TOP, |
e062b571 TA |
243 | SRC_MASK_CAM, |
244 | SRC_MASK_TV, | |
245 | SRC_MASK_LCD0, | |
e062b571 TA |
246 | SRC_MASK_MAUDIO, |
247 | SRC_MASK_FSYS, | |
248 | SRC_MASK_PERIL0, | |
249 | SRC_MASK_PERIL1, | |
250 | DIV_TOP, | |
251 | DIV_CAM, | |
252 | DIV_TV, | |
253 | DIV_MFC, | |
254 | DIV_G3D, | |
255 | DIV_IMAGE, | |
256 | DIV_LCD0, | |
e062b571 TA |
257 | DIV_MAUDIO, |
258 | DIV_FSYS0, | |
259 | DIV_FSYS1, | |
260 | DIV_FSYS2, | |
261 | DIV_FSYS3, | |
262 | DIV_PERIL0, | |
263 | DIV_PERIL1, | |
264 | DIV_PERIL2, | |
265 | DIV_PERIL3, | |
266 | DIV_PERIL4, | |
267 | DIV_PERIL5, | |
e062b571 TA |
268 | GATE_SCLK_CAM, |
269 | GATE_IP_CAM, | |
270 | GATE_IP_TV, | |
271 | GATE_IP_MFC, | |
272 | GATE_IP_G3D, | |
e062b571 | 273 | GATE_IP_LCD0, |
e062b571 TA |
274 | GATE_IP_FSYS, |
275 | GATE_IP_GPS, | |
276 | GATE_IP_PERIL, | |
fb948f74 TF |
277 | GATE_BLOCK, |
278 | SRC_MASK_DMC, | |
279 | SRC_DMC, | |
280 | DIV_DMC0, | |
281 | DIV_DMC1, | |
282 | GATE_IP_DMC, | |
e062b571 | 283 | APLL_CON0, |
e062b571 TA |
284 | SRC_CPU, |
285 | DIV_CPU0, | |
fb948f74 TF |
286 | DIV_CPU1, |
287 | GATE_SCLK_CPU, | |
288 | GATE_IP_CPU, | |
e062b571 TA |
289 | }; |
290 | ||
291 | /* list of all parent clock list */ | |
292 | PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; | |
293 | PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; | |
294 | PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; | |
295 | PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; | |
e062b571 | 296 | PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; |
e062b571 TA |
297 | PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; |
298 | PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; | |
299 | PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; | |
300 | PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; | |
e062b571 TA |
301 | PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; |
302 | PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; | |
e062b571 TA |
303 | PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", |
304 | "spdif_extclk", }; | |
15547015 AH |
305 | PNAME(mout_onenand_p) = {"aclk133", "aclk160", }; |
306 | PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", }; | |
e062b571 | 307 | |
74f7f8ba TF |
308 | /* Exynos 4210-specific parent groups */ |
309 | PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; | |
310 | PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; | |
311 | PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; | |
312 | PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", | |
313 | "sclk_usbphy0", "none", "sclk_hdmiphy", | |
314 | "sclk_mpll", "sclk_epll", "sclk_vpll", }; | |
315 | PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", | |
316 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
317 | "sclk_epll", "sclk_vpll" }; | |
318 | PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", | |
319 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
320 | "sclk_epll", "sclk_vpll", }; | |
321 | PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", | |
322 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
323 | "sclk_epll", "sclk_vpll", }; | |
324 | PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; | |
325 | PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; | |
326 | ||
327 | /* Exynos 4x12-specific parent groups */ | |
328 | PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; | |
329 | PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; | |
330 | PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; | |
331 | PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", | |
332 | "none", "sclk_hdmiphy", "mout_mpll_user_t", | |
333 | "sclk_epll", "sclk_vpll", }; | |
334 | PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", | |
335 | "sclk_usbphy0", "xxti", "xusbxti", | |
336 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; | |
337 | PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", | |
338 | "sclk_usbphy0", "xxti", "xusbxti", | |
339 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; | |
340 | PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", | |
341 | "sclk_usbphy0", "xxti", "xusbxti", | |
342 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; | |
343 | PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; | |
15547015 AH |
344 | PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; |
345 | PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; | |
346 | PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; | |
74f7f8ba | 347 | |
e062b571 | 348 | /* fixed rate clocks generated outside the soc */ |
d75f3063 | 349 | static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { |
e062b571 TA |
350 | FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), |
351 | FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), | |
352 | }; | |
353 | ||
354 | /* fixed rate clocks generated inside the soc */ | |
d75f3063 | 355 | static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { |
e062b571 TA |
356 | FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), |
357 | FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), | |
358 | FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), | |
359 | }; | |
360 | ||
d75f3063 | 361 | static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { |
e062b571 TA |
362 | FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), |
363 | }; | |
364 | ||
365 | /* list of mux clocks supported in all exynos4 soc's */ | |
d75f3063 | 366 | static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { |
82ba93b2 TB |
367 | MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, |
368 | CLK_SET_RATE_PARENT, 0, "mout_apll"), | |
e062b571 | 369 | MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), |
e062b571 TA |
370 | MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), |
371 | MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), | |
8e1ce839 TF |
372 | MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, |
373 | CLK_SET_RATE_PARENT, 0), | |
374 | MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, | |
375 | CLK_SET_RATE_PARENT, 0), | |
e062b571 | 376 | MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), |
15547015 | 377 | MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), |
a11a2f8f | 378 | MUX(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), |
15547015 | 379 | MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), |
e062b571 TA |
380 | }; |
381 | ||
382 | /* list of mux clocks supported in exynos4210 soc */ | |
4f7641f5 TF |
383 | static struct samsung_mux_clock exynos4210_mux_early[] __initdata = { |
384 | MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), | |
385 | }; | |
386 | ||
d75f3063 | 387 | static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { |
74f7f8ba TF |
388 | MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), |
389 | MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), | |
390 | MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), | |
391 | MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), | |
e062b571 TA |
392 | MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), |
393 | MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), | |
74f7f8ba | 394 | MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), |
e062b571 TA |
395 | MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), |
396 | MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), | |
7406ee7c TF |
397 | MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), |
398 | MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), | |
e6c3e730 TF |
399 | MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), |
400 | MUX(mout_core, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), | |
a11a2f8f | 401 | MUX(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), |
1e25810b SN |
402 | MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), |
403 | MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), | |
404 | MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), | |
405 | MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), | |
406 | MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), | |
407 | MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), | |
408 | MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), | |
409 | MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), | |
74f7f8ba | 410 | MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), |
8e1ce839 TF |
411 | MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, |
412 | CLK_SET_RATE_PARENT, 0), | |
74f7f8ba TF |
413 | MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), |
414 | MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), | |
415 | MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), | |
416 | MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), | |
417 | MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), | |
418 | MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), | |
419 | MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), | |
420 | MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), | |
8e79561c | 421 | MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), |
74f7f8ba TF |
422 | MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), |
423 | MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), | |
424 | MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), | |
425 | MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), | |
426 | MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), | |
427 | MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), | |
428 | MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), | |
429 | MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), | |
430 | MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), | |
431 | MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), | |
e062b571 TA |
432 | }; |
433 | ||
434 | /* list of mux clocks supported in exynos4x12 soc */ | |
d75f3063 | 435 | static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { |
e6c3e730 TF |
436 | MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, |
437 | SRC_CPU, 24, 1), | |
15547015 AH |
438 | MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), |
439 | MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), | |
74f7f8ba TF |
440 | MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, |
441 | SRC_TOP1, 12, 1), | |
15547015 AH |
442 | MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, |
443 | SRC_TOP1, 16, 1), | |
444 | MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), | |
cdbf618a | 445 | MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12, |
15547015 | 446 | SRC_TOP1, 24, 1), |
e062b571 TA |
447 | MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), |
448 | MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), | |
449 | MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), | |
450 | MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), | |
74f7f8ba TF |
451 | MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), |
452 | MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), | |
453 | MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), | |
454 | MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), | |
e062b571 TA |
455 | MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), |
456 | MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), | |
a11a2f8f TF |
457 | MUX(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), |
458 | MUX(sclk_vpll, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), | |
e6c3e730 | 459 | MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), |
1e25810b SN |
460 | MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), |
461 | MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), | |
462 | MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), | |
463 | MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), | |
464 | MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), | |
465 | MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), | |
466 | MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), | |
467 | MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), | |
74f7f8ba | 468 | MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), |
8e1ce839 TF |
469 | MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, |
470 | CLK_SET_RATE_PARENT, 0), | |
74f7f8ba TF |
471 | MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), |
472 | MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), | |
473 | MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), | |
474 | MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), | |
475 | MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), | |
476 | MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), | |
477 | MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), | |
478 | MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), | |
4c3cc72c | 479 | MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), |
74f7f8ba TF |
480 | MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), |
481 | MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), | |
482 | MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), | |
483 | MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), | |
484 | MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), | |
485 | MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), | |
486 | MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), | |
487 | MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), | |
488 | MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), | |
489 | MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), | |
15547015 AH |
490 | MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), |
491 | MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), | |
492 | MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), | |
493 | MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), | |
5cd644d8 SK |
494 | MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), |
495 | MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), | |
496 | MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), | |
e062b571 TA |
497 | }; |
498 | ||
499 | /* list of divider clocks supported in all exynos4 soc's */ | |
d75f3063 | 500 | static struct samsung_div_clock exynos4_div_clks[] __initdata = { |
e062b571 TA |
501 | DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), |
502 | DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), | |
503 | DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), | |
504 | DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), | |
505 | DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), | |
506 | DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), | |
507 | DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), | |
508 | DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), | |
509 | DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), | |
510 | DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), | |
36fc0972 | 511 | DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), |
8e1ce839 TF |
512 | DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, |
513 | CLK_SET_RATE_PARENT, 0), | |
e062b571 TA |
514 | DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), |
515 | DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), | |
516 | DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), | |
6976d274 | 517 | DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), |
e062b571 TA |
518 | DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), |
519 | DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), | |
520 | DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), | |
521 | DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), | |
522 | DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), | |
e062b571 TA |
523 | DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), |
524 | DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), | |
525 | DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), | |
15547015 | 526 | DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), |
e062b571 TA |
527 | DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), |
528 | DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), | |
529 | DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), | |
530 | DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), | |
531 | DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), | |
532 | DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), | |
533 | DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), | |
534 | DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), | |
535 | DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), | |
536 | DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), | |
537 | DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), | |
538 | DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), | |
539 | DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), | |
540 | DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), | |
541 | DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), | |
542 | DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), | |
543 | DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), | |
544 | DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), | |
545 | DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), | |
546 | DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), | |
e6c3e730 | 547 | DIV(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3), |
a11a2f8f | 548 | DIV(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), |
e062b571 TA |
549 | DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, |
550 | CLK_SET_RATE_PARENT, 0), | |
551 | DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, | |
552 | CLK_SET_RATE_PARENT, 0), | |
553 | DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, | |
554 | CLK_SET_RATE_PARENT, 0), | |
555 | DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, | |
556 | CLK_SET_RATE_PARENT, 0), | |
557 | DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, | |
558 | CLK_SET_RATE_PARENT, 0), | |
559 | }; | |
560 | ||
561 | /* list of divider clocks supported in exynos4210 soc */ | |
d75f3063 | 562 | static struct samsung_div_clock exynos4210_div_clks[] __initdata = { |
15547015 | 563 | DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), |
5cd644d8 | 564 | DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), |
e062b571 TA |
565 | DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), |
566 | DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), | |
567 | DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), | |
568 | DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, | |
569 | CLK_SET_RATE_PARENT, 0), | |
570 | }; | |
571 | ||
572 | /* list of divider clocks supported in exynos4x12 soc */ | |
d75f3063 | 573 | static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { |
e062b571 TA |
574 | DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), |
575 | DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), | |
576 | DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), | |
577 | DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), | |
578 | DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), | |
cdbf618a | 579 | DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), |
15547015 | 580 | DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), |
cdbf618a SN |
581 | DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", |
582 | DIV_TOP, 24, 3), | |
15547015 AH |
583 | DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), |
584 | DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), | |
585 | DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), | |
586 | DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), | |
587 | DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), | |
588 | DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), | |
a701fe38 SN |
589 | DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, |
590 | CLK_GET_RATE_NOCACHE, 0), | |
591 | DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, | |
592 | CLK_GET_RATE_NOCACHE, 0), | |
15547015 | 593 | DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), |
a701fe38 SN |
594 | DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, |
595 | 4, 3, CLK_GET_RATE_NOCACHE, 0), | |
596 | DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, | |
597 | 8, 3, CLK_GET_RATE_NOCACHE, 0), | |
5cd644d8 | 598 | DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), |
e062b571 TA |
599 | }; |
600 | ||
601 | /* list of gate clocks supported in all exynos4 soc's */ | |
d75f3063 | 602 | static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { |
e062b571 TA |
603 | /* |
604 | * After all Exynos4 based platforms are migrated to use device tree, | |
605 | * the device name and clock alias names specified below for some | |
606 | * of the clocks can be removed. | |
607 | */ | |
608 | GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), | |
017ab64b | 609 | GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0), |
e062b571 TA |
610 | GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), |
611 | GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), | |
612 | GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), | |
7406ee7c TF |
613 | GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), |
614 | GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), | |
615 | GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), | |
616 | GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0), | |
e062b571 TA |
617 | GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), |
618 | GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), | |
8e1ce839 TF |
619 | GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, |
620 | CLK_SET_RATE_PARENT, 0), | |
e062b571 TA |
621 | GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), |
622 | GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), | |
623 | GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), | |
624 | GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), | |
625 | GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), | |
626 | GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), | |
627 | GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, | |
628 | CLK_SET_RATE_PARENT, 0), | |
629 | GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, | |
630 | CLK_SET_RATE_PARENT, 0), | |
631 | GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0", | |
632 | SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), | |
69aff2fd TF |
633 | GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, |
634 | CLK_SET_RATE_PARENT, 0), | |
017ab64b | 635 | GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, |
e062b571 | 636 | CLK_SET_RATE_PARENT, 0), |
a11a2f8f TF |
637 | GATE(vp, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), |
638 | GATE(mixer, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), | |
639 | GATE(hdmi, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), | |
640 | GATE(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), | |
641 | GATE(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), | |
642 | GATE(usb_host, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), | |
643 | GATE(sclk_fimc0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, | |
644 | CLK_SET_RATE_PARENT, 0), | |
645 | GATE(sclk_fimc1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, | |
646 | CLK_SET_RATE_PARENT, 0), | |
647 | GATE(sclk_fimc2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, | |
648 | CLK_SET_RATE_PARENT, 0), | |
649 | GATE(sclk_fimc3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, | |
650 | CLK_SET_RATE_PARENT, 0), | |
651 | GATE(sclk_csis0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, | |
652 | CLK_SET_RATE_PARENT, 0), | |
653 | GATE(sclk_csis1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, | |
654 | CLK_SET_RATE_PARENT, 0), | |
655 | GATE(sclk_fimd0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, | |
656 | CLK_SET_RATE_PARENT, 0), | |
657 | GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, | |
658 | CLK_SET_RATE_PARENT, 0), | |
659 | GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, | |
660 | CLK_SET_RATE_PARENT, 0), | |
661 | GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, | |
662 | CLK_SET_RATE_PARENT, 0), | |
663 | GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, | |
664 | CLK_SET_RATE_PARENT, 0), | |
665 | GATE(sclk_mmc4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, | |
666 | CLK_SET_RATE_PARENT, 0), | |
667 | GATE(sclk_uart0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, | |
668 | CLK_SET_RATE_PARENT, 0), | |
669 | GATE(sclk_uart1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, | |
670 | CLK_SET_RATE_PARENT, 0), | |
671 | GATE(sclk_uart2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, | |
672 | CLK_SET_RATE_PARENT, 0), | |
673 | GATE(sclk_uart3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, | |
674 | CLK_SET_RATE_PARENT, 0), | |
675 | GATE(sclk_uart4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, | |
676 | CLK_SET_RATE_PARENT, 0), | |
017ab64b | 677 | GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, |
e062b571 | 678 | CLK_SET_RATE_PARENT, 0), |
a11a2f8f TF |
679 | GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, |
680 | CLK_SET_RATE_PARENT, 0), | |
681 | GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, | |
682 | CLK_SET_RATE_PARENT, 0), | |
683 | GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, | |
684 | CLK_SET_RATE_PARENT, 0), | |
685 | GATE(fimc0, "fimc0", "aclk160", GATE_IP_CAM, 0, | |
686 | 0, 0), | |
687 | GATE(fimc1, "fimc1", "aclk160", GATE_IP_CAM, 1, | |
688 | 0, 0), | |
689 | GATE(fimc2, "fimc2", "aclk160", GATE_IP_CAM, 2, | |
690 | 0, 0), | |
691 | GATE(fimc3, "fimc3", "aclk160", GATE_IP_CAM, 3, | |
692 | 0, 0), | |
693 | GATE(csis0, "csis0", "aclk160", GATE_IP_CAM, 4, | |
694 | 0, 0), | |
695 | GATE(csis1, "csis1", "aclk160", GATE_IP_CAM, 5, | |
696 | 0, 0), | |
697 | GATE(smmu_fimc0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, | |
698 | 0, 0), | |
699 | GATE(smmu_fimc1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, | |
700 | 0, 0), | |
701 | GATE(smmu_fimc2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, | |
702 | 0, 0), | |
703 | GATE(smmu_fimc3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, | |
704 | 0, 0), | |
705 | GATE(smmu_jpeg, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, | |
706 | 0, 0), | |
1e25810b SN |
707 | GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), |
708 | GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), | |
a11a2f8f TF |
709 | GATE(smmu_tv, "smmu_tv", "aclk160", GATE_IP_TV, 4, |
710 | 0, 0), | |
711 | GATE(mfc, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), | |
712 | GATE(smmu_mfcl, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, | |
713 | 0, 0), | |
714 | GATE(smmu_mfcr, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, | |
715 | 0, 0), | |
716 | GATE(fimd0, "fimd0", "aclk160", GATE_IP_LCD0, 0, | |
717 | 0, 0), | |
718 | GATE(smmu_fimd0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, | |
719 | 0, 0), | |
720 | GATE(pdma0, "pdma0", "aclk133", GATE_IP_FSYS, 0, | |
721 | 0, 0), | |
722 | GATE(pdma1, "pdma1", "aclk133", GATE_IP_FSYS, 1, | |
723 | 0, 0), | |
724 | GATE(sdmmc0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, | |
725 | 0, 0), | |
726 | GATE(sdmmc1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, | |
727 | 0, 0), | |
728 | GATE(sdmmc2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, | |
729 | 0, 0), | |
730 | GATE(sdmmc3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, | |
731 | 0, 0), | |
732 | GATE(uart0, "uart0", "aclk100", GATE_IP_PERIL, 0, | |
733 | 0, 0), | |
734 | GATE(uart1, "uart1", "aclk100", GATE_IP_PERIL, 1, | |
735 | 0, 0), | |
736 | GATE(uart2, "uart2", "aclk100", GATE_IP_PERIL, 2, | |
737 | 0, 0), | |
738 | GATE(uart3, "uart3", "aclk100", GATE_IP_PERIL, 3, | |
739 | 0, 0), | |
740 | GATE(uart4, "uart4", "aclk100", GATE_IP_PERIL, 4, | |
741 | 0, 0), | |
742 | GATE(i2c0, "i2c0", "aclk100", GATE_IP_PERIL, 6, | |
743 | 0, 0), | |
744 | GATE(i2c1, "i2c1", "aclk100", GATE_IP_PERIL, 7, | |
745 | 0, 0), | |
746 | GATE(i2c2, "i2c2", "aclk100", GATE_IP_PERIL, 8, | |
747 | 0, 0), | |
748 | GATE(i2c3, "i2c3", "aclk100", GATE_IP_PERIL, 9, | |
749 | 0, 0), | |
750 | GATE(i2c4, "i2c4", "aclk100", GATE_IP_PERIL, 10, | |
751 | 0, 0), | |
752 | GATE(i2c5, "i2c5", "aclk100", GATE_IP_PERIL, 11, | |
753 | 0, 0), | |
754 | GATE(i2c6, "i2c6", "aclk100", GATE_IP_PERIL, 12, | |
755 | 0, 0), | |
756 | GATE(i2c7, "i2c7", "aclk100", GATE_IP_PERIL, 13, | |
757 | 0, 0), | |
758 | GATE(i2c_hdmi, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, | |
759 | 0, 0), | |
760 | GATE(spi0, "spi0", "aclk100", GATE_IP_PERIL, 16, | |
761 | 0, 0), | |
762 | GATE(spi1, "spi1", "aclk100", GATE_IP_PERIL, 17, | |
763 | 0, 0), | |
764 | GATE(spi2, "spi2", "aclk100", GATE_IP_PERIL, 18, | |
765 | 0, 0), | |
766 | GATE(i2s1, "i2s1", "aclk100", GATE_IP_PERIL, 20, | |
767 | 0, 0), | |
768 | GATE(i2s2, "i2s2", "aclk100", GATE_IP_PERIL, 21, | |
769 | 0, 0), | |
770 | GATE(pcm1, "pcm1", "aclk100", GATE_IP_PERIL, 22, | |
771 | 0, 0), | |
772 | GATE(pcm2, "pcm2", "aclk100", GATE_IP_PERIL, 23, | |
773 | 0, 0), | |
774 | GATE(spdif, "spdif", "aclk100", GATE_IP_PERIL, 26, | |
775 | 0, 0), | |
776 | GATE(ac97, "ac97", "aclk100", GATE_IP_PERIL, 27, | |
777 | 0, 0), | |
e062b571 TA |
778 | }; |
779 | ||
780 | /* list of gate clocks supported in exynos4210 soc */ | |
d75f3063 | 781 | static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { |
e062b571 TA |
782 | GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), |
783 | GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), | |
784 | GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), | |
785 | GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), | |
786 | GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), | |
787 | GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0), | |
788 | GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), | |
789 | GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), | |
790 | GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), | |
791 | GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), | |
792 | GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), | |
793 | GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), | |
1f1f3267 | 794 | GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), |
056f3d58 SN |
795 | GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, |
796 | CLK_IGNORE_UNUSED, 0), | |
1f1f3267 | 797 | GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), |
e062b571 TA |
798 | GATE(smmu_rotator, "smmu_rotator", "aclk200", |
799 | E4210_GATE_IP_IMAGE, 4, 0, 0), | |
800 | GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", | |
7406ee7c | 801 | E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), |
e062b571 TA |
802 | GATE(sclk_sata, "sclk_sata", "div_sata", |
803 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), | |
7bc1d2da TF |
804 | GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), |
805 | GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), | |
a11a2f8f TF |
806 | GATE(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, |
807 | 0, 0), | |
808 | GATE(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, | |
809 | 0, 0), | |
810 | GATE(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, | |
811 | 0, 0), | |
812 | GATE(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, | |
813 | 0, 0), | |
814 | GATE(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, | |
815 | 0, 0), | |
816 | GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, | |
817 | CLK_SET_RATE_PARENT, 0), | |
9f271369 | 818 | GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0), |
e062b571 TA |
819 | }; |
820 | ||
821 | /* list of gate clocks supported in exynos4x12 soc */ | |
d75f3063 | 822 | static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { |
e062b571 TA |
823 | GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), |
824 | GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), | |
825 | GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), | |
826 | GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), | |
827 | GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), | |
828 | GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), | |
829 | GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), | |
056f3d58 SN |
830 | GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, |
831 | CLK_IGNORE_UNUSED, 0), | |
e062b571 TA |
832 | GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), |
833 | GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", | |
834 | SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), | |
835 | GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", | |
836 | SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), | |
837 | GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", | |
838 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), | |
839 | GATE(smmu_rotator, "smmu_rotator", "aclk200", | |
840 | E4X12_GATE_IP_IMAGE, 4, 0, 0), | |
a11a2f8f TF |
841 | GATE(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, |
842 | 0, 0), | |
843 | GATE(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, | |
844 | 0, 0), | |
845 | GATE(keyif, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), | |
15547015 AH |
846 | GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", |
847 | E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), | |
848 | GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre", | |
849 | E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), | |
850 | GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre", | |
851 | E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), | |
852 | GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp", | |
853 | E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), | |
854 | GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp", | |
855 | E4X12_GATE_IP_ISP, 0, 0, 0), | |
856 | GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp", | |
857 | E4X12_GATE_IP_ISP, 1, 0, 0), | |
858 | GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp", | |
859 | E4X12_GATE_IP_ISP, 2, 0, 0), | |
860 | GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp", | |
861 | E4X12_GATE_IP_ISP, 3, 0, 0), | |
a11a2f8f TF |
862 | GATE(wdt, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), |
863 | GATE(pcm0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, | |
864 | 0, 0), | |
865 | GATE(i2s0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, | |
866 | 0, 0), | |
15547015 | 867 | GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, |
a701fe38 | 868 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 869 | GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, |
a701fe38 | 870 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 871 | GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, |
a701fe38 | 872 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
1e25810b | 873 | GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, |
a701fe38 | 874 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
1e25810b | 875 | GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, |
a701fe38 | 876 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 877 | GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, |
a701fe38 | 878 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 879 | GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, |
a701fe38 | 880 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 881 | GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, |
a701fe38 | 882 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 883 | GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, |
a701fe38 | 884 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 885 | GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, |
a701fe38 | 886 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 887 | GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, |
a701fe38 | 888 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 889 | GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, |
a701fe38 | 890 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
1e25810b | 891 | GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, |
a701fe38 | 892 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
1e25810b | 893 | GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, |
a701fe38 | 894 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 895 | GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, |
a701fe38 | 896 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 897 | GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, |
a701fe38 | 898 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 899 | GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, |
a701fe38 | 900 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 901 | GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, |
a701fe38 | 902 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 903 | GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, |
a701fe38 | 904 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 905 | GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, |
a701fe38 | 906 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 907 | GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, |
a701fe38 | 908 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 909 | GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, |
a701fe38 | 910 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 911 | GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, |
a701fe38 | 912 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 913 | GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, |
a701fe38 | 914 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 915 | GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, |
a701fe38 | 916 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
15547015 | 917 | GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, |
a701fe38 | 918 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
5cd644d8 | 919 | GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), |
9f271369 | 920 | GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0), |
e062b571 TA |
921 | }; |
922 | ||
e6c3e730 TF |
923 | static struct samsung_clock_alias exynos4_aliases[] __initdata = { |
924 | ALIAS(mout_core, NULL, "moutcore"), | |
925 | ALIAS(arm_clk, NULL, "armclk"), | |
926 | ALIAS(sclk_apll, NULL, "mout_apll"), | |
927 | }; | |
928 | ||
929 | static struct samsung_clock_alias exynos4210_aliases[] __initdata = { | |
930 | ALIAS(sclk_mpll, NULL, "mout_mpll"), | |
931 | }; | |
932 | ||
933 | static struct samsung_clock_alias exynos4x12_aliases[] __initdata = { | |
934 | ALIAS(mout_mpll_user_c, NULL, "mout_mpll"), | |
e062b571 TA |
935 | }; |
936 | ||
e062b571 TA |
937 | /* |
938 | * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit | |
939 | * resides in chipid register space, outside of the clock controller memory | |
940 | * mapped space. So to determine the parent of fin_pll clock, the chipid | |
941 | * controller is first remapped and the value of XOM[0] bit is read to | |
942 | * determine the parent clock. | |
943 | */ | |
25e56eba | 944 | static unsigned long exynos4_get_xom(void) |
e062b571 | 945 | { |
25e56eba AB |
946 | unsigned long xom = 0; |
947 | void __iomem *chipid_base; | |
e062b571 | 948 | struct device_node *np; |
e062b571 TA |
949 | |
950 | np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); | |
25e56eba | 951 | if (np) { |
e062b571 TA |
952 | chipid_base = of_iomap(np, 0); |
953 | ||
25e56eba AB |
954 | if (chipid_base) |
955 | xom = readl(chipid_base + 8); | |
956 | ||
957 | iounmap(chipid_base); | |
958 | } | |
959 | ||
960 | return xom; | |
961 | } | |
962 | ||
963 | static void __init exynos4_clk_register_finpll(unsigned long xom) | |
964 | { | |
965 | struct samsung_fixed_rate_clock fclk; | |
966 | struct clk *clk; | |
967 | unsigned long finpll_f = 24000000; | |
968 | char *parent_name; | |
969 | ||
970 | parent_name = xom & 1 ? "xusbxti" : "xxti"; | |
971 | clk = clk_get(NULL, parent_name); | |
972 | if (IS_ERR(clk)) { | |
973 | pr_err("%s: failed to lookup parent clock %s, assuming " | |
974 | "fin_pll clock frequency is 24MHz\n", __func__, | |
975 | parent_name); | |
e062b571 | 976 | } else { |
25e56eba | 977 | finpll_f = clk_get_rate(clk); |
e062b571 TA |
978 | } |
979 | ||
980 | fclk.id = fin_pll; | |
981 | fclk.name = "fin_pll"; | |
982 | fclk.parent_name = NULL; | |
983 | fclk.flags = CLK_IS_ROOT; | |
984 | fclk.fixed_rate = finpll_f; | |
985 | samsung_clk_register_fixed_rate(&fclk, 1); | |
986 | ||
e062b571 TA |
987 | } |
988 | ||
3c701c51 | 989 | static struct of_device_id ext_clk_match[] __initdata = { |
e062b571 TA |
990 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, |
991 | { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, | |
992 | {}, | |
993 | }; | |
994 | ||
5fadfc7e TF |
995 | /* PLLs PMS values */ |
996 | static struct samsung_pll_rate_table exynos4210_apll_rates[] __initdata = { | |
997 | PLL_45XX_RATE(1200000000, 150, 3, 1, 28), | |
998 | PLL_45XX_RATE(1000000000, 250, 6, 1, 28), | |
999 | PLL_45XX_RATE( 800000000, 200, 6, 1, 28), | |
1000 | PLL_45XX_RATE( 666857142, 389, 14, 1, 13), | |
1001 | PLL_45XX_RATE( 600000000, 100, 4, 1, 13), | |
1002 | PLL_45XX_RATE( 533000000, 533, 24, 1, 5), | |
1003 | PLL_45XX_RATE( 500000000, 250, 6, 2, 28), | |
1004 | PLL_45XX_RATE( 400000000, 200, 6, 2, 28), | |
1005 | PLL_45XX_RATE( 200000000, 200, 6, 3, 28), | |
1006 | { /* sentinel */ } | |
1007 | }; | |
1008 | ||
1009 | static struct samsung_pll_rate_table exynos4210_epll_rates[] __initdata = { | |
1010 | PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), | |
1011 | PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), | |
1012 | PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), | |
1013 | PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), | |
1014 | PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), | |
1015 | PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), | |
1016 | PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), | |
1017 | { /* sentinel */ } | |
1018 | }; | |
1019 | ||
1020 | static struct samsung_pll_rate_table exynos4210_vpll_rates[] __initdata = { | |
1021 | PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), | |
1022 | PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), | |
1023 | PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), | |
1024 | PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), | |
1025 | PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), | |
1026 | { /* sentinel */ } | |
1027 | }; | |
1028 | ||
efb19a85 TF |
1029 | static struct samsung_pll_rate_table exynos4x12_apll_rates[] __initdata = { |
1030 | PLL_35XX_RATE(1500000000, 250, 4, 0), | |
1031 | PLL_35XX_RATE(1400000000, 175, 3, 0), | |
1032 | PLL_35XX_RATE(1300000000, 325, 6, 0), | |
1033 | PLL_35XX_RATE(1200000000, 200, 4, 0), | |
1034 | PLL_35XX_RATE(1100000000, 275, 6, 0), | |
1035 | PLL_35XX_RATE(1000000000, 125, 3, 0), | |
1036 | PLL_35XX_RATE( 900000000, 150, 4, 0), | |
1037 | PLL_35XX_RATE( 800000000, 100, 3, 0), | |
1038 | PLL_35XX_RATE( 700000000, 175, 3, 1), | |
1039 | PLL_35XX_RATE( 600000000, 200, 4, 1), | |
1040 | PLL_35XX_RATE( 500000000, 125, 3, 1), | |
1041 | PLL_35XX_RATE( 400000000, 100, 3, 1), | |
1042 | PLL_35XX_RATE( 300000000, 200, 4, 2), | |
1043 | PLL_35XX_RATE( 200000000, 100, 3, 2), | |
1044 | { /* sentinel */ } | |
1045 | }; | |
1046 | ||
1047 | static struct samsung_pll_rate_table exynos4x12_epll_rates[] __initdata = { | |
1048 | PLL_36XX_RATE(192000000, 48, 3, 1, 0), | |
1049 | PLL_36XX_RATE(180633605, 45, 3, 1, 10381), | |
1050 | PLL_36XX_RATE(180000000, 45, 3, 1, 0), | |
1051 | PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), | |
1052 | PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), | |
1053 | PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), | |
1054 | PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), | |
1055 | { /* sentinel */ } | |
1056 | }; | |
1057 | ||
1058 | static struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initdata = { | |
1059 | PLL_36XX_RATE(533000000, 133, 3, 1, 16384), | |
1060 | PLL_36XX_RATE(440000000, 110, 3, 1, 0), | |
1061 | PLL_36XX_RATE(350000000, 175, 3, 2, 0), | |
1062 | PLL_36XX_RATE(266000000, 133, 3, 2, 0), | |
1063 | PLL_36XX_RATE(160000000, 160, 3, 3, 0), | |
1064 | PLL_36XX_RATE(106031250, 53, 3, 2, 1024), | |
1065 | PLL_36XX_RATE( 53015625, 53, 3, 3, 1024), | |
1066 | { /* sentinel */ } | |
1067 | }; | |
1068 | ||
c50d11f3 | 1069 | static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { |
52b06016 TF |
1070 | [apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, |
1071 | APLL_CON0, "fout_apll", NULL), | |
1072 | [mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll", | |
1073 | E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), | |
c50d11f3 TF |
1074 | [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, |
1075 | EPLL_CON0, "fout_epll", NULL), | |
1076 | [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc", | |
1077 | VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), | |
52b06016 TF |
1078 | }; |
1079 | ||
c6415963 | 1080 | static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { |
a11a2f8f TF |
1081 | [apll] = PLL(pll_35xx, fout_apll, "fout_apll", "fin_pll", |
1082 | APLL_LOCK, APLL_CON0, NULL), | |
1083 | [mpll] = PLL(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", | |
1084 | E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), | |
1085 | [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", | |
1086 | EPLL_LOCK, EPLL_CON0, NULL), | |
1087 | [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "fin_pll", | |
1088 | VPLL_LOCK, VPLL_CON0, NULL), | |
160641e7 YSB |
1089 | }; |
1090 | ||
e062b571 | 1091 | /* register exynos4 clocks */ |
d75f3063 SK |
1092 | static void __init exynos4_clk_init(struct device_node *np, |
1093 | enum exynos4_soc exynos4_soc, | |
1094 | void __iomem *reg_base, unsigned long xom) | |
e062b571 | 1095 | { |
336c18bd TF |
1096 | reg_base = of_iomap(np, 0); |
1097 | if (!reg_base) | |
1098 | panic("%s: failed to map registers\n", __func__); | |
e062b571 | 1099 | |
6b5756e8 TF |
1100 | if (exynos4_soc == EXYNOS4210) |
1101 | samsung_clk_init(np, reg_base, nr_clks, | |
1102 | exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), | |
1103 | exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save)); | |
1104 | else | |
1105 | samsung_clk_init(np, reg_base, nr_clks, | |
1106 | exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), | |
1107 | exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); | |
e062b571 | 1108 | |
336c18bd | 1109 | samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, |
e062b571 TA |
1110 | ARRAY_SIZE(exynos4_fixed_rate_ext_clks), |
1111 | ext_clk_match); | |
1112 | ||
25e56eba | 1113 | exynos4_clk_register_finpll(xom); |
e062b571 TA |
1114 | |
1115 | if (exynos4_soc == EXYNOS4210) { | |
4f7641f5 TF |
1116 | samsung_clk_register_mux(exynos4210_mux_early, |
1117 | ARRAY_SIZE(exynos4210_mux_early)); | |
1118 | ||
5fadfc7e TF |
1119 | if (_get_rate("fin_pll") == 24000000) { |
1120 | exynos4210_plls[apll].rate_table = | |
1121 | exynos4210_apll_rates; | |
1122 | exynos4210_plls[epll].rate_table = | |
1123 | exynos4210_epll_rates; | |
1124 | } | |
1125 | ||
1126 | if (_get_rate("mout_vpllsrc") == 24000000) | |
1127 | exynos4210_plls[vpll].rate_table = | |
1128 | exynos4210_vpll_rates; | |
1129 | ||
52b06016 TF |
1130 | samsung_clk_register_pll(exynos4210_plls, |
1131 | ARRAY_SIZE(exynos4210_plls), reg_base); | |
e062b571 | 1132 | } else { |
efb19a85 TF |
1133 | if (_get_rate("fin_pll") == 24000000) { |
1134 | exynos4x12_plls[apll].rate_table = | |
1135 | exynos4x12_apll_rates; | |
1136 | exynos4x12_plls[epll].rate_table = | |
1137 | exynos4x12_epll_rates; | |
1138 | exynos4x12_plls[vpll].rate_table = | |
1139 | exynos4x12_vpll_rates; | |
1140 | } | |
e062b571 | 1141 | |
c6415963 TF |
1142 | samsung_clk_register_pll(exynos4x12_plls, |
1143 | ARRAY_SIZE(exynos4x12_plls), reg_base); | |
e062b571 | 1144 | } |
e062b571 TA |
1145 | |
1146 | samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, | |
1147 | ARRAY_SIZE(exynos4_fixed_rate_clks)); | |
1148 | samsung_clk_register_mux(exynos4_mux_clks, | |
1149 | ARRAY_SIZE(exynos4_mux_clks)); | |
1150 | samsung_clk_register_div(exynos4_div_clks, | |
1151 | ARRAY_SIZE(exynos4_div_clks)); | |
1152 | samsung_clk_register_gate(exynos4_gate_clks, | |
1153 | ARRAY_SIZE(exynos4_gate_clks)); | |
1154 | ||
1155 | if (exynos4_soc == EXYNOS4210) { | |
1156 | samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, | |
1157 | ARRAY_SIZE(exynos4210_fixed_rate_clks)); | |
1158 | samsung_clk_register_mux(exynos4210_mux_clks, | |
1159 | ARRAY_SIZE(exynos4210_mux_clks)); | |
1160 | samsung_clk_register_div(exynos4210_div_clks, | |
1161 | ARRAY_SIZE(exynos4210_div_clks)); | |
1162 | samsung_clk_register_gate(exynos4210_gate_clks, | |
1163 | ARRAY_SIZE(exynos4210_gate_clks)); | |
e6c3e730 TF |
1164 | samsung_clk_register_alias(exynos4210_aliases, |
1165 | ARRAY_SIZE(exynos4210_aliases)); | |
e062b571 TA |
1166 | } else { |
1167 | samsung_clk_register_mux(exynos4x12_mux_clks, | |
1168 | ARRAY_SIZE(exynos4x12_mux_clks)); | |
1169 | samsung_clk_register_div(exynos4x12_div_clks, | |
1170 | ARRAY_SIZE(exynos4x12_div_clks)); | |
1171 | samsung_clk_register_gate(exynos4x12_gate_clks, | |
1172 | ARRAY_SIZE(exynos4x12_gate_clks)); | |
e6c3e730 TF |
1173 | samsung_clk_register_alias(exynos4x12_aliases, |
1174 | ARRAY_SIZE(exynos4x12_aliases)); | |
e062b571 TA |
1175 | } |
1176 | ||
e6c3e730 TF |
1177 | samsung_clk_register_alias(exynos4_aliases, |
1178 | ARRAY_SIZE(exynos4_aliases)); | |
1179 | ||
e062b571 TA |
1180 | pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" |
1181 | "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", | |
1182 | exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", | |
3a647895 | 1183 | _get_rate("sclk_apll"), _get_rate("sclk_mpll"), |
e062b571 | 1184 | _get_rate("sclk_epll"), _get_rate("sclk_vpll"), |
3a647895 | 1185 | _get_rate("arm_clk")); |
e062b571 | 1186 | } |
25e56eba AB |
1187 | |
1188 | ||
1189 | static void __init exynos4210_clk_init(struct device_node *np) | |
1190 | { | |
1191 | exynos4_clk_init(np, EXYNOS4210, NULL, exynos4_get_xom()); | |
1192 | } | |
1193 | CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init); | |
1194 | ||
1195 | static void __init exynos4412_clk_init(struct device_node *np) | |
1196 | { | |
1197 | exynos4_clk_init(np, EXYNOS4X12, NULL, exynos4_get_xom()); | |
1198 | } | |
1199 | CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init); |