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1609027f CK |
1 | /* |
2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
3 | * Authors: Thomas Abraham <thomas.ab@samsung.com> | |
4 | * Chander Kashyap <k.chander@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Common Clock Framework support for Exynos5420 SoC. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/clkdev.h> | |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
18 | ||
19 | #include "clk.h" | |
1609027f | 20 | |
c898c6b7 YSB |
21 | #define APLL_LOCK 0x0 |
22 | #define APLL_CON0 0x100 | |
1609027f CK |
23 | #define SRC_CPU 0x200 |
24 | #define DIV_CPU0 0x500 | |
25 | #define DIV_CPU1 0x504 | |
26 | #define GATE_BUS_CPU 0x700 | |
27 | #define GATE_SCLK_CPU 0x800 | |
c898c6b7 YSB |
28 | #define CPLL_LOCK 0x10020 |
29 | #define DPLL_LOCK 0x10030 | |
30 | #define EPLL_LOCK 0x10040 | |
31 | #define RPLL_LOCK 0x10050 | |
32 | #define IPLL_LOCK 0x10060 | |
33 | #define SPLL_LOCK 0x10070 | |
34 | #define VPLL_LOCK 0x10070 | |
35 | #define MPLL_LOCK 0x10090 | |
36 | #define CPLL_CON0 0x10120 | |
37 | #define DPLL_CON0 0x10128 | |
38 | #define EPLL_CON0 0x10130 | |
39 | #define RPLL_CON0 0x10140 | |
40 | #define IPLL_CON0 0x10150 | |
41 | #define SPLL_CON0 0x10160 | |
42 | #define VPLL_CON0 0x10170 | |
43 | #define MPLL_CON0 0x10180 | |
1609027f CK |
44 | #define SRC_TOP0 0x10200 |
45 | #define SRC_TOP1 0x10204 | |
46 | #define SRC_TOP2 0x10208 | |
47 | #define SRC_TOP3 0x1020c | |
48 | #define SRC_TOP4 0x10210 | |
49 | #define SRC_TOP5 0x10214 | |
50 | #define SRC_TOP6 0x10218 | |
51 | #define SRC_TOP7 0x1021c | |
52 | #define SRC_DISP10 0x1022c | |
53 | #define SRC_MAU 0x10240 | |
54 | #define SRC_FSYS 0x10244 | |
55 | #define SRC_PERIC0 0x10250 | |
56 | #define SRC_PERIC1 0x10254 | |
57 | #define SRC_TOP10 0x10280 | |
58 | #define SRC_TOP11 0x10284 | |
59 | #define SRC_TOP12 0x10288 | |
60 | #define SRC_MASK_DISP10 0x1032c | |
61 | #define SRC_MASK_FSYS 0x10340 | |
62 | #define SRC_MASK_PERIC0 0x10350 | |
63 | #define SRC_MASK_PERIC1 0x10354 | |
64 | #define DIV_TOP0 0x10500 | |
65 | #define DIV_TOP1 0x10504 | |
66 | #define DIV_TOP2 0x10508 | |
67 | #define DIV_DISP10 0x1052c | |
68 | #define DIV_MAU 0x10544 | |
69 | #define DIV_FSYS0 0x10548 | |
70 | #define DIV_FSYS1 0x1054c | |
71 | #define DIV_FSYS2 0x10550 | |
72 | #define DIV_PERIC0 0x10558 | |
73 | #define DIV_PERIC1 0x1055c | |
74 | #define DIV_PERIC2 0x10560 | |
75 | #define DIV_PERIC3 0x10564 | |
76 | #define DIV_PERIC4 0x10568 | |
77 | #define GATE_BUS_TOP 0x10700 | |
78 | #define GATE_BUS_FSYS0 0x10740 | |
79 | #define GATE_BUS_PERIC 0x10750 | |
80 | #define GATE_BUS_PERIC1 0x10754 | |
81 | #define GATE_BUS_PERIS0 0x10760 | |
82 | #define GATE_BUS_PERIS1 0x10764 | |
83 | #define GATE_IP_GSCL0 0x10910 | |
84 | #define GATE_IP_GSCL1 0x10920 | |
85 | #define GATE_IP_MFC 0x1092c | |
86 | #define GATE_IP_DISP1 0x10928 | |
87 | #define GATE_IP_G3D 0x10930 | |
88 | #define GATE_IP_GEN 0x10934 | |
89 | #define GATE_IP_MSCL 0x10970 | |
90 | #define GATE_TOP_SCLK_GSCL 0x10820 | |
91 | #define GATE_TOP_SCLK_DISP1 0x10828 | |
92 | #define GATE_TOP_SCLK_MAU 0x1083c | |
93 | #define GATE_TOP_SCLK_FSYS 0x10840 | |
94 | #define GATE_TOP_SCLK_PERIC 0x10850 | |
c898c6b7 YSB |
95 | #define BPLL_LOCK 0x20010 |
96 | #define BPLL_CON0 0x20110 | |
1609027f | 97 | #define SRC_CDREX 0x20200 |
c898c6b7 YSB |
98 | #define KPLL_LOCK 0x28000 |
99 | #define KPLL_CON0 0x28100 | |
1609027f CK |
100 | #define SRC_KFC 0x28200 |
101 | #define DIV_KFC0 0x28500 | |
102 | ||
c898c6b7 YSB |
103 | /* list of PLLs */ |
104 | enum exynos5420_plls { | |
105 | apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, | |
106 | bpll, kpll, | |
107 | nr_plls /* number of PLLs */ | |
108 | }; | |
109 | ||
1609027f CK |
110 | enum exynos5420_clks { |
111 | none, | |
112 | ||
113 | /* core clocks */ | |
c898c6b7 YSB |
114 | fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll, |
115 | fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll, | |
1609027f CK |
116 | |
117 | /* gate for special clocks (sclk) */ | |
118 | sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0, | |
119 | sclk_mmc1, sclk_mmc2, sclk_spi0, sclk_spi1, sclk_spi2, sclk_i2s1, | |
120 | sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel, | |
121 | sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0, | |
122 | sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro, | |
c9f3f081 | 123 | sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy, |
1609027f CK |
124 | |
125 | /* gate clocks */ | |
126 | aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3, | |
127 | i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, spi0, spi1, spi2, keyif, i2s1, | |
128 | i2s2, pcm1, pcm2, pwm, spdif, i2c8, i2c9, i2c10, aclk66_psgen = 300, | |
129 | chipid, sysreg, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, | |
130 | tzpc8, tzpc9, hdmi_cec, seckey, mct, wdt, rtc, tmu, tmu_gpu, | |
131 | pclk66_gpio = 330, aclk200_fsys2 = 350, mmc0, mmc1, mmc2, sromc, ufs, | |
132 | aclk200_fsys = 360, tsi, pdma0, pdma1, rtic, usbh20, usbd300, usbd301, | |
133 | aclk400_mscl = 380, mscl0, mscl1, mscl2, smmu_mscl0, smmu_mscl1, | |
134 | smmu_mscl2, aclk333 = 400, mfc, smmu_mfcl, smmu_mfcr, | |
135 | aclk200_disp1 = 410, dsim1, dp1, hdmi, aclk300_disp1 = 420, fimd1, | |
136 | smmu_fimd1, aclk166 = 430, mixer, aclk266 = 440, rotator, mdma1, | |
137 | smmu_rotator, smmu_mdma1, aclk300_jpeg = 450, jpeg, jpeg2, smmu_jpeg, | |
138 | aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0, | |
139 | gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0, | |
140 | aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0, | |
9b229d8b | 141 | smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer, |
1609027f | 142 | |
4625f1b5 RS |
143 | /* mux clocks */ |
144 | mout_hdmi = 640, | |
145 | ||
0044cbcd RS |
146 | /* divider clocks */ |
147 | dout_pixel = 768, | |
148 | ||
1609027f CK |
149 | nr_clks, |
150 | }; | |
151 | ||
152 | /* | |
153 | * list of controller registers to be saved and restored during a | |
154 | * suspend/resume cycle. | |
155 | */ | |
202e5ae9 | 156 | static unsigned long exynos5420_clk_regs[] __initdata = { |
1609027f CK |
157 | SRC_CPU, |
158 | DIV_CPU0, | |
159 | DIV_CPU1, | |
160 | GATE_BUS_CPU, | |
161 | GATE_SCLK_CPU, | |
162 | SRC_TOP0, | |
163 | SRC_TOP1, | |
164 | SRC_TOP2, | |
165 | SRC_TOP3, | |
166 | SRC_TOP4, | |
167 | SRC_TOP5, | |
168 | SRC_TOP6, | |
169 | SRC_TOP7, | |
170 | SRC_DISP10, | |
171 | SRC_MAU, | |
172 | SRC_FSYS, | |
173 | SRC_PERIC0, | |
174 | SRC_PERIC1, | |
175 | SRC_TOP10, | |
176 | SRC_TOP11, | |
177 | SRC_TOP12, | |
178 | SRC_MASK_DISP10, | |
179 | SRC_MASK_FSYS, | |
180 | SRC_MASK_PERIC0, | |
181 | SRC_MASK_PERIC1, | |
182 | DIV_TOP0, | |
183 | DIV_TOP1, | |
184 | DIV_TOP2, | |
185 | DIV_DISP10, | |
186 | DIV_MAU, | |
187 | DIV_FSYS0, | |
188 | DIV_FSYS1, | |
189 | DIV_FSYS2, | |
190 | DIV_PERIC0, | |
191 | DIV_PERIC1, | |
192 | DIV_PERIC2, | |
193 | DIV_PERIC3, | |
194 | DIV_PERIC4, | |
195 | GATE_BUS_TOP, | |
196 | GATE_BUS_FSYS0, | |
197 | GATE_BUS_PERIC, | |
198 | GATE_BUS_PERIC1, | |
199 | GATE_BUS_PERIS0, | |
200 | GATE_BUS_PERIS1, | |
201 | GATE_IP_GSCL0, | |
202 | GATE_IP_GSCL1, | |
203 | GATE_IP_MFC, | |
204 | GATE_IP_DISP1, | |
205 | GATE_IP_G3D, | |
206 | GATE_IP_GEN, | |
207 | GATE_IP_MSCL, | |
208 | GATE_TOP_SCLK_GSCL, | |
209 | GATE_TOP_SCLK_DISP1, | |
210 | GATE_TOP_SCLK_MAU, | |
211 | GATE_TOP_SCLK_FSYS, | |
212 | GATE_TOP_SCLK_PERIC, | |
213 | SRC_CDREX, | |
214 | SRC_KFC, | |
215 | DIV_KFC0, | |
216 | }; | |
217 | ||
218 | /* list of all parent clocks */ | |
219 | PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll", | |
220 | "sclk_mpll", "sclk_spll" }; | |
221 | PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" }; | |
222 | PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" }; | |
223 | PNAME(apll_p) = { "fin_pll", "fout_apll", }; | |
224 | PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; | |
225 | PNAME(cpll_p) = { "fin_pll", "fout_cpll", }; | |
226 | PNAME(dpll_p) = { "fin_pll", "fout_dpll", }; | |
227 | PNAME(epll_p) = { "fin_pll", "fout_epll", }; | |
228 | PNAME(ipll_p) = { "fin_pll", "fout_ipll", }; | |
229 | PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; | |
230 | PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; | |
231 | PNAME(rpll_p) = { "fin_pll", "fout_rpll", }; | |
232 | PNAME(spll_p) = { "fin_pll", "fout_spll", }; | |
233 | PNAME(vpll_p) = { "fin_pll", "fout_vpll", }; | |
234 | ||
235 | PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" }; | |
236 | PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", | |
237 | "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; | |
238 | PNAME(group3_p) = { "sclk_rpll", "sclk_spll" }; | |
239 | PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" }; | |
240 | PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" }; | |
241 | ||
242 | PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" }; | |
243 | PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; | |
244 | ||
245 | PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"}; | |
246 | PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" }; | |
247 | ||
248 | PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"}; | |
249 | PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" }; | |
250 | ||
251 | PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"}; | |
252 | PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" }; | |
253 | ||
254 | PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"}; | |
255 | PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" }; | |
256 | ||
257 | PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"}; | |
258 | PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" }; | |
259 | ||
260 | PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"}; | |
261 | PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" }; | |
262 | ||
263 | PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"}; | |
264 | PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" }; | |
265 | ||
266 | PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"}; | |
267 | PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" }; | |
268 | ||
269 | PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"}; | |
270 | PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" }; | |
271 | ||
272 | PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"}; | |
273 | PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" }; | |
274 | ||
275 | PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"}; | |
276 | PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" }; | |
277 | ||
278 | PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"}; | |
279 | PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" }; | |
280 | ||
281 | PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"}; | |
282 | PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" }; | |
283 | ||
284 | PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"}; | |
285 | PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" }; | |
286 | ||
287 | PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll", | |
288 | "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; | |
289 | PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll", | |
290 | "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; | |
291 | PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", | |
292 | "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; | |
293 | PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", | |
294 | "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; | |
14d87cda | 295 | PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; |
1609027f CK |
296 | PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", |
297 | "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; | |
298 | ||
299 | /* fixed rate clocks generated outside the soc */ | |
c7306229 | 300 | static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { |
1609027f CK |
301 | FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), |
302 | }; | |
303 | ||
304 | /* fixed rate clocks generated inside the soc */ | |
c7306229 | 305 | static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { |
c9f3f081 | 306 | FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), |
1609027f CK |
307 | FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), |
308 | FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), | |
309 | FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), | |
310 | FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), | |
311 | }; | |
312 | ||
c7306229 | 313 | static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { |
1609027f CK |
314 | FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0), |
315 | }; | |
316 | ||
c7306229 | 317 | static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { |
1609027f CK |
318 | MUX(none, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), |
319 | MUX(none, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), | |
320 | MUX(none, "mout_apll", apll_p, SRC_CPU, 0, 1), | |
321 | MUX(none, "mout_cpu", cpu_p, SRC_CPU, 16, 1), | |
322 | MUX(none, "mout_kpll", kpll_p, SRC_KFC, 0, 1), | |
323 | MUX(none, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), | |
324 | ||
325 | MUX(none, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), | |
326 | ||
327 | MUX_A(none, "mout_aclk400_mscl", group1_p, | |
328 | SRC_TOP0, 4, 2, "aclk400_mscl"), | |
329 | MUX(none, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), | |
330 | MUX(none, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), | |
331 | MUX(none, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), | |
332 | ||
333 | MUX(none, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), | |
334 | MUX(none, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), | |
335 | MUX(none, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), | |
336 | MUX(none, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), | |
337 | MUX(none, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), | |
338 | ||
339 | MUX(none, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), | |
340 | MUX(none, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), | |
341 | MUX(none, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), | |
342 | MUX(none, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), | |
343 | MUX(none, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), | |
344 | MUX(none, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), | |
345 | ||
346 | MUX(none, "mout_user_aclk400_mscl", user_aclk400_mscl_p, | |
347 | SRC_TOP3, 4, 1), | |
348 | MUX_A(none, "mout_aclk200_disp1", aclk200_disp1_p, | |
349 | SRC_TOP3, 8, 1, "aclk200_disp1"), | |
350 | MUX(none, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, | |
351 | SRC_TOP3, 12, 1), | |
352 | MUX(none, "mout_user_aclk200_fsys", user_aclk200_fsys_p, | |
353 | SRC_TOP3, 28, 1), | |
354 | ||
355 | MUX(none, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, | |
356 | SRC_TOP4, 0, 1), | |
357 | MUX(none, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), | |
358 | MUX(none, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), | |
359 | MUX(none, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), | |
360 | MUX(none, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), | |
361 | ||
362 | MUX(none, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), | |
363 | MUX(none, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), | |
364 | MUX(none, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), | |
365 | MUX_A(none, "mout_user_aclk_g3d", user_aclk_g3d_p, | |
366 | SRC_TOP5, 16, 1, "aclkg3d"), | |
367 | MUX(none, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, | |
368 | SRC_TOP5, 20, 1), | |
369 | MUX(none, "mout_user_aclk300_disp1", user_aclk300_disp1_p, | |
370 | SRC_TOP5, 24, 1), | |
371 | MUX(none, "mout_user_aclk300_gscl", user_aclk300_gscl_p, | |
372 | SRC_TOP5, 28, 1), | |
373 | ||
374 | MUX(none, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), | |
375 | MUX(none, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), | |
376 | MUX(none, "sclk_spll", spll_p, SRC_TOP6, 8, 1), | |
377 | MUX(none, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), | |
378 | MUX(none, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), | |
379 | MUX(none, "sclk_epll", epll_p, SRC_TOP6, 20, 1), | |
380 | MUX(none, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), | |
381 | MUX(none, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), | |
382 | ||
383 | MUX(none, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), | |
384 | MUX(none, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), | |
385 | MUX(none, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, | |
386 | SRC_TOP10, 12, 1), | |
387 | MUX(none, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), | |
388 | ||
389 | MUX(none, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, | |
390 | SRC_TOP11, 0, 1), | |
391 | MUX(none, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), | |
392 | MUX(none, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), | |
393 | MUX(none, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), | |
394 | MUX(none, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), | |
395 | ||
396 | MUX(none, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), | |
397 | MUX(none, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), | |
398 | MUX(none, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), | |
399 | MUX(none, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), | |
400 | MUX(none, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, | |
401 | SRC_TOP12, 24, 1), | |
402 | MUX(none, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), | |
403 | ||
404 | /* DISP1 Block */ | |
405 | MUX(none, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), | |
406 | MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), | |
407 | MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3), | |
408 | MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3), | |
4625f1b5 | 409 | MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), |
1609027f CK |
410 | |
411 | /* MAU Block */ | |
412 | MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), | |
413 | ||
414 | /* FSYS Block */ | |
415 | MUX(none, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), | |
416 | MUX(none, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), | |
417 | MUX(none, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), | |
418 | MUX(none, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), | |
419 | MUX(none, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), | |
420 | MUX(none, "mout_unipro", group2_p, SRC_FSYS, 24, 3), | |
421 | ||
422 | /* PERIC Block */ | |
423 | MUX(none, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), | |
424 | MUX(none, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), | |
425 | MUX(none, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), | |
426 | MUX(none, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), | |
427 | MUX(none, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), | |
428 | MUX(none, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), | |
429 | MUX(none, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), | |
430 | MUX(none, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), | |
431 | MUX(none, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), | |
432 | MUX(none, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), | |
433 | MUX(none, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), | |
434 | MUX(none, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), | |
435 | }; | |
436 | ||
c7306229 | 437 | static struct samsung_div_clock exynos5420_div_clks[] __initdata = { |
1609027f CK |
438 | DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), |
439 | DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), | |
440 | DIV(none, "armclk2", "div_arm", DIV_CPU0, 28, 3), | |
441 | DIV(none, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), | |
442 | DIV(none, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), | |
443 | ||
444 | DIV(none, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), | |
445 | DIV(none, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), | |
446 | DIV(none, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), | |
447 | DIV(none, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), | |
448 | DIV(none, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), | |
449 | ||
450 | DIV(none, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", | |
451 | DIV_TOP1, 0, 3), | |
452 | DIV(none, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), | |
453 | DIV(none, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), | |
454 | DIV(none, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), | |
455 | DIV(none, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), | |
456 | ||
457 | DIV(none, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), | |
458 | DIV(none, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), | |
459 | DIV(none, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), | |
460 | DIV(none, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), | |
461 | DIV_A(none, "dout_aclk300_disp1", "mout_aclk300_disp1", | |
462 | DIV_TOP2, 24, 3, "aclk300_disp1"), | |
463 | DIV(none, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), | |
464 | ||
465 | /* DISP1 Block */ | |
466 | DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), | |
467 | DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), | |
468 | DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), | |
0044cbcd | 469 | DIV(dout_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), |
1609027f CK |
470 | |
471 | /* Audio Block */ | |
472 | DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), | |
473 | DIV(none, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), | |
474 | ||
475 | /* USB3.0 */ | |
476 | DIV(none, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), | |
477 | DIV(none, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), | |
478 | DIV(none, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), | |
479 | DIV(none, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), | |
480 | ||
481 | /* MMC */ | |
482 | DIV(none, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), | |
483 | DIV(none, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), | |
484 | DIV(none, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), | |
485 | ||
486 | DIV(none, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), | |
487 | ||
488 | /* UART and PWM */ | |
489 | DIV(none, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), | |
490 | DIV(none, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), | |
491 | DIV(none, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), | |
492 | DIV(none, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), | |
493 | DIV(none, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), | |
494 | ||
495 | /* SPI */ | |
496 | DIV(none, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), | |
497 | DIV(none, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), | |
498 | DIV(none, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), | |
499 | ||
500 | /* PCM */ | |
501 | DIV(none, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), | |
502 | DIV(none, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), | |
503 | ||
504 | /* Audio - I2S */ | |
505 | DIV(none, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), | |
506 | DIV(none, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), | |
507 | DIV(none, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), | |
508 | DIV(none, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), | |
509 | DIV(none, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), | |
510 | ||
511 | /* SPI Pre-Ratio */ | |
512 | DIV(none, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), | |
513 | DIV(none, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), | |
514 | DIV(none, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), | |
515 | }; | |
516 | ||
c7306229 | 517 | static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { |
1609027f CK |
518 | /* TODO: Re-verify the CG bits for all the gate clocks */ |
519 | GATE_A(mct, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"), | |
520 | ||
521 | GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", | |
522 | GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), | |
523 | GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", | |
524 | GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), | |
525 | ||
526 | GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", | |
527 | GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), | |
528 | GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", | |
529 | GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), | |
530 | GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", | |
531 | GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), | |
532 | GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", | |
533 | GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), | |
534 | GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", | |
535 | GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), | |
536 | GATE(0, "pclk66_gpio", "mout_sw_aclk66", | |
537 | GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), | |
538 | GATE(0, "aclk66_psgen", "mout_aclk66_psgen", | |
539 | GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), | |
540 | GATE(0, "aclk66_peric", "mout_aclk66_peric", | |
541 | GATE_BUS_TOP, 11, 0, 0), | |
542 | GATE(0, "aclk166", "mout_user_aclk166", | |
543 | GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), | |
544 | GATE(0, "aclk333", "mout_aclk333", | |
545 | GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), | |
546 | ||
547 | /* sclk */ | |
548 | GATE(sclk_uart0, "sclk_uart0", "dout_uart0", | |
549 | GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), | |
550 | GATE(sclk_uart1, "sclk_uart1", "dout_uart1", | |
551 | GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), | |
552 | GATE(sclk_uart2, "sclk_uart2", "dout_uart2", | |
553 | GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), | |
554 | GATE(sclk_uart3, "sclk_uart3", "dout_uart3", | |
555 | GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), | |
556 | GATE(sclk_spi0, "sclk_spi0", "dout_pre_spi0", | |
557 | GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), | |
558 | GATE(sclk_spi1, "sclk_spi1", "dout_pre_spi1", | |
559 | GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), | |
560 | GATE(sclk_spi2, "sclk_spi2", "dout_pre_spi2", | |
561 | GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), | |
562 | GATE(sclk_spdif, "sclk_spdif", "mout_spdif", | |
563 | GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), | |
564 | GATE(sclk_pwm, "sclk_pwm", "dout_pwm", | |
565 | GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), | |
566 | GATE(sclk_pcm1, "sclk_pcm1", "dout_pcm1", | |
567 | GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), | |
568 | GATE(sclk_pcm2, "sclk_pcm2", "dout_pcm2", | |
569 | GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), | |
570 | GATE(sclk_i2s1, "sclk_i2s1", "dout_i2s1", | |
571 | GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), | |
572 | GATE(sclk_i2s2, "sclk_i2s2", "dout_i2s2", | |
573 | GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), | |
574 | ||
575 | GATE(sclk_mmc0, "sclk_mmc0", "dout_mmc0", | |
576 | GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), | |
577 | GATE(sclk_mmc1, "sclk_mmc1", "dout_mmc1", | |
578 | GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), | |
579 | GATE(sclk_mmc2, "sclk_mmc2", "dout_mmc2", | |
580 | GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), | |
581 | GATE(sclk_usbphy301, "sclk_usbphy301", "dout_usbphy301", | |
582 | GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), | |
583 | GATE(sclk_usbphy300, "sclk_usbphy300", "dout_usbphy300", | |
584 | GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), | |
585 | GATE(sclk_usbd300, "sclk_usbd300", "dout_usbd300", | |
586 | GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), | |
587 | GATE(sclk_usbd301, "sclk_usbd301", "dout_usbd301", | |
588 | GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), | |
589 | ||
590 | GATE(sclk_usbd301, "sclk_unipro", "dout_unipro", | |
591 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), | |
592 | ||
593 | GATE(sclk_gscl_wa, "sclk_gscl_wa", "aclK333_432_gscl", | |
594 | GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0), | |
595 | GATE(sclk_gscl_wb, "sclk_gscl_wb", "aclk333_432_gscl", | |
596 | GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0), | |
597 | ||
598 | /* Display */ | |
599 | GATE(sclk_fimd1, "sclk_fimd1", "dout_fimd1", | |
600 | GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), | |
601 | GATE(sclk_mipi1, "sclk_mipi1", "dout_mipi1", | |
602 | GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), | |
603 | GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", | |
604 | GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), | |
605 | GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", | |
606 | GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), | |
607 | GATE(sclk_dp1, "sclk_dp1", "dout_dp1", | |
608 | GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), | |
609 | ||
610 | /* Maudio Block */ | |
611 | GATE(sclk_maudio0, "sclk_maudio0", "dout_maudio0", | |
612 | GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), | |
613 | GATE(sclk_maupcm0, "sclk_maupcm0", "dout_maupcm0", | |
614 | GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), | |
615 | /* FSYS */ | |
616 | GATE(tsi, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), | |
617 | GATE(pdma0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), | |
618 | GATE(pdma1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), | |
619 | GATE(ufs, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), | |
620 | GATE(rtic, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), | |
621 | GATE(mmc0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), | |
622 | GATE(mmc1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), | |
623 | GATE(mmc2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), | |
624 | GATE(sromc, "sromc", "aclk200_fsys2", | |
625 | GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), | |
626 | GATE(usbh20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), | |
627 | GATE(usbd300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), | |
628 | GATE(usbd301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), | |
629 | ||
630 | /* UART */ | |
631 | GATE(uart0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), | |
632 | GATE(uart1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), | |
633 | GATE_A(uart2, "uart2", "aclk66_peric", | |
634 | GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), | |
635 | GATE(uart3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), | |
636 | /* I2C */ | |
637 | GATE(i2c0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), | |
638 | GATE(i2c1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), | |
639 | GATE(i2c2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), | |
640 | GATE(i2c3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), | |
641 | GATE(i2c4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), | |
642 | GATE(i2c5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), | |
643 | GATE(i2c6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), | |
644 | GATE(i2c7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), | |
645 | GATE(i2c_hdmi, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 0), | |
646 | GATE(tsadc, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), | |
647 | /* SPI */ | |
648 | GATE(spi0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), | |
649 | GATE(spi1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), | |
650 | GATE(spi2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), | |
651 | GATE(keyif, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), | |
652 | /* I2S */ | |
653 | GATE(i2s1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), | |
654 | GATE(i2s2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), | |
655 | /* PCM */ | |
656 | GATE(pcm1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), | |
657 | GATE(pcm2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), | |
658 | /* PWM */ | |
659 | GATE(pwm, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), | |
660 | /* SPDIF */ | |
661 | GATE(spdif, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), | |
662 | ||
663 | GATE(i2c8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), | |
664 | GATE(i2c9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), | |
665 | GATE(i2c10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), | |
666 | ||
667 | GATE(chipid, "chipid", "aclk66_psgen", | |
668 | GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), | |
669 | GATE(sysreg, "sysreg", "aclk66_psgen", | |
670 | GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), | |
671 | GATE(tzpc0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), | |
672 | GATE(tzpc1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), | |
673 | GATE(tzpc2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), | |
674 | GATE(tzpc3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), | |
675 | GATE(tzpc4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), | |
676 | GATE(tzpc5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), | |
677 | GATE(tzpc6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), | |
678 | GATE(tzpc7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), | |
679 | GATE(tzpc8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), | |
680 | GATE(tzpc9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), | |
681 | ||
682 | GATE(hdmi_cec, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 0), | |
683 | GATE(seckey, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), | |
684 | GATE(wdt, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), | |
685 | GATE(rtc, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), | |
686 | GATE(tmu, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), | |
687 | GATE(tmu_gpu, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), | |
688 | ||
689 | GATE(gscl0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), | |
690 | GATE(gscl1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), | |
691 | GATE(clk_3aa, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), | |
692 | ||
693 | GATE(smmu_3aa, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 0), | |
694 | GATE(smmu_fimcl0, "smmu_fimcl0", "aclk333_432_gscl", | |
695 | GATE_IP_GSCL1, 3, 0, 0), | |
696 | GATE(smmu_fimcl1, "smmu_fimcl1", "aclk333_432_gscl", | |
697 | GATE_IP_GSCL1, 4, 0, 0), | |
698 | GATE(smmu_gscl0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 0), | |
699 | GATE(smmu_gscl1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 0), | |
700 | GATE(gscl_wa, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), | |
701 | GATE(gscl_wb, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), | |
702 | GATE(smmu_fimcl3, "smmu_fimcl3,", "aclk333_432_gscl", | |
703 | GATE_IP_GSCL1, 16, 0, 0), | |
704 | GATE(fimc_lite3, "fimc_lite3", "aclk333_432_gscl", | |
705 | GATE_IP_GSCL1, 17, 0, 0), | |
706 | ||
707 | GATE(fimd1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), | |
708 | GATE(dsim1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), | |
709 | GATE(dp1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), | |
710 | GATE(mixer, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), | |
711 | GATE(hdmi, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), | |
712 | GATE(smmu_fimd1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 0), | |
713 | ||
714 | GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), | |
715 | GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), | |
716 | GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), | |
717 | ||
718 | GATE(g3d, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), | |
719 | ||
720 | GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), | |
721 | GATE(jpeg, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), | |
722 | GATE(jpeg2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), | |
723 | GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), | |
724 | GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), | |
725 | GATE(smmu_jpeg, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), | |
726 | GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), | |
727 | ||
728 | GATE(mscl0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), | |
729 | GATE(mscl1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), | |
730 | GATE(mscl2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), | |
731 | GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), | |
732 | GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), | |
733 | GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), | |
9b229d8b | 734 | GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), |
1609027f CK |
735 | }; |
736 | ||
202e5ae9 | 737 | static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { |
c898c6b7 | 738 | [apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, |
3ff6e0d8 | 739 | APLL_CON0, NULL), |
c898c6b7 | 740 | [cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, |
3ff6e0d8 | 741 | MPLL_CON0, NULL), |
c898c6b7 | 742 | [dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK, |
3ff6e0d8 | 743 | DPLL_CON0, NULL), |
c898c6b7 | 744 | [epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, |
3ff6e0d8 | 745 | EPLL_CON0, NULL), |
c898c6b7 | 746 | [rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK, |
3ff6e0d8 | 747 | RPLL_CON0, NULL), |
c898c6b7 | 748 | [ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK, |
3ff6e0d8 | 749 | IPLL_CON0, NULL), |
c898c6b7 | 750 | [spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK, |
3ff6e0d8 | 751 | SPLL_CON0, NULL), |
c898c6b7 | 752 | [vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK, |
3ff6e0d8 | 753 | VPLL_CON0, NULL), |
c898c6b7 | 754 | [mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, |
3ff6e0d8 | 755 | MPLL_CON0, NULL), |
c898c6b7 | 756 | [bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK, |
3ff6e0d8 | 757 | BPLL_CON0, NULL), |
c898c6b7 | 758 | [kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK, |
3ff6e0d8 | 759 | KPLL_CON0, NULL), |
c898c6b7 YSB |
760 | }; |
761 | ||
202e5ae9 | 762 | static struct of_device_id ext_clk_match[] __initdata = { |
1609027f CK |
763 | { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, |
764 | { }, | |
765 | }; | |
766 | ||
767 | /* register exynos5420 clocks */ | |
c7306229 | 768 | static void __init exynos5420_clk_init(struct device_node *np) |
1609027f CK |
769 | { |
770 | void __iomem *reg_base; | |
1609027f CK |
771 | |
772 | if (np) { | |
773 | reg_base = of_iomap(np, 0); | |
774 | if (!reg_base) | |
775 | panic("%s: failed to map registers\n", __func__); | |
776 | } else { | |
777 | panic("%s: unable to determine soc\n", __func__); | |
778 | } | |
779 | ||
780 | samsung_clk_init(np, reg_base, nr_clks, | |
781 | exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs), | |
782 | NULL, 0); | |
783 | samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, | |
784 | ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), | |
785 | ext_clk_match); | |
c898c6b7 YSB |
786 | samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), |
787 | reg_base); | |
1609027f CK |
788 | samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, |
789 | ARRAY_SIZE(exynos5420_fixed_rate_clks)); | |
790 | samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, | |
791 | ARRAY_SIZE(exynos5420_fixed_factor_clks)); | |
792 | samsung_clk_register_mux(exynos5420_mux_clks, | |
793 | ARRAY_SIZE(exynos5420_mux_clks)); | |
794 | samsung_clk_register_div(exynos5420_div_clks, | |
795 | ARRAY_SIZE(exynos5420_div_clks)); | |
796 | samsung_clk_register_gate(exynos5420_gate_clks, | |
797 | ARRAY_SIZE(exynos5420_gate_clks)); | |
798 | } | |
799 | CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); |