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f2585b1c TA |
1 | /* |
2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
3 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Common Clock Framework support for Exynos5440 SoC. | |
10 | */ | |
11 | ||
ad3ab455 | 12 | #include <dt-bindings/clock/exynos5440.h> |
f2585b1c TA |
13 | #include <linux/clk.h> |
14 | #include <linux/clkdev.h> | |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
18 | ||
f2585b1c TA |
19 | #include "clk.h" |
20 | #include "clk-pll.h" | |
21 | ||
22 | #define CLKEN_OV_VAL 0xf8 | |
23 | #define CPU_CLK_STATUS 0xfc | |
24 | #define MISC_DOUT1 0x558 | |
25 | ||
f2585b1c TA |
26 | /* parent clock name list */ |
27 | PNAME(mout_armclk_p) = { "cplla", "cpllb" }; | |
28 | PNAME(mout_spi_p) = { "div125", "div200" }; | |
29 | ||
30 | /* fixed rate clocks generated outside the soc */ | |
901f8576 | 31 | static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { |
ad3ab455 | 32 | FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0), |
f2585b1c TA |
33 | }; |
34 | ||
35 | /* fixed rate clocks */ | |
901f8576 | 36 | static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { |
ad3ab455 AH |
37 | FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000), |
38 | FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), | |
39 | FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), | |
40 | FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), | |
41 | FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), | |
f2585b1c TA |
42 | }; |
43 | ||
44 | /* fixed factor clocks */ | |
901f8576 | 45 | static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { |
ad3ab455 AH |
46 | FFACTOR(0, "div250", "ppll", 1, 4, 0), |
47 | FFACTOR(0, "div200", "ppll", 1, 5, 0), | |
48 | FFACTOR(0, "div125", "div250", 1, 2, 0), | |
f2585b1c TA |
49 | }; |
50 | ||
51 | /* mux clocks */ | |
901f8576 | 52 | static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { |
ad3ab455 AH |
53 | MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), |
54 | MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, | |
f2585b1c TA |
55 | CPU_CLK_STATUS, 0, 1, "armclk"), |
56 | }; | |
57 | ||
58 | /* divider clocks */ | |
901f8576 | 59 | static struct samsung_div_clock exynos5440_div_clks[] __initdata = { |
ad3ab455 | 60 | DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), |
f2585b1c TA |
61 | }; |
62 | ||
63 | /* gate clocks */ | |
901f8576 | 64 | static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { |
ad3ab455 AH |
65 | GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), |
66 | GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), | |
67 | GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), | |
68 | GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0), | |
69 | GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0), | |
70 | GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0), | |
71 | GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0), | |
72 | GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0), | |
73 | GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0), | |
74 | GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0), | |
75 | GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0), | |
76 | GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0), | |
77 | GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0), | |
78 | GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0), | |
79 | GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0), | |
80 | GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0), | |
81 | GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0), | |
82 | GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0), | |
83 | GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0), | |
84 | GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), | |
f2585b1c TA |
85 | }; |
86 | ||
4d1b5e73 | 87 | static struct of_device_id ext_clk_match[] __initdata = { |
f2585b1c TA |
88 | { .compatible = "samsung,clock-xtal", .data = (void *)0, }, |
89 | {}, | |
90 | }; | |
91 | ||
92 | /* register exynos5440 clocks */ | |
901f8576 | 93 | static void __init exynos5440_clk_init(struct device_node *np) |
f2585b1c TA |
94 | { |
95 | void __iomem *reg_base; | |
96 | ||
97 | reg_base = of_iomap(np, 0); | |
98 | if (!reg_base) { | |
99 | pr_err("%s: failed to map clock controller registers," | |
100 | " aborting clock initialization\n", __func__); | |
101 | return; | |
102 | } | |
103 | ||
ad3ab455 | 104 | samsung_clk_init(np, reg_base, CLK_NR_CLKS, NULL, 0, NULL, 0); |
f2585b1c TA |
105 | samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks, |
106 | ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); | |
107 | ||
108 | samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); | |
109 | samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); | |
110 | ||
111 | samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks, | |
112 | ARRAY_SIZE(exynos5440_fixed_rate_clks)); | |
113 | samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks, | |
114 | ARRAY_SIZE(exynos5440_fixed_factor_clks)); | |
115 | samsung_clk_register_mux(exynos5440_mux_clks, | |
116 | ARRAY_SIZE(exynos5440_mux_clks)); | |
117 | samsung_clk_register_div(exynos5440_div_clks, | |
118 | ARRAY_SIZE(exynos5440_div_clks)); | |
119 | samsung_clk_register_gate(exynos5440_gate_clks, | |
120 | ARRAY_SIZE(exynos5440_gate_clks)); | |
121 | ||
3a647895 | 122 | pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); |
f2585b1c TA |
123 | pr_info("exynos5440 clock initialization complete\n"); |
124 | } | |
125 | CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init); |