[deliverable/linux.git] / drivers / clk / samsung / clk-pll.h

/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Copyright (c) 2013 Linaro Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for all PLL's in Samsung platforms
*/

#ifndef __SAMSUNG_CLK_PLL_H
#define __SAMSUNG_CLK_PLL_H

enum samsung_pll_type {
	pll_35xx,
	pll_36xx,
	pll_2550,
	pll_2650,
	pll_4500,
	pll_4502,
	pll_4508,
	pll_4600,
	pll_4650,
	pll_4650c,
	pll_6552,
	pll_6553,
};

#define PLL_35XX_RATE(_rate, _m, _p, _s)			\
	{							\
		.rate	=	(_rate),				\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
	}

#define PLL_36XX_RATE(_rate, _m, _p, _s, _k)			\
	{							\
		.rate	=	(_rate),				\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
	}

#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc)			\
	{							\
		.rate	=	(_rate),			\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.afc	=	(_afc),				\
	}

#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)		\
	{							\
		.rate	=	(_rate),			\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
		.vsel	=	(_vsel),			\
	}

#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel)	\
	{							\
		.rate	=	(_rate),			\
		.mdiv	=	(_m),				\
		.pdiv	=	(_p),				\
		.sdiv	=	(_s),				\
		.kdiv	=	(_k),				\
		.mfr	=	(_mfr),				\
		.mrr	=	(_mrr),				\
		.vsel	=	(_vsel),			\
	}

/* NOTE: Rate table should be kept sorted in descending order. */

struct samsung_pll_rate_table {
	unsigned int rate;
	unsigned int pdiv;
	unsigned int mdiv;
	unsigned int sdiv;
	unsigned int kdiv;
	unsigned int afc;
	unsigned int mfr;
	unsigned int mrr;
	unsigned int vsel;
};

extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
			const char *pname, const void __iomem *reg_base,
			const unsigned long offset);

#endif /* __SAMSUNG_CLK_PLL_H */
Commit	Line	Data
1c4c5fe0 TA	1	/*
	2	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	3	* Copyright (c) 2013 Linaro Ltd.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* Common Clock Framework support for all PLL's in Samsung platforms
	10	*/
	11
	12	#ifndef __SAMSUNG_CLK_PLL_H
	13	#define __SAMSUNG_CLK_PLL_H
	14
07dc76fa YSB	15	enum samsung_pll_type {
	16	pll_35xx,
	17	pll_36xx,
	18	pll_2550,
	19	pll_2650,
52b06016 TF	20	pll_4500,
	21	pll_4502,
	22	pll_4508,
c50d11f3 TF	23	pll_4600,
	24	pll_4650,
	25	pll_4650c,
40ef723c TF	26	pll_6552,
40ef723c TF	27	pll_6553,
07dc76fa YSB	28	};
07dc76fa YSB	29
3ff6e0d8 YSB	30	#define PLL_35XX_RATE(_rate, _m, _p, _s) \
	31	{ \
	32	.rate = (_rate), \
	33	.mdiv = (_m), \
	34	.pdiv = (_p), \
	35	.sdiv = (_s), \
	36	}
	37
	38	#define PLL_36XX_RATE(_rate, _m, _p, _s, _k) \
	39	{ \
	40	.rate = (_rate), \
	41	.mdiv = (_m), \
	42	.pdiv = (_p), \
	43	.sdiv = (_s), \
	44	.kdiv = (_k), \
	45	}
	46
b4054ac6 TF	47	#define PLL_45XX_RATE(_rate, _m, _p, _s, _afc) \
	48	{ \
	49	.rate = (_rate), \
	50	.mdiv = (_m), \
	51	.pdiv = (_p), \
	52	.sdiv = (_s), \
	53	.afc = (_afc), \
	54	}
	55
5c89658a TF	56	#define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel) \
	57	{ \
	58	.rate = (_rate), \
	59	.mdiv = (_m), \
	60	.pdiv = (_p), \
	61	.sdiv = (_s), \
	62	.kdiv = (_k), \
	63	.vsel = (_vsel), \
	64	}
	65
	66	#define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
	67	{ \
	68	.rate = (_rate), \
	69	.mdiv = (_m), \
	70	.pdiv = (_p), \
	71	.sdiv = (_s), \
	72	.kdiv = (_k), \
	73	.mfr = (_mfr), \
	74	.mrr = (_mrr), \
	75	.vsel = (_vsel), \
	76	}
	77
3ff6e0d8 YSB	78	/* NOTE: Rate table should be kept sorted in descending order. */
	79
	80	struct samsung_pll_rate_table {
	81	unsigned int rate;
	82	unsigned int pdiv;
	83	unsigned int mdiv;
	84	unsigned int sdiv;
	85	unsigned int kdiv;
b4054ac6	86	unsigned int afc;
5c89658a TF	87	unsigned int mfr;
	88	unsigned int mrr;
	89	unsigned int vsel;
3ff6e0d8 YSB	90	};
3ff6e0d8 YSB	91
1c4c5fe0 TA	92	extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
	93	const char pname, const void __iomem reg_base,
	94	const unsigned long offset);
	95
	96	#endif /* __SAMSUNG_CLK_PLL_H */