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5799ea12 HS |
1 | /* |
2 | * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Common Clock Framework support for s3c24xx external clock output. | |
9 | */ | |
10 | ||
6f1ed07a SB |
11 | #include <linux/clkdev.h> |
12 | #include <linux/slab.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/clk-provider.h> | |
5799ea12 HS |
15 | #include <linux/platform_device.h> |
16 | #include <linux/module.h> | |
17 | #include "clk.h" | |
18 | ||
19 | /* legacy access to misccr, until dt conversion is finished */ | |
20 | #include <mach/hardware.h> | |
21 | #include <mach/regs-gpio.h> | |
22 | ||
23 | #define MUX_DCLK0 0 | |
24 | #define MUX_DCLK1 1 | |
25 | #define DIV_DCLK0 2 | |
26 | #define DIV_DCLK1 3 | |
27 | #define GATE_DCLK0 4 | |
28 | #define GATE_DCLK1 5 | |
29 | #define MUX_CLKOUT0 6 | |
30 | #define MUX_CLKOUT1 7 | |
31 | #define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1) | |
32 | ||
33 | enum supported_socs { | |
34 | S3C2410, | |
35 | S3C2412, | |
36 | S3C2440, | |
37 | S3C2443, | |
38 | }; | |
39 | ||
40 | struct s3c24xx_dclk_drv_data { | |
41 | const char **clkout0_parent_names; | |
42 | int clkout0_num_parents; | |
43 | const char **clkout1_parent_names; | |
44 | int clkout1_num_parents; | |
45 | const char **mux_parent_names; | |
46 | int mux_num_parents; | |
47 | }; | |
48 | ||
49 | /* | |
50 | * Clock for output-parent selection in misccr | |
51 | */ | |
52 | ||
53 | struct s3c24xx_clkout { | |
54 | struct clk_hw hw; | |
55 | u32 mask; | |
56 | u8 shift; | |
57 | }; | |
58 | ||
59 | #define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw) | |
60 | ||
61 | static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw) | |
62 | { | |
63 | struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw); | |
497295af | 64 | int num_parents = clk_hw_get_num_parents(hw); |
5799ea12 HS |
65 | u32 val; |
66 | ||
67 | val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift; | |
68 | val >>= clkout->shift; | |
69 | val &= clkout->mask; | |
70 | ||
71 | if (val >= num_parents) | |
72 | return -EINVAL; | |
73 | ||
74 | return val; | |
75 | } | |
76 | ||
77 | static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index) | |
78 | { | |
79 | struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw); | |
5799ea12 HS |
80 | |
81 | s3c2410_modify_misccr((clkout->mask << clkout->shift), | |
82 | (index << clkout->shift)); | |
83 | ||
c5e949c1 | 84 | return 0; |
5799ea12 HS |
85 | } |
86 | ||
1237dc44 | 87 | static const struct clk_ops s3c24xx_clkout_ops = { |
5799ea12 HS |
88 | .get_parent = s3c24xx_clkout_get_parent, |
89 | .set_parent = s3c24xx_clkout_set_parent, | |
90 | .determine_rate = __clk_mux_determine_rate, | |
91 | }; | |
92 | ||
1237dc44 | 93 | static struct clk *s3c24xx_register_clkout(struct device *dev, const char *name, |
5799ea12 HS |
94 | const char **parent_names, u8 num_parents, |
95 | u8 shift, u32 mask) | |
96 | { | |
97 | struct s3c24xx_clkout *clkout; | |
98 | struct clk *clk; | |
99 | struct clk_init_data init; | |
100 | ||
101 | /* allocate the clkout */ | |
102 | clkout = kzalloc(sizeof(*clkout), GFP_KERNEL); | |
103 | if (!clkout) | |
104 | return ERR_PTR(-ENOMEM); | |
105 | ||
106 | init.name = name; | |
107 | init.ops = &s3c24xx_clkout_ops; | |
108 | init.flags = CLK_IS_BASIC; | |
109 | init.parent_names = parent_names; | |
110 | init.num_parents = num_parents; | |
111 | ||
112 | clkout->shift = shift; | |
113 | clkout->mask = mask; | |
114 | clkout->hw.init = &init; | |
115 | ||
116 | clk = clk_register(dev, &clkout->hw); | |
117 | ||
118 | return clk; | |
119 | } | |
120 | ||
121 | /* | |
122 | * dclk and clkout init | |
123 | */ | |
124 | ||
125 | struct s3c24xx_dclk { | |
126 | struct device *dev; | |
127 | void __iomem *base; | |
128 | struct clk_onecell_data clk_data; | |
129 | struct notifier_block dclk0_div_change_nb; | |
130 | struct notifier_block dclk1_div_change_nb; | |
131 | spinlock_t dclk_lock; | |
132 | unsigned long reg_save; | |
133 | }; | |
134 | ||
135 | #define to_s3c24xx_dclk0(x) \ | |
136 | container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb) | |
137 | ||
138 | #define to_s3c24xx_dclk1(x) \ | |
139 | container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb) | |
140 | ||
5a3babfc HS |
141 | static const char *dclk_s3c2410_p[] = { "pclk", "uclk" }; |
142 | static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk", | |
5799ea12 | 143 | "gate_dclk0" }; |
5a3babfc | 144 | static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk", |
5799ea12 HS |
145 | "gate_dclk1" }; |
146 | ||
5a3babfc | 147 | static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout", |
5799ea12 | 148 | "hclk", "pclk", "gate_dclk0" }; |
708cec66 | 149 | static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk", |
5799ea12 HS |
150 | "gate_dclk1" }; |
151 | ||
5a3babfc | 152 | static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk", |
5799ea12 | 153 | "gate_dclk0" }; |
5a3babfc | 154 | static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout", |
5799ea12 HS |
155 | "hclk", "pclk", "gate_dclk1" }; |
156 | ||
5a3babfc HS |
157 | static const char *dclk_s3c2443_p[] = { "pclk", "epll" }; |
158 | static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk", | |
5799ea12 | 159 | "gate_dclk0" }; |
5a3babfc | 160 | static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout", |
5799ea12 HS |
161 | "hclk", "pclk", "gate_dclk1" }; |
162 | ||
163 | #define DCLKCON_DCLK_DIV_MASK 0xf | |
164 | #define DCLKCON_DCLK0_DIV_SHIFT 4 | |
165 | #define DCLKCON_DCLK0_CMP_SHIFT 8 | |
166 | #define DCLKCON_DCLK1_DIV_SHIFT 20 | |
167 | #define DCLKCON_DCLK1_CMP_SHIFT 24 | |
168 | ||
169 | static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk, | |
170 | int div_shift, int cmp_shift) | |
171 | { | |
172 | unsigned long flags = 0; | |
173 | u32 dclk_con, div, cmp; | |
174 | ||
175 | spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags); | |
176 | ||
177 | dclk_con = readl_relaxed(s3c24xx_dclk->base); | |
178 | ||
179 | div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1; | |
180 | cmp = ((div + 1) / 2) - 1; | |
181 | ||
182 | dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift); | |
183 | dclk_con |= (cmp << cmp_shift); | |
184 | ||
185 | writel_relaxed(dclk_con, s3c24xx_dclk->base); | |
186 | ||
187 | spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags); | |
188 | } | |
189 | ||
190 | static int s3c24xx_dclk0_div_notify(struct notifier_block *nb, | |
191 | unsigned long event, void *data) | |
192 | { | |
193 | struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb); | |
194 | ||
195 | if (event == POST_RATE_CHANGE) { | |
196 | s3c24xx_dclk_update_cmp(s3c24xx_dclk, | |
197 | DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT); | |
198 | } | |
199 | ||
200 | return NOTIFY_DONE; | |
201 | } | |
202 | ||
203 | static int s3c24xx_dclk1_div_notify(struct notifier_block *nb, | |
204 | unsigned long event, void *data) | |
205 | { | |
206 | struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb); | |
207 | ||
208 | if (event == POST_RATE_CHANGE) { | |
209 | s3c24xx_dclk_update_cmp(s3c24xx_dclk, | |
210 | DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT); | |
211 | } | |
212 | ||
213 | return NOTIFY_DONE; | |
214 | } | |
215 | ||
216 | #ifdef CONFIG_PM_SLEEP | |
217 | static int s3c24xx_dclk_suspend(struct device *dev) | |
218 | { | |
219 | struct platform_device *pdev = to_platform_device(dev); | |
220 | struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev); | |
221 | ||
222 | s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base); | |
223 | return 0; | |
224 | } | |
225 | ||
226 | static int s3c24xx_dclk_resume(struct device *dev) | |
227 | { | |
228 | struct platform_device *pdev = to_platform_device(dev); | |
229 | struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev); | |
230 | ||
231 | writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base); | |
232 | return 0; | |
233 | } | |
234 | #endif | |
235 | ||
236 | static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops, | |
237 | s3c24xx_dclk_suspend, s3c24xx_dclk_resume); | |
238 | ||
239 | static int s3c24xx_dclk_probe(struct platform_device *pdev) | |
240 | { | |
241 | struct s3c24xx_dclk *s3c24xx_dclk; | |
242 | struct resource *mem; | |
243 | struct clk **clk_table; | |
244 | struct s3c24xx_dclk_drv_data *dclk_variant; | |
245 | int ret, i; | |
246 | ||
247 | s3c24xx_dclk = devm_kzalloc(&pdev->dev, sizeof(*s3c24xx_dclk), | |
248 | GFP_KERNEL); | |
249 | if (!s3c24xx_dclk) | |
250 | return -ENOMEM; | |
251 | ||
252 | s3c24xx_dclk->dev = &pdev->dev; | |
253 | platform_set_drvdata(pdev, s3c24xx_dclk); | |
254 | spin_lock_init(&s3c24xx_dclk->dclk_lock); | |
255 | ||
256 | clk_table = devm_kzalloc(&pdev->dev, | |
257 | sizeof(struct clk *) * DCLK_MAX_CLKS, | |
258 | GFP_KERNEL); | |
259 | if (!clk_table) | |
260 | return -ENOMEM; | |
261 | ||
262 | s3c24xx_dclk->clk_data.clks = clk_table; | |
263 | s3c24xx_dclk->clk_data.clk_num = DCLK_MAX_CLKS; | |
264 | ||
265 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
266 | s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem); | |
267 | if (IS_ERR(s3c24xx_dclk->base)) | |
268 | return PTR_ERR(s3c24xx_dclk->base); | |
269 | ||
270 | dclk_variant = (struct s3c24xx_dclk_drv_data *) | |
271 | platform_get_device_id(pdev)->driver_data; | |
272 | ||
273 | ||
274 | clk_table[MUX_DCLK0] = clk_register_mux(&pdev->dev, "mux_dclk0", | |
275 | dclk_variant->mux_parent_names, | |
276 | dclk_variant->mux_num_parents, 0, | |
277 | s3c24xx_dclk->base, 1, 1, 0, | |
278 | &s3c24xx_dclk->dclk_lock); | |
279 | clk_table[MUX_DCLK1] = clk_register_mux(&pdev->dev, "mux_dclk1", | |
280 | dclk_variant->mux_parent_names, | |
281 | dclk_variant->mux_num_parents, 0, | |
282 | s3c24xx_dclk->base, 17, 1, 0, | |
283 | &s3c24xx_dclk->dclk_lock); | |
284 | ||
285 | clk_table[DIV_DCLK0] = clk_register_divider(&pdev->dev, "div_dclk0", | |
286 | "mux_dclk0", 0, s3c24xx_dclk->base, | |
287 | 4, 4, 0, &s3c24xx_dclk->dclk_lock); | |
288 | clk_table[DIV_DCLK1] = clk_register_divider(&pdev->dev, "div_dclk1", | |
289 | "mux_dclk1", 0, s3c24xx_dclk->base, | |
290 | 20, 4, 0, &s3c24xx_dclk->dclk_lock); | |
291 | ||
292 | clk_table[GATE_DCLK0] = clk_register_gate(&pdev->dev, "gate_dclk0", | |
293 | "div_dclk0", CLK_SET_RATE_PARENT, | |
294 | s3c24xx_dclk->base, 0, 0, | |
295 | &s3c24xx_dclk->dclk_lock); | |
296 | clk_table[GATE_DCLK1] = clk_register_gate(&pdev->dev, "gate_dclk1", | |
297 | "div_dclk1", CLK_SET_RATE_PARENT, | |
298 | s3c24xx_dclk->base, 16, 0, | |
299 | &s3c24xx_dclk->dclk_lock); | |
300 | ||
301 | clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev, | |
302 | "clkout0", dclk_variant->clkout0_parent_names, | |
303 | dclk_variant->clkout0_num_parents, 4, 7); | |
304 | clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev, | |
305 | "clkout1", dclk_variant->clkout1_parent_names, | |
306 | dclk_variant->clkout1_num_parents, 8, 7); | |
307 | ||
308 | for (i = 0; i < DCLK_MAX_CLKS; i++) | |
309 | if (IS_ERR(clk_table[i])) { | |
310 | dev_err(&pdev->dev, "clock %d failed to register\n", i); | |
311 | ret = PTR_ERR(clk_table[i]); | |
312 | goto err_clk_register; | |
313 | } | |
314 | ||
315 | ret = clk_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL); | |
316 | if (!ret) | |
317 | ret = clk_register_clkdev(clk_table[MUX_DCLK1], "dclk1", NULL); | |
318 | if (!ret) | |
319 | ret = clk_register_clkdev(clk_table[MUX_CLKOUT0], | |
320 | "clkout0", NULL); | |
321 | if (!ret) | |
322 | ret = clk_register_clkdev(clk_table[MUX_CLKOUT1], | |
323 | "clkout1", NULL); | |
324 | if (ret) { | |
325 | dev_err(&pdev->dev, "failed to register aliases, %d\n", ret); | |
326 | goto err_clk_register; | |
327 | } | |
328 | ||
329 | s3c24xx_dclk->dclk0_div_change_nb.notifier_call = | |
330 | s3c24xx_dclk0_div_notify; | |
331 | ||
332 | s3c24xx_dclk->dclk1_div_change_nb.notifier_call = | |
333 | s3c24xx_dclk1_div_notify; | |
334 | ||
335 | ret = clk_notifier_register(clk_table[DIV_DCLK0], | |
336 | &s3c24xx_dclk->dclk0_div_change_nb); | |
337 | if (ret) | |
338 | goto err_clk_register; | |
339 | ||
340 | ret = clk_notifier_register(clk_table[DIV_DCLK1], | |
341 | &s3c24xx_dclk->dclk1_div_change_nb); | |
342 | if (ret) | |
343 | goto err_dclk_notify; | |
344 | ||
345 | return 0; | |
346 | ||
347 | err_dclk_notify: | |
348 | clk_notifier_unregister(clk_table[DIV_DCLK0], | |
349 | &s3c24xx_dclk->dclk0_div_change_nb); | |
350 | err_clk_register: | |
351 | for (i = 0; i < DCLK_MAX_CLKS; i++) | |
352 | if (clk_table[i] && !IS_ERR(clk_table[i])) | |
353 | clk_unregister(clk_table[i]); | |
354 | ||
355 | return ret; | |
356 | } | |
357 | ||
358 | static int s3c24xx_dclk_remove(struct platform_device *pdev) | |
359 | { | |
360 | struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev); | |
361 | struct clk **clk_table = s3c24xx_dclk->clk_data.clks; | |
362 | int i; | |
363 | ||
364 | clk_notifier_unregister(clk_table[DIV_DCLK1], | |
365 | &s3c24xx_dclk->dclk1_div_change_nb); | |
366 | clk_notifier_unregister(clk_table[DIV_DCLK0], | |
367 | &s3c24xx_dclk->dclk0_div_change_nb); | |
368 | ||
369 | for (i = 0; i < DCLK_MAX_CLKS; i++) | |
370 | clk_unregister(clk_table[i]); | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | static struct s3c24xx_dclk_drv_data dclk_variants[] = { | |
376 | [S3C2410] = { | |
377 | .clkout0_parent_names = clkout0_s3c2410_p, | |
378 | .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p), | |
379 | .clkout1_parent_names = clkout1_s3c2410_p, | |
380 | .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p), | |
381 | .mux_parent_names = dclk_s3c2410_p, | |
382 | .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p), | |
383 | }, | |
384 | [S3C2412] = { | |
385 | .clkout0_parent_names = clkout0_s3c2412_p, | |
386 | .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p), | |
387 | .clkout1_parent_names = clkout1_s3c2412_p, | |
388 | .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p), | |
389 | .mux_parent_names = dclk_s3c2410_p, | |
390 | .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p), | |
391 | }, | |
392 | [S3C2440] = { | |
393 | .clkout0_parent_names = clkout0_s3c2440_p, | |
394 | .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p), | |
395 | .clkout1_parent_names = clkout1_s3c2440_p, | |
396 | .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p), | |
397 | .mux_parent_names = dclk_s3c2410_p, | |
398 | .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p), | |
399 | }, | |
400 | [S3C2443] = { | |
401 | .clkout0_parent_names = clkout0_s3c2443_p, | |
402 | .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p), | |
403 | .clkout1_parent_names = clkout1_s3c2443_p, | |
404 | .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p), | |
405 | .mux_parent_names = dclk_s3c2443_p, | |
406 | .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p), | |
407 | }, | |
408 | }; | |
409 | ||
d5255ec3 | 410 | static const struct platform_device_id s3c24xx_dclk_driver_ids[] = { |
5799ea12 HS |
411 | { |
412 | .name = "s3c2410-dclk", | |
413 | .driver_data = (kernel_ulong_t)&dclk_variants[S3C2410], | |
414 | }, { | |
415 | .name = "s3c2412-dclk", | |
416 | .driver_data = (kernel_ulong_t)&dclk_variants[S3C2412], | |
417 | }, { | |
418 | .name = "s3c2440-dclk", | |
419 | .driver_data = (kernel_ulong_t)&dclk_variants[S3C2440], | |
420 | }, { | |
421 | .name = "s3c2443-dclk", | |
422 | .driver_data = (kernel_ulong_t)&dclk_variants[S3C2443], | |
423 | }, | |
424 | { } | |
425 | }; | |
426 | ||
427 | MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids); | |
428 | ||
429 | static struct platform_driver s3c24xx_dclk_driver = { | |
430 | .driver = { | |
f4f4dd0c KK |
431 | .name = "s3c24xx-dclk", |
432 | .pm = &s3c24xx_dclk_pm_ops, | |
433 | .suppress_bind_attrs = true, | |
5799ea12 HS |
434 | }, |
435 | .probe = s3c24xx_dclk_probe, | |
436 | .remove = s3c24xx_dclk_remove, | |
437 | .id_table = s3c24xx_dclk_driver_ids, | |
438 | }; | |
439 | module_platform_driver(s3c24xx_dclk_driver); | |
440 | ||
441 | MODULE_LICENSE("GPL v2"); | |
442 | MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); | |
443 | MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs"); |