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06dda9d7 TF |
1 | /* |
2 | * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Common Clock Framework support for all S3C64xx SoCs. | |
9 | */ | |
10 | ||
11 | #include <linux/clk.h> | |
12 | #include <linux/clkdev.h> | |
13 | #include <linux/clk-provider.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
16 | ||
17 | #include <dt-bindings/clock/samsung,s3c64xx-clock.h> | |
18 | ||
19 | #include "clk.h" | |
20 | #include "clk-pll.h" | |
21 | ||
22 | /* S3C64xx clock controller register offsets. */ | |
23 | #define APLL_LOCK 0x000 | |
24 | #define MPLL_LOCK 0x004 | |
25 | #define EPLL_LOCK 0x008 | |
26 | #define APLL_CON 0x00c | |
27 | #define MPLL_CON 0x010 | |
28 | #define EPLL_CON0 0x014 | |
29 | #define EPLL_CON1 0x018 | |
30 | #define CLK_SRC 0x01c | |
31 | #define CLK_DIV0 0x020 | |
32 | #define CLK_DIV1 0x024 | |
33 | #define CLK_DIV2 0x028 | |
34 | #define HCLK_GATE 0x030 | |
35 | #define PCLK_GATE 0x034 | |
36 | #define SCLK_GATE 0x038 | |
37 | #define MEM0_GATE 0x03c | |
38 | #define CLK_SRC2 0x10c | |
39 | #define OTHERS 0x900 | |
40 | ||
41 | /* Helper macros to define clock arrays. */ | |
42 | #define FIXED_RATE_CLOCKS(name) \ | |
43 | static struct samsung_fixed_rate_clock name[] | |
44 | #define MUX_CLOCKS(name) \ | |
45 | static struct samsung_mux_clock name[] | |
46 | #define DIV_CLOCKS(name) \ | |
47 | static struct samsung_div_clock name[] | |
48 | #define GATE_CLOCKS(name) \ | |
49 | static struct samsung_gate_clock name[] | |
50 | ||
51 | /* Helper macros for gate types present on S3C64xx. */ | |
52 | #define GATE_BUS(_id, cname, pname, o, b) \ | |
53 | GATE(_id, cname, pname, o, b, 0, 0) | |
54 | #define GATE_SCLK(_id, cname, pname, o, b) \ | |
55 | GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0) | |
56 | #define GATE_ON(_id, cname, pname, o, b) \ | |
57 | GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0) | |
58 | ||
59 | /* list of PLLs to be registered */ | |
60 | enum s3c64xx_plls { | |
61 | apll, mpll, epll, | |
62 | }; | |
63 | ||
64 | /* | |
65 | * List of controller registers to be saved and restored during | |
66 | * a suspend/resume cycle. | |
67 | */ | |
5b0dde99 | 68 | static unsigned long s3c64xx_clk_regs[] __initdata = { |
06dda9d7 TF |
69 | APLL_LOCK, |
70 | MPLL_LOCK, | |
71 | EPLL_LOCK, | |
72 | APLL_CON, | |
73 | MPLL_CON, | |
74 | EPLL_CON0, | |
75 | EPLL_CON1, | |
76 | CLK_SRC, | |
77 | CLK_DIV0, | |
78 | CLK_DIV1, | |
79 | CLK_DIV2, | |
80 | HCLK_GATE, | |
81 | PCLK_GATE, | |
82 | SCLK_GATE, | |
83 | }; | |
84 | ||
5b0dde99 | 85 | static unsigned long s3c6410_clk_regs[] __initdata = { |
06dda9d7 TF |
86 | CLK_SRC2, |
87 | MEM0_GATE, | |
88 | }; | |
89 | ||
90 | /* List of parent clocks common for all S3C64xx SoCs. */ | |
91 | PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" }; | |
92 | PNAME(uart_p) = { "mout_epll", "dout_mpll" }; | |
93 | PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0", | |
94 | "pcmcdclk0", "none", "none", "none" }; | |
95 | PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1", | |
96 | "pcmcdclk0", "none", "none", "none" }; | |
97 | PNAME(mfc_p) = { "hclkx2", "mout_epll" }; | |
98 | PNAME(apll_p) = { "fin_pll", "fout_apll" }; | |
99 | PNAME(mpll_p) = { "fin_pll", "fout_mpll" }; | |
100 | PNAME(epll_p) = { "fin_pll", "fout_epll" }; | |
101 | PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" }; | |
102 | ||
103 | /* S3C6400-specific parent clocks. */ | |
104 | PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" }; | |
105 | PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" }; | |
106 | PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" }; | |
107 | ||
108 | /* S3C6410-specific parent clocks. */ | |
109 | PNAME(clk27_p6410) = { "clk27m", "fin_pll" }; | |
110 | PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" }; | |
111 | PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" }; | |
112 | PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" }; | |
113 | PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2", | |
114 | "pcmcdclk1", "none", "none", "none" }; | |
115 | ||
116 | /* Fixed rate clocks generated outside the SoC. */ | |
117 | FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = { | |
118 | FRATE(0, "fin_pll", NULL, CLK_IS_ROOT, 0), | |
119 | FRATE(0, "xusbxti", NULL, CLK_IS_ROOT, 0), | |
120 | }; | |
121 | ||
122 | /* Fixed rate clocks generated inside the SoC. */ | |
123 | FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = { | |
124 | FRATE(CLK27M, "clk27m", NULL, CLK_IS_ROOT, 27000000), | |
125 | FRATE(CLK48M, "clk48m", NULL, CLK_IS_ROOT, 48000000), | |
126 | }; | |
127 | ||
128 | /* List of clock muxes present on all S3C64xx SoCs. */ | |
129 | MUX_CLOCKS(s3c64xx_mux_clks) __initdata = { | |
130 | MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY), | |
131 | MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1), | |
132 | MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1), | |
133 | MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1), | |
134 | MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1), | |
135 | MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3), | |
136 | MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3), | |
137 | MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1), | |
138 | MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2), | |
139 | MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2), | |
140 | MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2), | |
141 | MUX(MOUT_MMC1, "mout_mmc1", spi_mmc_p, CLK_SRC, 20, 2), | |
142 | MUX(MOUT_MMC2, "mout_mmc2", spi_mmc_p, CLK_SRC, 22, 2), | |
143 | }; | |
144 | ||
145 | /* List of clock muxes present on S3C6400. */ | |
146 | MUX_CLOCKS(s3c6400_mux_clks) __initdata = { | |
147 | MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2), | |
148 | MUX(MOUT_IRDA, "mout_irda", irda_p6400, CLK_SRC, 24, 2), | |
149 | MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6400, CLK_SRC, 26, 2), | |
150 | MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6400, CLK_SRC, 28, 2), | |
151 | }; | |
152 | ||
153 | /* List of clock muxes present on S3C6410. */ | |
154 | MUX_CLOCKS(s3c6410_mux_clks) __initdata = { | |
155 | MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2), | |
156 | MUX(MOUT_IRDA, "mout_irda", irda_p6410, CLK_SRC, 24, 2), | |
157 | MUX(MOUT_LCD, "mout_lcd", scaler_lcd_p6410, CLK_SRC, 26, 2), | |
158 | MUX(MOUT_SCALER, "mout_scaler", scaler_lcd_p6410, CLK_SRC, 28, 2), | |
159 | MUX(MOUT_DAC27, "mout_dac27", clk27_p6410, CLK_SRC, 30, 1), | |
160 | MUX(MOUT_TV27, "mout_tv27", clk27_p6410, CLK_SRC, 31, 1), | |
161 | MUX(MOUT_AUDIO2, "mout_audio2", audio2_p6410, CLK_SRC2, 0, 3), | |
162 | }; | |
163 | ||
164 | /* List of clock dividers present on all S3C64xx SoCs. */ | |
165 | DIV_CLOCKS(s3c64xx_div_clks) __initdata = { | |
166 | DIV(DOUT_MPLL, "dout_mpll", "mout_mpll", CLK_DIV0, 4, 1), | |
167 | DIV(HCLKX2, "hclkx2", "mout_syncmux", CLK_DIV0, 9, 3), | |
168 | DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1), | |
169 | DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4), | |
170 | DIV(DOUT_SECUR, "dout_secur", "hclkx2", CLK_DIV0, 18, 2), | |
171 | DIV(DOUT_CAM, "dout_cam", "hclkx2", CLK_DIV0, 20, 4), | |
172 | DIV(DOUT_JPEG, "dout_jpeg", "hclkx2", CLK_DIV0, 24, 4), | |
173 | DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV0, 28, 4), | |
174 | DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV1, 0, 4), | |
175 | DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV1, 4, 4), | |
176 | DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4), | |
177 | DIV(DOUT_LCD, "dout_lcd", "mout_lcd", CLK_DIV1, 12, 4), | |
178 | DIV(DOUT_SCALER, "dout_scaler", "mout_scaler", CLK_DIV1, 16, 4), | |
179 | DIV(DOUT_UHOST, "dout_uhost", "mout_uhost", CLK_DIV1, 20, 4), | |
180 | DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV2, 0, 4), | |
181 | DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV2, 4, 4), | |
182 | DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4), | |
183 | DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV2, 12, 4), | |
184 | DIV(DOUT_UART, "dout_uart", "mout_uart", CLK_DIV2, 16, 4), | |
185 | DIV(DOUT_IRDA, "dout_irda", "mout_irda", CLK_DIV2, 20, 4), | |
186 | }; | |
187 | ||
188 | /* List of clock dividers present on S3C6400. */ | |
189 | DIV_CLOCKS(s3c6400_div_clks) __initdata = { | |
190 | DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 3), | |
191 | }; | |
192 | ||
193 | /* List of clock dividers present on S3C6410. */ | |
194 | DIV_CLOCKS(s3c6410_div_clks) __initdata = { | |
195 | DIV(ARMCLK, "armclk", "mout_apll", CLK_DIV0, 0, 4), | |
196 | DIV(DOUT_FIMC, "dout_fimc", "hclk", CLK_DIV1, 24, 4), | |
197 | DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV2, 24, 4), | |
198 | }; | |
199 | ||
200 | /* List of clock gates present on all S3C64xx SoCs. */ | |
201 | GATE_CLOCKS(s3c64xx_gate_clks) __initdata = { | |
202 | GATE_BUS(HCLK_UHOST, "hclk_uhost", "hclk", HCLK_GATE, 29), | |
203 | GATE_BUS(HCLK_SECUR, "hclk_secur", "hclk", HCLK_GATE, 28), | |
204 | GATE_BUS(HCLK_SDMA1, "hclk_sdma1", "hclk", HCLK_GATE, 27), | |
205 | GATE_BUS(HCLK_SDMA0, "hclk_sdma0", "hclk", HCLK_GATE, 26), | |
206 | GATE_ON(HCLK_DDR1, "hclk_ddr1", "hclk", HCLK_GATE, 24), | |
207 | GATE_BUS(HCLK_USB, "hclk_usb", "hclk", HCLK_GATE, 20), | |
208 | GATE_BUS(HCLK_HSMMC2, "hclk_hsmmc2", "hclk", HCLK_GATE, 19), | |
209 | GATE_BUS(HCLK_HSMMC1, "hclk_hsmmc1", "hclk", HCLK_GATE, 18), | |
210 | GATE_BUS(HCLK_HSMMC0, "hclk_hsmmc0", "hclk", HCLK_GATE, 17), | |
211 | GATE_BUS(HCLK_MDP, "hclk_mdp", "hclk", HCLK_GATE, 16), | |
212 | GATE_BUS(HCLK_DHOST, "hclk_dhost", "hclk", HCLK_GATE, 15), | |
213 | GATE_BUS(HCLK_IHOST, "hclk_ihost", "hclk", HCLK_GATE, 14), | |
214 | GATE_BUS(HCLK_DMA1, "hclk_dma1", "hclk", HCLK_GATE, 13), | |
215 | GATE_BUS(HCLK_DMA0, "hclk_dma0", "hclk", HCLK_GATE, 12), | |
216 | GATE_BUS(HCLK_JPEG, "hclk_jpeg", "hclk", HCLK_GATE, 11), | |
217 | GATE_BUS(HCLK_CAMIF, "hclk_camif", "hclk", HCLK_GATE, 10), | |
218 | GATE_BUS(HCLK_SCALER, "hclk_scaler", "hclk", HCLK_GATE, 9), | |
219 | GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8), | |
220 | GATE_BUS(HCLK_TV, "hclk_tv", "hclk", HCLK_GATE, 7), | |
221 | GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5), | |
222 | GATE_BUS(HCLK_ROT, "hclk_rot", "hclk", HCLK_GATE, 4), | |
223 | GATE_BUS(HCLK_LCD, "hclk_lcd", "hclk", HCLK_GATE, 3), | |
224 | GATE_BUS(HCLK_TZIC, "hclk_tzic", "hclk", HCLK_GATE, 2), | |
225 | GATE_ON(HCLK_INTC, "hclk_intc", "hclk", HCLK_GATE, 1), | |
226 | GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24), | |
227 | GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23), | |
228 | GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22), | |
229 | GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21), | |
230 | GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20), | |
231 | GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19), | |
232 | GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18), | |
233 | GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17), | |
234 | GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16), | |
235 | GATE_BUS(PCLK_IIS0, "pclk_iis0", "pclk", PCLK_GATE, 15), | |
236 | GATE_BUS(PCLK_AC97, "pclk_ac97", "pclk", PCLK_GATE, 14), | |
237 | GATE_BUS(PCLK_TZPC, "pclk_tzpc", "pclk", PCLK_GATE, 13), | |
238 | GATE_BUS(PCLK_TSADC, "pclk_tsadc", "pclk", PCLK_GATE, 12), | |
239 | GATE_BUS(PCLK_KEYPAD, "pclk_keypad", "pclk", PCLK_GATE, 11), | |
240 | GATE_BUS(PCLK_IRDA, "pclk_irda", "pclk", PCLK_GATE, 10), | |
241 | GATE_BUS(PCLK_PCM1, "pclk_pcm1", "pclk", PCLK_GATE, 9), | |
242 | GATE_BUS(PCLK_PCM0, "pclk_pcm0", "pclk", PCLK_GATE, 8), | |
243 | GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7), | |
244 | GATE_BUS(PCLK_RTC, "pclk_rtc", "pclk", PCLK_GATE, 6), | |
245 | GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5), | |
246 | GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4), | |
247 | GATE_BUS(PCLK_UART2, "pclk_uart2", "pclk", PCLK_GATE, 3), | |
248 | GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2), | |
249 | GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1), | |
250 | GATE_BUS(PCLK_MFC, "pclk_mfc", "pclk", PCLK_GATE, 0), | |
251 | GATE_SCLK(SCLK_UHOST, "sclk_uhost", "dout_uhost", SCLK_GATE, 30), | |
252 | GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29), | |
253 | GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28), | |
254 | GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27), | |
255 | GATE_SCLK(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", SCLK_GATE, 26), | |
256 | GATE_SCLK(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", SCLK_GATE, 25), | |
257 | GATE_SCLK(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", SCLK_GATE, 24), | |
258 | GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23), | |
259 | GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22), | |
260 | GATE_SCLK(SCLK_SPI1, "sclk_spi1", "dout_spi1", SCLK_GATE, 21), | |
261 | GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20), | |
262 | GATE_SCLK(SCLK_DAC27, "sclk_dac27", "mout_dac27", SCLK_GATE, 19), | |
263 | GATE_SCLK(SCLK_TV27, "sclk_tv27", "mout_tv27", SCLK_GATE, 18), | |
264 | GATE_SCLK(SCLK_SCALER27, "sclk_scaler27", "clk27m", SCLK_GATE, 17), | |
265 | GATE_SCLK(SCLK_SCALER, "sclk_scaler", "dout_scaler", SCLK_GATE, 16), | |
266 | GATE_SCLK(SCLK_LCD27, "sclk_lcd27", "clk27m", SCLK_GATE, 15), | |
267 | GATE_SCLK(SCLK_LCD, "sclk_lcd", "dout_lcd", SCLK_GATE, 14), | |
268 | GATE_SCLK(SCLK_POST0_27, "sclk_post0_27", "clk27m", SCLK_GATE, 12), | |
269 | GATE_SCLK(SCLK_POST0, "sclk_post0", "dout_lcd", SCLK_GATE, 10), | |
270 | GATE_SCLK(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", SCLK_GATE, 9), | |
271 | GATE_SCLK(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", SCLK_GATE, 8), | |
272 | GATE_SCLK(SCLK_SECUR, "sclk_secur", "dout_secur", SCLK_GATE, 7), | |
273 | GATE_SCLK(SCLK_IRDA, "sclk_irda", "dout_irda", SCLK_GATE, 6), | |
274 | GATE_SCLK(SCLK_UART, "sclk_uart", "dout_uart", SCLK_GATE, 5), | |
275 | GATE_SCLK(SCLK_MFC, "sclk_mfc", "dout_mfc", SCLK_GATE, 3), | |
276 | GATE_SCLK(SCLK_CAM, "sclk_cam", "dout_cam", SCLK_GATE, 2), | |
277 | GATE_SCLK(SCLK_JPEG, "sclk_jpeg", "dout_jpeg", SCLK_GATE, 1), | |
278 | }; | |
279 | ||
280 | /* List of clock gates present on S3C6400. */ | |
281 | GATE_CLOCKS(s3c6400_gate_clks) __initdata = { | |
282 | GATE_ON(HCLK_DDR0, "hclk_ddr0", "hclk", HCLK_GATE, 23), | |
283 | GATE_SCLK(SCLK_ONENAND, "sclk_onenand", "parent", SCLK_GATE, 4), | |
284 | }; | |
285 | ||
286 | /* List of clock gates present on S3C6410. */ | |
287 | GATE_CLOCKS(s3c6410_gate_clks) __initdata = { | |
288 | GATE_BUS(HCLK_3DSE, "hclk_3dse", "hclk", HCLK_GATE, 31), | |
289 | GATE_ON(HCLK_IROM, "hclk_irom", "hclk", HCLK_GATE, 25), | |
290 | GATE_ON(HCLK_MEM1, "hclk_mem1", "hclk", HCLK_GATE, 22), | |
291 | GATE_ON(HCLK_MEM0, "hclk_mem0", "hclk", HCLK_GATE, 21), | |
292 | GATE_BUS(HCLK_MFC, "hclk_mfc", "hclk", HCLK_GATE, 0), | |
293 | GATE_BUS(PCLK_IIC1, "pclk_iic1", "pclk", PCLK_GATE, 27), | |
294 | GATE_BUS(PCLK_IIS2, "pclk_iis2", "pclk", PCLK_GATE, 26), | |
295 | GATE_SCLK(SCLK_FIMC, "sclk_fimc", "dout_fimc", SCLK_GATE, 13), | |
296 | GATE_SCLK(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", SCLK_GATE, 11), | |
297 | GATE_BUS(MEM0_CFCON, "mem0_cfcon", "hclk_mem0", MEM0_GATE, 5), | |
298 | GATE_BUS(MEM0_ONENAND1, "mem0_onenand1", "hclk_mem0", MEM0_GATE, 4), | |
299 | GATE_BUS(MEM0_ONENAND0, "mem0_onenand0", "hclk_mem0", MEM0_GATE, 3), | |
300 | GATE_BUS(MEM0_NFCON, "mem0_nfcon", "hclk_mem0", MEM0_GATE, 2), | |
301 | GATE_ON(MEM0_SROM, "mem0_srom", "hclk_mem0", MEM0_GATE, 1), | |
302 | }; | |
303 | ||
304 | /* List of PLL clocks. */ | |
305 | static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = { | |
306 | [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll", | |
307 | APLL_LOCK, APLL_CON, NULL), | |
308 | [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll", | |
309 | MPLL_LOCK, MPLL_CON, NULL), | |
310 | [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll", | |
311 | EPLL_LOCK, EPLL_CON0, NULL), | |
312 | }; | |
313 | ||
314 | /* Aliases for common s3c64xx clocks. */ | |
315 | static struct samsung_clock_alias s3c64xx_clock_aliases[] = { | |
316 | ALIAS(FOUT_APLL, NULL, "fout_apll"), | |
317 | ALIAS(FOUT_MPLL, NULL, "fout_mpll"), | |
318 | ALIAS(FOUT_EPLL, NULL, "fout_epll"), | |
319 | ALIAS(MOUT_EPLL, NULL, "mout_epll"), | |
320 | ALIAS(DOUT_MPLL, NULL, "dout_mpll"), | |
321 | ALIAS(HCLKX2, NULL, "hclk2"), | |
322 | ALIAS(HCLK, NULL, "hclk"), | |
323 | ALIAS(PCLK, NULL, "pclk"), | |
324 | ALIAS(PCLK, NULL, "clk_uart_baud2"), | |
325 | ALIAS(ARMCLK, NULL, "armclk"), | |
326 | ALIAS(HCLK_UHOST, "s3c2410-ohci", "usb-host"), | |
327 | ALIAS(HCLK_USB, "s3c-hsotg", "otg"), | |
328 | ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "hsmmc"), | |
329 | ALIAS(HCLK_HSMMC2, "s3c-sdhci.2", "mmc_busclk.0"), | |
330 | ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"), | |
331 | ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), | |
332 | ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), | |
333 | ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), | |
334 | ALIAS(HCLK_DMA1, NULL, "dma1"), | |
335 | ALIAS(HCLK_DMA0, NULL, "dma0"), | |
336 | ALIAS(HCLK_CAMIF, "s3c-camif", "camif"), | |
337 | ALIAS(HCLK_LCD, "s3c-fb", "lcd"), | |
338 | ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"), | |
339 | ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi"), | |
340 | ALIAS(PCLK_IIC0, "s3c2440-i2c.0", "i2c"), | |
341 | ALIAS(PCLK_IIS1, "samsung-i2s.1", "iis"), | |
342 | ALIAS(PCLK_IIS0, "samsung-i2s.0", "iis"), | |
343 | ALIAS(PCLK_AC97, "samsung-ac97", "ac97"), | |
344 | ALIAS(PCLK_TSADC, "s3c64xx-adc", "adc"), | |
345 | ALIAS(PCLK_KEYPAD, "samsung-keypad", "keypad"), | |
346 | ALIAS(PCLK_PCM1, "samsung-pcm.1", "pcm"), | |
347 | ALIAS(PCLK_PCM0, "samsung-pcm.0", "pcm"), | |
348 | ALIAS(PCLK_PWM, NULL, "timers"), | |
349 | ALIAS(PCLK_RTC, "s3c64xx-rtc", "rtc"), | |
350 | ALIAS(PCLK_WDT, NULL, "watchdog"), | |
351 | ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"), | |
352 | ALIAS(PCLK_UART2, "s3c6400-uart.2", "uart"), | |
353 | ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"), | |
354 | ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"), | |
355 | ALIAS(SCLK_UHOST, "s3c2410-ohci", "usb-bus-host"), | |
356 | ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"), | |
357 | ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"), | |
358 | ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"), | |
359 | ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi-bus"), | |
360 | ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi-bus"), | |
361 | ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"), | |
362 | ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"), | |
363 | ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"), | |
364 | ALIAS(SCLK_AUDIO0, "samsung-i2s.0", "audio-bus"), | |
365 | ALIAS(SCLK_UART, NULL, "clk_uart_baud3"), | |
366 | ALIAS(SCLK_CAM, "s3c-camif", "camera"), | |
367 | }; | |
368 | ||
369 | /* Aliases for s3c6400-specific clocks. */ | |
370 | static struct samsung_clock_alias s3c6400_clock_aliases[] = { | |
371 | /* Nothing to place here yet. */ | |
372 | }; | |
373 | ||
374 | /* Aliases for s3c6410-specific clocks. */ | |
375 | static struct samsung_clock_alias s3c6410_clock_aliases[] = { | |
376 | ALIAS(PCLK_IIC1, "s3c2440-i2c.1", "i2c"), | |
377 | ALIAS(PCLK_IIS2, "samsung-i2s.2", "iis"), | |
378 | ALIAS(SCLK_FIMC, "s3c-camif", "fimc"), | |
379 | ALIAS(SCLK_AUDIO2, "samsung-i2s.2", "audio-bus"), | |
380 | ALIAS(MEM0_SROM, NULL, "srom"), | |
381 | }; | |
382 | ||
383 | static void __init s3c64xx_clk_register_fixed_ext(unsigned long fin_pll_f, | |
384 | unsigned long xusbxti_f) | |
385 | { | |
386 | s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f; | |
387 | s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f; | |
388 | samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_ext_clks, | |
389 | ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks)); | |
390 | } | |
391 | ||
392 | /* Register s3c64xx clocks. */ | |
393 | void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, | |
394 | unsigned long xusbxti_f, bool is_s3c6400, | |
395 | void __iomem *reg_base) | |
396 | { | |
397 | unsigned long *soc_regs = NULL; | |
398 | unsigned long nr_soc_regs = 0; | |
399 | ||
400 | if (np) { | |
401 | reg_base = of_iomap(np, 0); | |
402 | if (!reg_base) | |
403 | panic("%s: failed to map registers\n", __func__); | |
404 | } | |
405 | ||
406 | if (!is_s3c6400) { | |
407 | soc_regs = s3c6410_clk_regs; | |
408 | nr_soc_regs = ARRAY_SIZE(s3c6410_clk_regs); | |
409 | } | |
410 | ||
411 | samsung_clk_init(np, reg_base, NR_CLKS, s3c64xx_clk_regs, | |
412 | ARRAY_SIZE(s3c64xx_clk_regs), soc_regs, nr_soc_regs); | |
413 | ||
414 | /* Register external clocks. */ | |
415 | if (!np) | |
416 | s3c64xx_clk_register_fixed_ext(xtal_f, xusbxti_f); | |
417 | ||
418 | /* Register PLLs. */ | |
419 | samsung_clk_register_pll(s3c64xx_pll_clks, | |
420 | ARRAY_SIZE(s3c64xx_pll_clks), reg_base); | |
421 | ||
422 | /* Register common internal clocks. */ | |
423 | samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_clks, | |
424 | ARRAY_SIZE(s3c64xx_fixed_rate_clks)); | |
425 | samsung_clk_register_mux(s3c64xx_mux_clks, | |
426 | ARRAY_SIZE(s3c64xx_mux_clks)); | |
427 | samsung_clk_register_div(s3c64xx_div_clks, | |
428 | ARRAY_SIZE(s3c64xx_div_clks)); | |
429 | samsung_clk_register_gate(s3c64xx_gate_clks, | |
430 | ARRAY_SIZE(s3c64xx_gate_clks)); | |
431 | ||
432 | /* Register SoC-specific clocks. */ | |
433 | if (is_s3c6400) { | |
434 | samsung_clk_register_mux(s3c6400_mux_clks, | |
435 | ARRAY_SIZE(s3c6400_mux_clks)); | |
436 | samsung_clk_register_div(s3c6400_div_clks, | |
437 | ARRAY_SIZE(s3c6400_div_clks)); | |
438 | samsung_clk_register_gate(s3c6400_gate_clks, | |
439 | ARRAY_SIZE(s3c6400_gate_clks)); | |
440 | samsung_clk_register_alias(s3c6400_clock_aliases, | |
441 | ARRAY_SIZE(s3c6400_clock_aliases)); | |
442 | } else { | |
443 | samsung_clk_register_mux(s3c6410_mux_clks, | |
444 | ARRAY_SIZE(s3c6410_mux_clks)); | |
445 | samsung_clk_register_div(s3c6410_div_clks, | |
446 | ARRAY_SIZE(s3c6410_div_clks)); | |
447 | samsung_clk_register_gate(s3c6410_gate_clks, | |
448 | ARRAY_SIZE(s3c6410_gate_clks)); | |
449 | samsung_clk_register_alias(s3c6410_clock_aliases, | |
450 | ARRAY_SIZE(s3c6410_clock_aliases)); | |
451 | } | |
452 | ||
453 | samsung_clk_register_alias(s3c64xx_clock_aliases, | |
454 | ARRAY_SIZE(s3c64xx_clock_aliases)); | |
455 | ||
456 | pr_info("%s clocks: apll = %lu, mpll = %lu\n" | |
457 | "\tepll = %lu, arm_clk = %lu\n", | |
458 | is_s3c6400 ? "S3C6400" : "S3C6410", | |
459 | _get_rate("fout_apll"), _get_rate("fout_mpll"), | |
460 | _get_rate("fout_epll"), _get_rate("armclk")); | |
461 | } | |
462 | ||
463 | static void __init s3c6400_clk_init(struct device_node *np) | |
464 | { | |
465 | s3c64xx_clk_init(np, 0, 0, true, NULL); | |
466 | } | |
467 | CLK_OF_DECLARE(s3c6400_clk, "samsung,s3c6400-clock", s3c6400_clk_init); | |
468 | ||
469 | static void __init s3c6410_clk_init(struct device_node *np) | |
470 | { | |
471 | s3c64xx_clk_init(np, 0, 0, false, NULL); | |
472 | } | |
473 | CLK_OF_DECLARE(s3c6410_clk, "samsung,s3c6410-clock", s3c6410_clk_init); |