Commit | Line | Data |
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301c5d29 ZS |
1 | /* |
2 | * Clock tree for CSR SiRFAtlas7 | |
3 | * | |
4 | * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/bitops.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/clk-provider.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <linux/reset-controller.h> | |
15 | #include <linux/slab.h> | |
16 | ||
17 | #define SIRFSOC_CLKC_MEMPLL_AB_FREQ 0x0000 | |
18 | #define SIRFSOC_CLKC_MEMPLL_AB_SSC 0x0004 | |
19 | #define SIRFSOC_CLKC_MEMPLL_AB_CTRL0 0x0008 | |
20 | #define SIRFSOC_CLKC_MEMPLL_AB_CTRL1 0x000c | |
21 | #define SIRFSOC_CLKC_MEMPLL_AB_STATUS 0x0010 | |
22 | #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_ADDR 0x0014 | |
23 | #define SIRFSOC_CLKC_MEMPLL_AB_SSRAM_DATA 0x0018 | |
24 | ||
25 | #define SIRFSOC_CLKC_CPUPLL_AB_FREQ 0x001c | |
26 | #define SIRFSOC_CLKC_CPUPLL_AB_SSC 0x0020 | |
27 | #define SIRFSOC_CLKC_CPUPLL_AB_CTRL0 0x0024 | |
28 | #define SIRFSOC_CLKC_CPUPLL_AB_CTRL1 0x0028 | |
29 | #define SIRFSOC_CLKC_CPUPLL_AB_STATUS 0x002c | |
30 | ||
31 | #define SIRFSOC_CLKC_SYS0PLL_AB_FREQ 0x0030 | |
32 | #define SIRFSOC_CLKC_SYS0PLL_AB_SSC 0x0034 | |
33 | #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL0 0x0038 | |
34 | #define SIRFSOC_CLKC_SYS0PLL_AB_CTRL1 0x003c | |
35 | #define SIRFSOC_CLKC_SYS0PLL_AB_STATUS 0x0040 | |
36 | ||
37 | #define SIRFSOC_CLKC_SYS1PLL_AB_FREQ 0x0044 | |
38 | #define SIRFSOC_CLKC_SYS1PLL_AB_SSC 0x0048 | |
39 | #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL0 0x004c | |
40 | #define SIRFSOC_CLKC_SYS1PLL_AB_CTRL1 0x0050 | |
41 | #define SIRFSOC_CLKC_SYS1PLL_AB_STATUS 0x0054 | |
42 | ||
43 | #define SIRFSOC_CLKC_SYS2PLL_AB_FREQ 0x0058 | |
44 | #define SIRFSOC_CLKC_SYS2PLL_AB_SSC 0x005c | |
45 | #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL0 0x0060 | |
46 | #define SIRFSOC_CLKC_SYS2PLL_AB_CTRL1 0x0064 | |
47 | #define SIRFSOC_CLKC_SYS2PLL_AB_STATUS 0x0068 | |
48 | ||
49 | #define SIRFSOC_CLKC_SYS3PLL_AB_FREQ 0x006c | |
50 | #define SIRFSOC_CLKC_SYS3PLL_AB_SSC 0x0070 | |
51 | #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL0 0x0074 | |
52 | #define SIRFSOC_CLKC_SYS3PLL_AB_CTRL1 0x0078 | |
53 | #define SIRFSOC_CLKC_SYS3PLL_AB_STATUS 0x007c | |
54 | ||
55 | #define SIRFSOC_ABPLL_CTRL0_SSEN 0x00001000 | |
56 | #define SIRFSOC_ABPLL_CTRL0_BYPASS 0x00000010 | |
57 | #define SIRFSOC_ABPLL_CTRL0_RESET 0x00000001 | |
58 | ||
59 | #define SIRFSOC_CLKC_AUDIO_DTO_INC 0x0088 | |
60 | #define SIRFSOC_CLKC_DISP0_DTO_INC 0x008c | |
61 | #define SIRFSOC_CLKC_DISP1_DTO_INC 0x0090 | |
62 | ||
63 | #define SIRFSOC_CLKC_AUDIO_DTO_SRC 0x0094 | |
64 | #define SIRFSOC_CLKC_AUDIO_DTO_ENA 0x0098 | |
65 | #define SIRFSOC_CLKC_AUDIO_DTO_DROFF 0x009c | |
66 | ||
67 | #define SIRFSOC_CLKC_DISP0_DTO_SRC 0x00a0 | |
68 | #define SIRFSOC_CLKC_DISP0_DTO_ENA 0x00a4 | |
69 | #define SIRFSOC_CLKC_DISP0_DTO_DROFF 0x00a8 | |
70 | ||
71 | #define SIRFSOC_CLKC_DISP1_DTO_SRC 0x00ac | |
72 | #define SIRFSOC_CLKC_DISP1_DTO_ENA 0x00b0 | |
73 | #define SIRFSOC_CLKC_DISP1_DTO_DROFF 0x00b4 | |
74 | ||
75 | #define SIRFSOC_CLKC_I2S_CLK_SEL 0x00b8 | |
76 | #define SIRFSOC_CLKC_I2S_SEL_STAT 0x00bc | |
77 | ||
78 | #define SIRFSOC_CLKC_USBPHY_CLKDIV_CFG 0x00c0 | |
79 | #define SIRFSOC_CLKC_USBPHY_CLKDIV_ENA 0x00c4 | |
80 | #define SIRFSOC_CLKC_USBPHY_CLK_SEL 0x00c8 | |
81 | #define SIRFSOC_CLKC_USBPHY_CLK_SEL_STAT 0x00cc | |
82 | ||
83 | #define SIRFSOC_CLKC_BTSS_CLKDIV_CFG 0x00d0 | |
84 | #define SIRFSOC_CLKC_BTSS_CLKDIV_ENA 0x00d4 | |
85 | #define SIRFSOC_CLKC_BTSS_CLK_SEL 0x00d8 | |
86 | #define SIRFSOC_CLKC_BTSS_CLK_SEL_STAT 0x00dc | |
87 | ||
88 | #define SIRFSOC_CLKC_RGMII_CLKDIV_CFG 0x00e0 | |
89 | #define SIRFSOC_CLKC_RGMII_CLKDIV_ENA 0x00e4 | |
90 | #define SIRFSOC_CLKC_RGMII_CLK_SEL 0x00e8 | |
91 | #define SIRFSOC_CLKC_RGMII_CLK_SEL_STAT 0x00ec | |
92 | ||
93 | #define SIRFSOC_CLKC_CPU_CLKDIV_CFG 0x00f0 | |
94 | #define SIRFSOC_CLKC_CPU_CLKDIV_ENA 0x00f4 | |
95 | #define SIRFSOC_CLKC_CPU_CLK_SEL 0x00f8 | |
96 | #define SIRFSOC_CLKC_CPU_CLK_SEL_STAT 0x00fc | |
97 | ||
98 | #define SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG 0x0100 | |
99 | #define SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA 0x0104 | |
100 | #define SIRFSOC_CLKC_SDPHY01_CLK_SEL 0x0108 | |
101 | #define SIRFSOC_CLKC_SDPHY01_CLK_SEL_STAT 0x010c | |
102 | ||
103 | #define SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG 0x0110 | |
104 | #define SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA 0x0114 | |
105 | #define SIRFSOC_CLKC_SDPHY23_CLK_SEL 0x0118 | |
106 | #define SIRFSOC_CLKC_SDPHY23_CLK_SEL_STAT 0x011c | |
107 | ||
108 | #define SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG 0x0120 | |
109 | #define SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA 0x0124 | |
110 | #define SIRFSOC_CLKC_SDPHY45_CLK_SEL 0x0128 | |
111 | #define SIRFSOC_CLKC_SDPHY45_CLK_SEL_STAT 0x012c | |
112 | ||
113 | #define SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG 0x0130 | |
114 | #define SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA 0x0134 | |
115 | #define SIRFSOC_CLKC_SDPHY67_CLK_SEL 0x0138 | |
116 | #define SIRFSOC_CLKC_SDPHY67_CLK_SEL_STAT 0x013c | |
117 | ||
118 | #define SIRFSOC_CLKC_CAN_CLKDIV_CFG 0x0140 | |
119 | #define SIRFSOC_CLKC_CAN_CLKDIV_ENA 0x0144 | |
120 | #define SIRFSOC_CLKC_CAN_CLK_SEL 0x0148 | |
121 | #define SIRFSOC_CLKC_CAN_CLK_SEL_STAT 0x014c | |
122 | ||
123 | #define SIRFSOC_CLKC_DEINT_CLKDIV_CFG 0x0150 | |
124 | #define SIRFSOC_CLKC_DEINT_CLKDIV_ENA 0x0154 | |
125 | #define SIRFSOC_CLKC_DEINT_CLK_SEL 0x0158 | |
126 | #define SIRFSOC_CLKC_DEINT_CLK_SEL_STAT 0x015c | |
127 | ||
128 | #define SIRFSOC_CLKC_NAND_CLKDIV_CFG 0x0160 | |
129 | #define SIRFSOC_CLKC_NAND_CLKDIV_ENA 0x0164 | |
130 | #define SIRFSOC_CLKC_NAND_CLK_SEL 0x0168 | |
131 | #define SIRFSOC_CLKC_NAND_CLK_SEL_STAT 0x016c | |
132 | ||
133 | #define SIRFSOC_CLKC_DISP0_CLKDIV_CFG 0x0170 | |
134 | #define SIRFSOC_CLKC_DISP0_CLKDIV_ENA 0x0174 | |
135 | #define SIRFSOC_CLKC_DISP0_CLK_SEL 0x0178 | |
136 | #define SIRFSOC_CLKC_DISP0_CLK_SEL_STAT 0x017c | |
137 | ||
138 | #define SIRFSOC_CLKC_DISP1_CLKDIV_CFG 0x0180 | |
139 | #define SIRFSOC_CLKC_DISP1_CLKDIV_ENA 0x0184 | |
140 | #define SIRFSOC_CLKC_DISP1_CLK_SEL 0x0188 | |
141 | #define SIRFSOC_CLKC_DISP1_CLK_SEL_STAT 0x018c | |
142 | ||
143 | #define SIRFSOC_CLKC_GPU_CLKDIV_CFG 0x0190 | |
144 | #define SIRFSOC_CLKC_GPU_CLKDIV_ENA 0x0194 | |
145 | #define SIRFSOC_CLKC_GPU_CLK_SEL 0x0198 | |
146 | #define SIRFSOC_CLKC_GPU_CLK_SEL_STAT 0x019c | |
147 | ||
148 | #define SIRFSOC_CLKC_GNSS_CLKDIV_CFG 0x01a0 | |
149 | #define SIRFSOC_CLKC_GNSS_CLKDIV_ENA 0x01a4 | |
150 | #define SIRFSOC_CLKC_GNSS_CLK_SEL 0x01a8 | |
151 | #define SIRFSOC_CLKC_GNSS_CLK_SEL_STAT 0x01ac | |
152 | ||
153 | #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG0 0x01b0 | |
154 | #define SIRFSOC_CLKC_SHARED_DIVIDER_CFG1 0x01b4 | |
155 | #define SIRFSOC_CLKC_SHARED_DIVIDER_ENA 0x01b8 | |
156 | ||
157 | #define SIRFSOC_CLKC_SYS_CLK_SEL 0x01bc | |
158 | #define SIRFSOC_CLKC_SYS_CLK_SEL_STAT 0x01c0 | |
159 | #define SIRFSOC_CLKC_IO_CLK_SEL 0x01c4 | |
160 | #define SIRFSOC_CLKC_IO_CLK_SEL_STAT 0x01c8 | |
161 | #define SIRFSOC_CLKC_G2D_CLK_SEL 0x01cc | |
162 | #define SIRFSOC_CLKC_G2D_CLK_SEL_STAT 0x01d0 | |
163 | #define SIRFSOC_CLKC_JPENC_CLK_SEL 0x01d4 | |
164 | #define SIRFSOC_CLKC_JPENC_CLK_SEL_STAT 0x01d8 | |
165 | #define SIRFSOC_CLKC_VDEC_CLK_SEL 0x01dc | |
166 | #define SIRFSOC_CLKC_VDEC_CLK_SEL_STAT 0x01e0 | |
167 | #define SIRFSOC_CLKC_GMAC_CLK_SEL 0x01e4 | |
168 | #define SIRFSOC_CLKC_GMAC_CLK_SEL_STAT 0x01e8 | |
169 | #define SIRFSOC_CLKC_USB_CLK_SEL 0x01ec | |
170 | #define SIRFSOC_CLKC_USB_CLK_SEL_STAT 0x01f0 | |
171 | #define SIRFSOC_CLKC_KAS_CLK_SEL 0x01f4 | |
172 | #define SIRFSOC_CLKC_KAS_CLK_SEL_STAT 0x01f8 | |
173 | #define SIRFSOC_CLKC_SEC_CLK_SEL 0x01fc | |
174 | #define SIRFSOC_CLKC_SEC_CLK_SEL_STAT 0x0200 | |
175 | #define SIRFSOC_CLKC_SDR_CLK_SEL 0x0204 | |
176 | #define SIRFSOC_CLKC_SDR_CLK_SEL_STAT 0x0208 | |
177 | #define SIRFSOC_CLKC_VIP_CLK_SEL 0x020c | |
178 | #define SIRFSOC_CLKC_VIP_CLK_SEL_STAT 0x0210 | |
179 | #define SIRFSOC_CLKC_NOCD_CLK_SEL 0x0214 | |
180 | #define SIRFSOC_CLKC_NOCD_CLK_SEL_STAT 0x0218 | |
181 | #define SIRFSOC_CLKC_NOCR_CLK_SEL 0x021c | |
182 | #define SIRFSOC_CLKC_NOCR_CLK_SEL_STAT 0x0220 | |
183 | #define SIRFSOC_CLKC_TPIU_CLK_SEL 0x0224 | |
184 | #define SIRFSOC_CLKC_TPIU_CLK_SEL_STAT 0x0228 | |
185 | ||
186 | #define SIRFSOC_CLKC_ROOT_CLK_EN0_SET 0x022c | |
187 | #define SIRFSOC_CLKC_ROOT_CLK_EN0_CLR 0x0230 | |
188 | #define SIRFSOC_CLKC_ROOT_CLK_EN0_STAT 0x0234 | |
189 | #define SIRFSOC_CLKC_ROOT_CLK_EN1_SET 0x0238 | |
190 | #define SIRFSOC_CLKC_ROOT_CLK_EN1_CLR 0x023c | |
191 | #define SIRFSOC_CLKC_ROOT_CLK_EN1_STAT 0x0240 | |
192 | ||
193 | #define SIRFSOC_CLKC_LEAF_CLK_EN0_SET 0x0244 | |
194 | #define SIRFSOC_CLKC_LEAF_CLK_EN0_CLR 0x0248 | |
195 | #define SIRFSOC_CLKC_LEAF_CLK_EN0_STAT 0x024c | |
196 | ||
197 | #define SIRFSOC_CLKC_RSTC_A7_SW_RST 0x0308 | |
198 | ||
199 | #define SIRFSOC_CLKC_LEAF_CLK_EN1_SET 0x04a0 | |
200 | #define SIRFSOC_CLKC_LEAF_CLK_EN2_SET 0x04b8 | |
201 | #define SIRFSOC_CLKC_LEAF_CLK_EN3_SET 0x04d0 | |
202 | #define SIRFSOC_CLKC_LEAF_CLK_EN4_SET 0x04e8 | |
203 | #define SIRFSOC_CLKC_LEAF_CLK_EN5_SET 0x0500 | |
204 | #define SIRFSOC_CLKC_LEAF_CLK_EN6_SET 0x0518 | |
205 | #define SIRFSOC_CLKC_LEAF_CLK_EN7_SET 0x0530 | |
206 | #define SIRFSOC_CLKC_LEAF_CLK_EN8_SET 0x0548 | |
207 | ||
a3ff2337 GZ |
208 | #define SIRFSOC_NOC_CLK_IDLEREQ_SET 0x02D0 |
209 | #define SIRFSOC_NOC_CLK_IDLEREQ_CLR 0x02D4 | |
210 | #define SIRFSOC_NOC_CLK_SLVRDY_SET 0x02E8 | |
211 | #define SIRFSOC_NOC_CLK_SLVRDY_CLR 0x02EC | |
212 | #define SIRFSOC_NOC_CLK_IDLE_STATUS 0x02F4 | |
301c5d29 | 213 | |
301c5d29 ZS |
214 | struct clk_pll { |
215 | struct clk_hw hw; | |
216 | u16 regofs; /* register offset */ | |
217 | }; | |
218 | #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw) | |
219 | ||
220 | struct clk_dto { | |
221 | struct clk_hw hw; | |
222 | u16 inc_offset; /* dto increment offset */ | |
223 | u16 src_offset; /* dto src offset */ | |
224 | }; | |
225 | #define to_dtoclk(_hw) container_of(_hw, struct clk_dto, hw) | |
226 | ||
a3ff2337 GZ |
227 | enum clk_unit_type { |
228 | CLK_UNIT_NOC_OTHER, | |
229 | CLK_UNIT_NOC_CLOCK, | |
230 | CLK_UNIT_NOC_SOCKET, | |
231 | }; | |
232 | ||
301c5d29 ZS |
233 | struct clk_unit { |
234 | struct clk_hw hw; | |
235 | u16 regofs; | |
236 | u16 bit; | |
a3ff2337 GZ |
237 | u32 type; |
238 | u8 idle_bit; | |
301c5d29 ZS |
239 | spinlock_t *lock; |
240 | }; | |
241 | #define to_unitclk(_hw) container_of(_hw, struct clk_unit, hw) | |
242 | ||
243 | struct atlas7_div_init_data { | |
244 | const char *div_name; | |
245 | const char *parent_name; | |
246 | const char *gate_name; | |
247 | unsigned long flags; | |
248 | u8 divider_flags; | |
249 | u8 gate_flags; | |
250 | u32 div_offset; | |
251 | u8 shift; | |
252 | u8 width; | |
253 | u32 gate_offset; | |
254 | u8 gate_bit; | |
255 | spinlock_t *lock; | |
256 | }; | |
257 | ||
258 | struct atlas7_mux_init_data { | |
259 | const char *mux_name; | |
260 | const char * const *parent_names; | |
261 | u8 parent_num; | |
262 | unsigned long flags; | |
263 | u8 mux_flags; | |
264 | u32 mux_offset; | |
265 | u8 shift; | |
266 | u8 width; | |
267 | }; | |
268 | ||
269 | struct atlas7_unit_init_data { | |
270 | u32 index; | |
271 | const char *unit_name; | |
272 | const char *parent_name; | |
273 | unsigned long flags; | |
274 | u32 regofs; | |
275 | u8 bit; | |
a3ff2337 GZ |
276 | u32 type; |
277 | u8 idle_bit; | |
301c5d29 ZS |
278 | spinlock_t *lock; |
279 | }; | |
280 | ||
281 | struct atlas7_reset_desc { | |
282 | const char *name; | |
283 | u32 clk_ofs; | |
284 | u8 clk_bit; | |
285 | u32 rst_ofs; | |
286 | u8 rst_bit; | |
287 | spinlock_t *lock; | |
288 | }; | |
289 | ||
1f57d1d8 GZ |
290 | static void __iomem *sirfsoc_clk_vbase; |
291 | static struct clk_onecell_data clk_data; | |
292 | ||
293 | static const struct clk_div_table pll_div_table[] = { | |
294 | { .val = 0, .div = 1 }, | |
295 | { .val = 1, .div = 2 }, | |
296 | { .val = 2, .div = 4 }, | |
297 | { .val = 3, .div = 8 }, | |
298 | { .val = 4, .div = 16 }, | |
299 | { .val = 5, .div = 32 }, | |
300 | }; | |
301 | ||
301c5d29 ZS |
302 | static DEFINE_SPINLOCK(cpupll_ctrl1_lock); |
303 | static DEFINE_SPINLOCK(mempll_ctrl1_lock); | |
304 | static DEFINE_SPINLOCK(sys0pll_ctrl1_lock); | |
305 | static DEFINE_SPINLOCK(sys1pll_ctrl1_lock); | |
306 | static DEFINE_SPINLOCK(sys2pll_ctrl1_lock); | |
307 | static DEFINE_SPINLOCK(sys3pll_ctrl1_lock); | |
308 | static DEFINE_SPINLOCK(usbphy_div_lock); | |
309 | static DEFINE_SPINLOCK(btss_div_lock); | |
310 | static DEFINE_SPINLOCK(rgmii_div_lock); | |
311 | static DEFINE_SPINLOCK(cpu_div_lock); | |
312 | static DEFINE_SPINLOCK(sdphy01_div_lock); | |
313 | static DEFINE_SPINLOCK(sdphy23_div_lock); | |
314 | static DEFINE_SPINLOCK(sdphy45_div_lock); | |
315 | static DEFINE_SPINLOCK(sdphy67_div_lock); | |
316 | static DEFINE_SPINLOCK(can_div_lock); | |
317 | static DEFINE_SPINLOCK(deint_div_lock); | |
318 | static DEFINE_SPINLOCK(nand_div_lock); | |
319 | static DEFINE_SPINLOCK(disp0_div_lock); | |
320 | static DEFINE_SPINLOCK(disp1_div_lock); | |
321 | static DEFINE_SPINLOCK(gpu_div_lock); | |
322 | static DEFINE_SPINLOCK(gnss_div_lock); | |
323 | /* gate register shared */ | |
324 | static DEFINE_SPINLOCK(share_div_lock); | |
325 | static DEFINE_SPINLOCK(root0_gate_lock); | |
326 | static DEFINE_SPINLOCK(root1_gate_lock); | |
327 | static DEFINE_SPINLOCK(leaf0_gate_lock); | |
328 | static DEFINE_SPINLOCK(leaf1_gate_lock); | |
329 | static DEFINE_SPINLOCK(leaf2_gate_lock); | |
330 | static DEFINE_SPINLOCK(leaf3_gate_lock); | |
331 | static DEFINE_SPINLOCK(leaf4_gate_lock); | |
332 | static DEFINE_SPINLOCK(leaf5_gate_lock); | |
333 | static DEFINE_SPINLOCK(leaf6_gate_lock); | |
334 | static DEFINE_SPINLOCK(leaf7_gate_lock); | |
335 | static DEFINE_SPINLOCK(leaf8_gate_lock); | |
336 | ||
337 | static inline unsigned long clkc_readl(unsigned reg) | |
338 | { | |
339 | return readl(sirfsoc_clk_vbase + reg); | |
340 | } | |
341 | ||
342 | static inline void clkc_writel(u32 val, unsigned reg) | |
343 | { | |
344 | writel(val, sirfsoc_clk_vbase + reg); | |
345 | } | |
346 | ||
347 | /* | |
348 | * ABPLL | |
349 | * integer mode: Fvco = Fin * 2 * NF / NR | |
350 | * Spread Spectrum mode: Fvco = Fin * SSN / NR | |
351 | * SSN = 2^24 / (256 * ((ssdiv >> ssdepth) << ssdepth) + (ssmod << ssdepth)) | |
352 | */ | |
353 | static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, | |
354 | unsigned long parent_rate) | |
355 | { | |
356 | unsigned long fin = parent_rate; | |
357 | struct clk_pll *clk = to_pllclk(hw); | |
358 | u64 rate; | |
359 | u32 regctrl0 = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_CTRL0 - | |
360 | SIRFSOC_CLKC_MEMPLL_AB_FREQ); | |
361 | u32 regfreq = clkc_readl(clk->regofs); | |
362 | u32 regssc = clkc_readl(clk->regofs + SIRFSOC_CLKC_MEMPLL_AB_SSC - | |
363 | SIRFSOC_CLKC_MEMPLL_AB_FREQ); | |
364 | u32 nr = (regfreq >> 16 & (BIT(3) - 1)) + 1; | |
365 | u32 nf = (regfreq & (BIT(9) - 1)) + 1; | |
366 | u32 ssdiv = regssc >> 8 & (BIT(12) - 1); | |
367 | u32 ssdepth = regssc >> 20 & (BIT(2) - 1); | |
368 | u32 ssmod = regssc & (BIT(8) - 1); | |
369 | ||
370 | if (regctrl0 & SIRFSOC_ABPLL_CTRL0_BYPASS) | |
371 | return fin; | |
372 | ||
373 | if (regctrl0 & SIRFSOC_ABPLL_CTRL0_SSEN) { | |
374 | rate = fin; | |
375 | rate *= 1 << 24; | |
b32a7cc6 | 376 | do_div(rate, nr); |
301c5d29 ZS |
377 | do_div(rate, (256 * ((ssdiv >> ssdepth) << ssdepth) |
378 | + (ssmod << ssdepth))); | |
379 | } else { | |
380 | rate = 2 * fin; | |
381 | rate *= nf; | |
382 | do_div(rate, nr); | |
383 | } | |
384 | return rate; | |
385 | } | |
386 | ||
387 | static const struct clk_ops ab_pll_ops = { | |
388 | .recalc_rate = pll_clk_recalc_rate, | |
389 | }; | |
390 | ||
391 | static const char * const pll_clk_parents[] = { | |
392 | "xin", | |
393 | }; | |
394 | ||
395 | static struct clk_init_data clk_cpupll_init = { | |
396 | .name = "cpupll_vco", | |
397 | .ops = &ab_pll_ops, | |
398 | .parent_names = pll_clk_parents, | |
399 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
400 | }; | |
401 | ||
402 | static struct clk_pll clk_cpupll = { | |
403 | .regofs = SIRFSOC_CLKC_CPUPLL_AB_FREQ, | |
404 | .hw = { | |
405 | .init = &clk_cpupll_init, | |
406 | }, | |
407 | }; | |
408 | ||
409 | static struct clk_init_data clk_mempll_init = { | |
410 | .name = "mempll_vco", | |
411 | .ops = &ab_pll_ops, | |
412 | .parent_names = pll_clk_parents, | |
413 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
414 | }; | |
415 | ||
416 | static struct clk_pll clk_mempll = { | |
417 | .regofs = SIRFSOC_CLKC_MEMPLL_AB_FREQ, | |
418 | .hw = { | |
419 | .init = &clk_mempll_init, | |
420 | }, | |
421 | }; | |
422 | ||
423 | static struct clk_init_data clk_sys0pll_init = { | |
424 | .name = "sys0pll_vco", | |
425 | .ops = &ab_pll_ops, | |
426 | .parent_names = pll_clk_parents, | |
427 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
428 | }; | |
429 | ||
430 | static struct clk_pll clk_sys0pll = { | |
431 | .regofs = SIRFSOC_CLKC_SYS0PLL_AB_FREQ, | |
432 | .hw = { | |
433 | .init = &clk_sys0pll_init, | |
434 | }, | |
435 | }; | |
436 | ||
437 | static struct clk_init_data clk_sys1pll_init = { | |
438 | .name = "sys1pll_vco", | |
439 | .ops = &ab_pll_ops, | |
440 | .parent_names = pll_clk_parents, | |
441 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
442 | }; | |
443 | ||
444 | static struct clk_pll clk_sys1pll = { | |
445 | .regofs = SIRFSOC_CLKC_SYS1PLL_AB_FREQ, | |
446 | .hw = { | |
447 | .init = &clk_sys1pll_init, | |
448 | }, | |
449 | }; | |
450 | ||
451 | static struct clk_init_data clk_sys2pll_init = { | |
452 | .name = "sys2pll_vco", | |
453 | .ops = &ab_pll_ops, | |
454 | .parent_names = pll_clk_parents, | |
455 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
456 | }; | |
457 | ||
458 | static struct clk_pll clk_sys2pll = { | |
459 | .regofs = SIRFSOC_CLKC_SYS2PLL_AB_FREQ, | |
460 | .hw = { | |
461 | .init = &clk_sys2pll_init, | |
462 | }, | |
463 | }; | |
464 | ||
465 | static struct clk_init_data clk_sys3pll_init = { | |
466 | .name = "sys3pll_vco", | |
467 | .ops = &ab_pll_ops, | |
468 | .parent_names = pll_clk_parents, | |
469 | .num_parents = ARRAY_SIZE(pll_clk_parents), | |
470 | }; | |
471 | ||
472 | static struct clk_pll clk_sys3pll = { | |
473 | .regofs = SIRFSOC_CLKC_SYS3PLL_AB_FREQ, | |
474 | .hw = { | |
475 | .init = &clk_sys3pll_init, | |
476 | }, | |
477 | }; | |
478 | ||
479 | /* | |
480 | * DTO in clkc, default enable double resolution mode | |
481 | * double resolution mode:fout = fin * finc / 2^29 | |
482 | * normal mode:fout = fin * finc / 2^28 | |
483 | */ | |
d1ccbddd YC |
484 | #define DTO_RESL_DOUBLE (1ULL << 29) |
485 | #define DTO_RESL_NORMAL (1ULL << 28) | |
486 | ||
301c5d29 ZS |
487 | static int dto_clk_is_enabled(struct clk_hw *hw) |
488 | { | |
489 | struct clk_dto *clk = to_dtoclk(hw); | |
490 | int reg; | |
491 | ||
492 | reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; | |
493 | ||
494 | return !!(clkc_readl(reg) & BIT(0)); | |
495 | } | |
496 | ||
497 | static int dto_clk_enable(struct clk_hw *hw) | |
498 | { | |
499 | u32 val, reg; | |
500 | struct clk_dto *clk = to_dtoclk(hw); | |
501 | ||
502 | reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; | |
503 | ||
504 | val = clkc_readl(reg) | BIT(0); | |
505 | clkc_writel(val, reg); | |
506 | return 0; | |
507 | } | |
508 | ||
509 | static void dto_clk_disable(struct clk_hw *hw) | |
510 | { | |
511 | u32 val, reg; | |
512 | struct clk_dto *clk = to_dtoclk(hw); | |
513 | ||
514 | reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; | |
515 | ||
516 | val = clkc_readl(reg) & ~BIT(0); | |
517 | clkc_writel(val, reg); | |
518 | } | |
519 | ||
520 | static unsigned long dto_clk_recalc_rate(struct clk_hw *hw, | |
521 | unsigned long parent_rate) | |
522 | { | |
523 | u64 rate = parent_rate; | |
524 | struct clk_dto *clk = to_dtoclk(hw); | |
525 | u32 finc = clkc_readl(clk->inc_offset); | |
526 | u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC); | |
527 | ||
528 | rate *= finc; | |
529 | if (droff & BIT(0)) | |
530 | /* Double resolution off */ | |
d1ccbddd | 531 | do_div(rate, DTO_RESL_NORMAL); |
301c5d29 | 532 | else |
d1ccbddd | 533 | do_div(rate, DTO_RESL_DOUBLE); |
301c5d29 ZS |
534 | |
535 | return rate; | |
536 | } | |
537 | ||
538 | static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
539 | unsigned long *parent_rate) | |
540 | { | |
d1ccbddd | 541 | u64 dividend = rate * DTO_RESL_DOUBLE; |
301c5d29 ZS |
542 | |
543 | do_div(dividend, *parent_rate); | |
544 | dividend *= *parent_rate; | |
d1ccbddd | 545 | do_div(dividend, DTO_RESL_DOUBLE); |
301c5d29 ZS |
546 | |
547 | return dividend; | |
548 | } | |
549 | ||
550 | static int dto_clk_set_rate(struct clk_hw *hw, unsigned long rate, | |
551 | unsigned long parent_rate) | |
552 | { | |
d1ccbddd | 553 | u64 dividend = rate * DTO_RESL_DOUBLE; |
301c5d29 ZS |
554 | struct clk_dto *clk = to_dtoclk(hw); |
555 | ||
556 | do_div(dividend, parent_rate); | |
557 | clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC); | |
558 | clkc_writel(dividend, clk->inc_offset); | |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
563 | static u8 dto_clk_get_parent(struct clk_hw *hw) | |
564 | { | |
565 | struct clk_dto *clk = to_dtoclk(hw); | |
566 | ||
567 | return clkc_readl(clk->src_offset); | |
568 | } | |
569 | ||
570 | /* | |
571 | * dto need CLK_SET_PARENT_GATE | |
572 | */ | |
573 | static int dto_clk_set_parent(struct clk_hw *hw, u8 index) | |
574 | { | |
575 | struct clk_dto *clk = to_dtoclk(hw); | |
576 | ||
577 | clkc_writel(index, clk->src_offset); | |
578 | return 0; | |
579 | } | |
580 | ||
581 | static const struct clk_ops dto_ops = { | |
582 | .is_enabled = dto_clk_is_enabled, | |
583 | .enable = dto_clk_enable, | |
584 | .disable = dto_clk_disable, | |
585 | .recalc_rate = dto_clk_recalc_rate, | |
586 | .round_rate = dto_clk_round_rate, | |
587 | .set_rate = dto_clk_set_rate, | |
588 | .get_parent = dto_clk_get_parent, | |
589 | .set_parent = dto_clk_set_parent, | |
590 | }; | |
591 | ||
592 | /* dto parent clock as syspllvco/clk1 */ | |
593 | static const char * const audiodto_clk_parents[] = { | |
594 | "sys0pll_clk1", | |
595 | "sys1pll_clk1", | |
596 | "sys3pll_clk1", | |
597 | }; | |
598 | ||
599 | static struct clk_init_data clk_audiodto_init = { | |
600 | .name = "audio_dto", | |
601 | .ops = &dto_ops, | |
602 | .parent_names = audiodto_clk_parents, | |
603 | .num_parents = ARRAY_SIZE(audiodto_clk_parents), | |
604 | }; | |
605 | ||
606 | static struct clk_dto clk_audio_dto = { | |
607 | .inc_offset = SIRFSOC_CLKC_AUDIO_DTO_INC, | |
608 | .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC, | |
609 | .hw = { | |
610 | .init = &clk_audiodto_init, | |
611 | }, | |
612 | }; | |
613 | ||
614 | static const char * const disp0dto_clk_parents[] = { | |
615 | "sys0pll_clk1", | |
616 | "sys1pll_clk1", | |
617 | "sys3pll_clk1", | |
618 | }; | |
619 | ||
620 | static struct clk_init_data clk_disp0dto_init = { | |
621 | .name = "disp0_dto", | |
622 | .ops = &dto_ops, | |
623 | .parent_names = disp0dto_clk_parents, | |
624 | .num_parents = ARRAY_SIZE(disp0dto_clk_parents), | |
625 | }; | |
626 | ||
627 | static struct clk_dto clk_disp0_dto = { | |
628 | .inc_offset = SIRFSOC_CLKC_DISP0_DTO_INC, | |
629 | .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC, | |
630 | .hw = { | |
631 | .init = &clk_disp0dto_init, | |
632 | }, | |
633 | }; | |
634 | ||
635 | static const char * const disp1dto_clk_parents[] = { | |
636 | "sys0pll_clk1", | |
637 | "sys1pll_clk1", | |
638 | "sys3pll_clk1", | |
639 | }; | |
640 | ||
641 | static struct clk_init_data clk_disp1dto_init = { | |
642 | .name = "disp1_dto", | |
643 | .ops = &dto_ops, | |
644 | .parent_names = disp1dto_clk_parents, | |
645 | .num_parents = ARRAY_SIZE(disp1dto_clk_parents), | |
646 | }; | |
647 | ||
648 | static struct clk_dto clk_disp1_dto = { | |
649 | .inc_offset = SIRFSOC_CLKC_DISP1_DTO_INC, | |
650 | .src_offset = SIRFSOC_CLKC_DISP1_DTO_SRC, | |
651 | .hw = { | |
652 | .init = &clk_disp1dto_init, | |
653 | }, | |
654 | }; | |
655 | ||
656 | static struct atlas7_div_init_data divider_list[] __initdata = { | |
657 | /* div_name, parent_name, gate_name, clk_flag, divider_flag, gate_flag, div_offset, shift, wdith, gate_offset, bit_enable, lock */ | |
658 | { "sys0pll_qa1", "sys0pll_fixdiv", "sys0pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 0, &usbphy_div_lock }, | |
659 | { "sys1pll_qa1", "sys1pll_fixdiv", "sys1pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 4, &usbphy_div_lock }, | |
660 | { "sys2pll_qa1", "sys2pll_fixdiv", "sys2pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 8, &usbphy_div_lock }, | |
661 | { "sys3pll_qa1", "sys3pll_fixdiv", "sys3pll_a1", 0, 0, 0, SIRFSOC_CLKC_USBPHY_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_USBPHY_CLKDIV_ENA, 12, &usbphy_div_lock }, | |
662 | { "sys0pll_qa2", "sys0pll_fixdiv", "sys0pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 0, &btss_div_lock }, | |
663 | { "sys1pll_qa2", "sys1pll_fixdiv", "sys1pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 4, &btss_div_lock }, | |
664 | { "sys2pll_qa2", "sys2pll_fixdiv", "sys2pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 8, &btss_div_lock }, | |
665 | { "sys3pll_qa2", "sys3pll_fixdiv", "sys3pll_a2", 0, 0, 0, SIRFSOC_CLKC_BTSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_BTSS_CLKDIV_ENA, 12, &btss_div_lock }, | |
666 | { "sys0pll_qa3", "sys0pll_fixdiv", "sys0pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 0, &rgmii_div_lock }, | |
667 | { "sys1pll_qa3", "sys1pll_fixdiv", "sys1pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 4, &rgmii_div_lock }, | |
668 | { "sys2pll_qa3", "sys2pll_fixdiv", "sys2pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 8, &rgmii_div_lock }, | |
669 | { "sys3pll_qa3", "sys3pll_fixdiv", "sys3pll_a3", 0, 0, 0, SIRFSOC_CLKC_RGMII_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_RGMII_CLKDIV_ENA, 12, &rgmii_div_lock }, | |
670 | { "sys0pll_qa4", "sys0pll_fixdiv", "sys0pll_a4", 0, 0, 0, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 0, &cpu_div_lock }, | |
671 | { "sys1pll_qa4", "sys1pll_fixdiv", "sys1pll_a4", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_CPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CPU_CLKDIV_ENA, 4, &cpu_div_lock }, | |
672 | { "sys0pll_qa5", "sys0pll_fixdiv", "sys0pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 0, &sdphy01_div_lock }, | |
673 | { "sys1pll_qa5", "sys1pll_fixdiv", "sys1pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 4, &sdphy01_div_lock }, | |
674 | { "sys2pll_qa5", "sys2pll_fixdiv", "sys2pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 8, &sdphy01_div_lock }, | |
675 | { "sys3pll_qa5", "sys3pll_fixdiv", "sys3pll_a5", 0, 0, 0, SIRFSOC_CLKC_SDPHY01_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY01_CLKDIV_ENA, 12, &sdphy01_div_lock }, | |
676 | { "sys0pll_qa6", "sys0pll_fixdiv", "sys0pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 0, &sdphy23_div_lock }, | |
677 | { "sys1pll_qa6", "sys1pll_fixdiv", "sys1pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 4, &sdphy23_div_lock }, | |
678 | { "sys2pll_qa6", "sys2pll_fixdiv", "sys2pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 8, &sdphy23_div_lock }, | |
679 | { "sys3pll_qa6", "sys3pll_fixdiv", "sys3pll_a6", 0, 0, 0, SIRFSOC_CLKC_SDPHY23_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY23_CLKDIV_ENA, 12, &sdphy23_div_lock }, | |
680 | { "sys0pll_qa7", "sys0pll_fixdiv", "sys0pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 0, &sdphy45_div_lock }, | |
681 | { "sys1pll_qa7", "sys1pll_fixdiv", "sys1pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 4, &sdphy45_div_lock }, | |
682 | { "sys2pll_qa7", "sys2pll_fixdiv", "sys2pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 8, &sdphy45_div_lock }, | |
683 | { "sys3pll_qa7", "sys3pll_fixdiv", "sys3pll_a7", 0, 0, 0, SIRFSOC_CLKC_SDPHY45_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY45_CLKDIV_ENA, 12, &sdphy45_div_lock }, | |
684 | { "sys0pll_qa8", "sys0pll_fixdiv", "sys0pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 0, &sdphy67_div_lock }, | |
685 | { "sys1pll_qa8", "sys1pll_fixdiv", "sys1pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 4, &sdphy67_div_lock }, | |
686 | { "sys2pll_qa8", "sys2pll_fixdiv", "sys2pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 8, &sdphy67_div_lock }, | |
687 | { "sys3pll_qa8", "sys3pll_fixdiv", "sys3pll_a8", 0, 0, 0, SIRFSOC_CLKC_SDPHY67_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_SDPHY67_CLKDIV_ENA, 12, &sdphy67_div_lock }, | |
688 | { "sys0pll_qa9", "sys0pll_fixdiv", "sys0pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 0, &can_div_lock }, | |
689 | { "sys1pll_qa9", "sys1pll_fixdiv", "sys1pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 4, &can_div_lock }, | |
690 | { "sys2pll_qa9", "sys2pll_fixdiv", "sys2pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 8, &can_div_lock }, | |
691 | { "sys3pll_qa9", "sys3pll_fixdiv", "sys3pll_a9", 0, 0, 0, SIRFSOC_CLKC_CAN_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_CAN_CLKDIV_ENA, 12, &can_div_lock }, | |
692 | { "sys0pll_qa10", "sys0pll_fixdiv", "sys0pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 0, &deint_div_lock }, | |
693 | { "sys1pll_qa10", "sys1pll_fixdiv", "sys1pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 4, &deint_div_lock }, | |
694 | { "sys2pll_qa10", "sys2pll_fixdiv", "sys2pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 8, &deint_div_lock }, | |
695 | { "sys3pll_qa10", "sys3pll_fixdiv", "sys3pll_a10", 0, 0, 0, SIRFSOC_CLKC_DEINT_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DEINT_CLKDIV_ENA, 12, &deint_div_lock }, | |
696 | { "sys0pll_qa11", "sys0pll_fixdiv", "sys0pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 0, &nand_div_lock }, | |
697 | { "sys1pll_qa11", "sys1pll_fixdiv", "sys1pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 4, &nand_div_lock }, | |
698 | { "sys2pll_qa11", "sys2pll_fixdiv", "sys2pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 8, &nand_div_lock }, | |
699 | { "sys3pll_qa11", "sys3pll_fixdiv", "sys3pll_a11", 0, 0, 0, SIRFSOC_CLKC_NAND_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_NAND_CLKDIV_ENA, 12, &nand_div_lock }, | |
700 | { "sys0pll_qa12", "sys0pll_fixdiv", "sys0pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 0, &disp0_div_lock }, | |
701 | { "sys1pll_qa12", "sys1pll_fixdiv", "sys1pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 4, &disp0_div_lock }, | |
702 | { "sys2pll_qa12", "sys2pll_fixdiv", "sys2pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 8, &disp0_div_lock }, | |
703 | { "sys3pll_qa12", "sys3pll_fixdiv", "sys3pll_a12", 0, 0, 0, SIRFSOC_CLKC_DISP0_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP0_CLKDIV_ENA, 12, &disp0_div_lock }, | |
704 | { "sys0pll_qa13", "sys0pll_fixdiv", "sys0pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 0, &disp1_div_lock }, | |
705 | { "sys1pll_qa13", "sys1pll_fixdiv", "sys1pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 4, &disp1_div_lock }, | |
706 | { "sys2pll_qa13", "sys2pll_fixdiv", "sys2pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 8, &disp1_div_lock }, | |
707 | { "sys3pll_qa13", "sys3pll_fixdiv", "sys3pll_a13", 0, 0, 0, SIRFSOC_CLKC_DISP1_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_DISP1_CLKDIV_ENA, 12, &disp1_div_lock }, | |
708 | { "sys0pll_qa14", "sys0pll_fixdiv", "sys0pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 0, &gpu_div_lock }, | |
709 | { "sys1pll_qa14", "sys1pll_fixdiv", "sys1pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 4, &gpu_div_lock }, | |
710 | { "sys2pll_qa14", "sys2pll_fixdiv", "sys2pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 8, &gpu_div_lock }, | |
711 | { "sys3pll_qa14", "sys3pll_fixdiv", "sys3pll_a14", 0, 0, 0, SIRFSOC_CLKC_GPU_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GPU_CLKDIV_ENA, 12, &gpu_div_lock }, | |
712 | { "sys0pll_qa15", "sys0pll_fixdiv", "sys0pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 0, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 0, &gnss_div_lock }, | |
713 | { "sys1pll_qa15", "sys1pll_fixdiv", "sys1pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 8, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 4, &gnss_div_lock }, | |
714 | { "sys2pll_qa15", "sys2pll_fixdiv", "sys2pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 16, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 8, &gnss_div_lock }, | |
715 | { "sys3pll_qa15", "sys3pll_fixdiv", "sys3pll_a15", 0, 0, 0, SIRFSOC_CLKC_GNSS_CLKDIV_CFG, 24, 6, SIRFSOC_CLKC_GNSS_CLKDIV_ENA, 12, &gnss_div_lock }, | |
716 | { "sys1pll_qa18", "sys1pll_fixdiv", "sys1pll_a18", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 24, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 12, &share_div_lock }, | |
717 | { "sys1pll_qa19", "sys1pll_fixdiv", "sys1pll_a19", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 16, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 8, &share_div_lock }, | |
718 | { "sys1pll_qa20", "sys1pll_fixdiv", "sys1pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 4, &share_div_lock }, | |
719 | { "sys2pll_qa20", "sys2pll_fixdiv", "sys2pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG0, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 0, &share_div_lock }, | |
720 | { "sys1pll_qa17", "sys1pll_fixdiv", "sys1pll_a17", 0, 0, CLK_IGNORE_UNUSED, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 8, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 20, &share_div_lock }, | |
721 | { "sys0pll_qa20", "sys0pll_fixdiv", "sys0pll_a20", 0, 0, 0, SIRFSOC_CLKC_SHARED_DIVIDER_CFG1, 0, 6, SIRFSOC_CLKC_SHARED_DIVIDER_ENA, 16, &share_div_lock }, | |
722 | }; | |
723 | ||
724 | static const char * const i2s_clk_parents[] = { | |
725 | "xin", | |
726 | "xinw", | |
727 | "audio_dto", | |
728 | /* "pwm_i2s01" */ | |
729 | }; | |
730 | ||
731 | static const char * const usbphy_clk_parents[] = { | |
732 | "xin", | |
733 | "xinw", | |
734 | "sys0pll_a1", | |
735 | "sys1pll_a1", | |
736 | "sys2pll_a1", | |
737 | "sys3pll_a1", | |
738 | }; | |
739 | ||
740 | static const char * const btss_clk_parents[] = { | |
741 | "xin", | |
742 | "xinw", | |
743 | "sys0pll_a2", | |
744 | "sys1pll_a2", | |
745 | "sys2pll_a2", | |
746 | "sys3pll_a2", | |
747 | }; | |
748 | ||
749 | static const char * const rgmii_clk_parents[] = { | |
750 | "xin", | |
751 | "xinw", | |
752 | "sys0pll_a3", | |
753 | "sys1pll_a3", | |
754 | "sys2pll_a3", | |
755 | "sys3pll_a3", | |
756 | }; | |
757 | ||
758 | static const char * const cpu_clk_parents[] = { | |
759 | "xin", | |
760 | "xinw", | |
761 | "sys0pll_a4", | |
762 | "sys1pll_a4", | |
763 | "cpupll_clk1", | |
764 | }; | |
765 | ||
766 | static const char * const sdphy01_clk_parents[] = { | |
767 | "xin", | |
768 | "xinw", | |
769 | "sys0pll_a5", | |
770 | "sys1pll_a5", | |
771 | "sys2pll_a5", | |
772 | "sys3pll_a5", | |
773 | }; | |
774 | ||
775 | static const char * const sdphy23_clk_parents[] = { | |
776 | "xin", | |
777 | "xinw", | |
778 | "sys0pll_a6", | |
779 | "sys1pll_a6", | |
780 | "sys2pll_a6", | |
781 | "sys3pll_a6", | |
782 | }; | |
783 | ||
784 | static const char * const sdphy45_clk_parents[] = { | |
785 | "xin", | |
786 | "xinw", | |
787 | "sys0pll_a7", | |
788 | "sys1pll_a7", | |
789 | "sys2pll_a7", | |
790 | "sys3pll_a7", | |
791 | }; | |
792 | ||
793 | static const char * const sdphy67_clk_parents[] = { | |
794 | "xin", | |
795 | "xinw", | |
796 | "sys0pll_a8", | |
797 | "sys1pll_a8", | |
798 | "sys2pll_a8", | |
799 | "sys3pll_a8", | |
800 | }; | |
801 | ||
802 | static const char * const can_clk_parents[] = { | |
803 | "xin", | |
804 | "xinw", | |
805 | "sys0pll_a9", | |
806 | "sys1pll_a9", | |
807 | "sys2pll_a9", | |
808 | "sys3pll_a9", | |
809 | }; | |
810 | ||
811 | static const char * const deint_clk_parents[] = { | |
812 | "xin", | |
813 | "xinw", | |
814 | "sys0pll_a10", | |
815 | "sys1pll_a10", | |
816 | "sys2pll_a10", | |
817 | "sys3pll_a10", | |
818 | }; | |
819 | ||
820 | static const char * const nand_clk_parents[] = { | |
821 | "xin", | |
822 | "xinw", | |
823 | "sys0pll_a11", | |
824 | "sys1pll_a11", | |
825 | "sys2pll_a11", | |
826 | "sys3pll_a11", | |
827 | }; | |
828 | ||
829 | static const char * const disp0_clk_parents[] = { | |
830 | "xin", | |
831 | "xinw", | |
832 | "sys0pll_a12", | |
833 | "sys1pll_a12", | |
834 | "sys2pll_a12", | |
835 | "sys3pll_a12", | |
836 | "disp0_dto", | |
837 | }; | |
838 | ||
839 | static const char * const disp1_clk_parents[] = { | |
840 | "xin", | |
841 | "xinw", | |
842 | "sys0pll_a13", | |
843 | "sys1pll_a13", | |
844 | "sys2pll_a13", | |
845 | "sys3pll_a13", | |
846 | "disp1_dto", | |
847 | }; | |
848 | ||
849 | static const char * const gpu_clk_parents[] = { | |
850 | "xin", | |
851 | "xinw", | |
852 | "sys0pll_a14", | |
853 | "sys1pll_a14", | |
854 | "sys2pll_a14", | |
855 | "sys3pll_a14", | |
856 | }; | |
857 | ||
858 | static const char * const gnss_clk_parents[] = { | |
859 | "xin", | |
860 | "xinw", | |
861 | "sys0pll_a15", | |
862 | "sys1pll_a15", | |
863 | "sys2pll_a15", | |
864 | "sys3pll_a15", | |
865 | }; | |
866 | ||
867 | static const char * const sys_clk_parents[] = { | |
868 | "xin", | |
869 | "xinw", | |
870 | "sys2pll_a20", | |
871 | "sys1pll_a20", | |
872 | "sys1pll_a19", | |
873 | "sys1pll_a18", | |
874 | "sys0pll_a20", | |
875 | "sys1pll_a17", | |
876 | }; | |
877 | ||
878 | static const char * const io_clk_parents[] = { | |
879 | "xin", | |
880 | "xinw", | |
881 | "sys2pll_a20", | |
882 | "sys1pll_a20", | |
883 | "sys1pll_a19", | |
884 | "sys1pll_a18", | |
885 | "sys0pll_a20", | |
886 | "sys1pll_a17", | |
887 | }; | |
888 | ||
889 | static const char * const g2d_clk_parents[] = { | |
890 | "xin", | |
891 | "xinw", | |
892 | "sys2pll_a20", | |
893 | "sys1pll_a20", | |
894 | "sys1pll_a19", | |
895 | "sys1pll_a18", | |
896 | "sys0pll_a20", | |
897 | "sys1pll_a17", | |
898 | }; | |
899 | ||
900 | static const char * const jpenc_clk_parents[] = { | |
901 | "xin", | |
902 | "xinw", | |
903 | "sys2pll_a20", | |
904 | "sys1pll_a20", | |
905 | "sys1pll_a19", | |
906 | "sys1pll_a18", | |
907 | "sys0pll_a20", | |
908 | "sys1pll_a17", | |
909 | }; | |
910 | ||
911 | static const char * const vdec_clk_parents[] = { | |
912 | "xin", | |
913 | "xinw", | |
914 | "sys2pll_a20", | |
915 | "sys1pll_a20", | |
916 | "sys1pll_a19", | |
917 | "sys1pll_a18", | |
918 | "sys0pll_a20", | |
919 | "sys1pll_a17", | |
920 | }; | |
921 | ||
922 | static const char * const gmac_clk_parents[] = { | |
923 | "xin", | |
924 | "xinw", | |
925 | "sys2pll_a20", | |
926 | "sys1pll_a20", | |
927 | "sys1pll_a19", | |
928 | "sys1pll_a18", | |
929 | "sys0pll_a20", | |
930 | "sys1pll_a17", | |
931 | }; | |
932 | ||
933 | static const char * const usb_clk_parents[] = { | |
934 | "xin", | |
935 | "xinw", | |
936 | "sys2pll_a20", | |
937 | "sys1pll_a20", | |
938 | "sys1pll_a19", | |
939 | "sys1pll_a18", | |
940 | "sys0pll_a20", | |
941 | "sys1pll_a17", | |
942 | }; | |
943 | ||
944 | static const char * const kas_clk_parents[] = { | |
945 | "xin", | |
946 | "xinw", | |
947 | "sys2pll_a20", | |
948 | "sys1pll_a20", | |
949 | "sys1pll_a19", | |
950 | "sys1pll_a18", | |
951 | "sys0pll_a20", | |
952 | "sys1pll_a17", | |
953 | }; | |
954 | ||
955 | static const char * const sec_clk_parents[] = { | |
956 | "xin", | |
957 | "xinw", | |
958 | "sys2pll_a20", | |
959 | "sys1pll_a20", | |
960 | "sys1pll_a19", | |
961 | "sys1pll_a18", | |
962 | "sys0pll_a20", | |
963 | "sys1pll_a17", | |
964 | }; | |
965 | ||
966 | static const char * const sdr_clk_parents[] = { | |
967 | "xin", | |
968 | "xinw", | |
969 | "sys2pll_a20", | |
970 | "sys1pll_a20", | |
971 | "sys1pll_a19", | |
972 | "sys1pll_a18", | |
973 | "sys0pll_a20", | |
974 | "sys1pll_a17", | |
975 | }; | |
976 | ||
977 | static const char * const vip_clk_parents[] = { | |
978 | "xin", | |
979 | "xinw", | |
980 | "sys2pll_a20", | |
981 | "sys1pll_a20", | |
982 | "sys1pll_a19", | |
983 | "sys1pll_a18", | |
984 | "sys0pll_a20", | |
985 | "sys1pll_a17", | |
986 | }; | |
987 | ||
988 | static const char * const nocd_clk_parents[] = { | |
989 | "xin", | |
990 | "xinw", | |
991 | "sys2pll_a20", | |
992 | "sys1pll_a20", | |
993 | "sys1pll_a19", | |
994 | "sys1pll_a18", | |
995 | "sys0pll_a20", | |
996 | "sys1pll_a17", | |
997 | }; | |
998 | ||
999 | static const char * const nocr_clk_parents[] = { | |
1000 | "xin", | |
1001 | "xinw", | |
1002 | "sys2pll_a20", | |
1003 | "sys1pll_a20", | |
1004 | "sys1pll_a19", | |
1005 | "sys1pll_a18", | |
1006 | "sys0pll_a20", | |
1007 | "sys1pll_a17", | |
1008 | }; | |
1009 | ||
1010 | static const char * const tpiu_clk_parents[] = { | |
1011 | "xin", | |
1012 | "xinw", | |
1013 | "sys2pll_a20", | |
1014 | "sys1pll_a20", | |
1015 | "sys1pll_a19", | |
1016 | "sys1pll_a18", | |
1017 | "sys0pll_a20", | |
1018 | "sys1pll_a17", | |
1019 | }; | |
1020 | ||
1021 | static struct atlas7_mux_init_data mux_list[] __initdata = { | |
1022 | /* mux_name, parent_names, parent_num, flags, mux_flags, mux_offset, shift, width */ | |
1023 | { "i2s_mux", i2s_clk_parents, ARRAY_SIZE(i2s_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 2 }, | |
1024 | { "usbphy_mux", usbphy_clk_parents, ARRAY_SIZE(usbphy_clk_parents), 0, 0, SIRFSOC_CLKC_I2S_CLK_SEL, 0, 3 }, | |
1025 | { "btss_mux", btss_clk_parents, ARRAY_SIZE(btss_clk_parents), 0, 0, SIRFSOC_CLKC_BTSS_CLK_SEL, 0, 3 }, | |
1026 | { "rgmii_mux", rgmii_clk_parents, ARRAY_SIZE(rgmii_clk_parents), 0, 0, SIRFSOC_CLKC_RGMII_CLK_SEL, 0, 3 }, | |
1027 | { "cpu_mux", cpu_clk_parents, ARRAY_SIZE(cpu_clk_parents), 0, 0, SIRFSOC_CLKC_CPU_CLK_SEL, 0, 3 }, | |
1028 | { "sdphy01_mux", sdphy01_clk_parents, ARRAY_SIZE(sdphy01_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY01_CLK_SEL, 0, 3 }, | |
1029 | { "sdphy23_mux", sdphy23_clk_parents, ARRAY_SIZE(sdphy23_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY23_CLK_SEL, 0, 3 }, | |
1030 | { "sdphy45_mux", sdphy45_clk_parents, ARRAY_SIZE(sdphy45_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY45_CLK_SEL, 0, 3 }, | |
1031 | { "sdphy67_mux", sdphy67_clk_parents, ARRAY_SIZE(sdphy67_clk_parents), 0, 0, SIRFSOC_CLKC_SDPHY67_CLK_SEL, 0, 3 }, | |
1032 | { "can_mux", can_clk_parents, ARRAY_SIZE(can_clk_parents), 0, 0, SIRFSOC_CLKC_CAN_CLK_SEL, 0, 3 }, | |
1033 | { "deint_mux", deint_clk_parents, ARRAY_SIZE(deint_clk_parents), 0, 0, SIRFSOC_CLKC_DEINT_CLK_SEL, 0, 3 }, | |
1034 | { "nand_mux", nand_clk_parents, ARRAY_SIZE(nand_clk_parents), 0, 0, SIRFSOC_CLKC_NAND_CLK_SEL, 0, 3 }, | |
1035 | { "disp0_mux", disp0_clk_parents, ARRAY_SIZE(disp0_clk_parents), 0, 0, SIRFSOC_CLKC_DISP0_CLK_SEL, 0, 3 }, | |
1036 | { "disp1_mux", disp1_clk_parents, ARRAY_SIZE(disp1_clk_parents), 0, 0, SIRFSOC_CLKC_DISP1_CLK_SEL, 0, 3 }, | |
1037 | { "gpu_mux", gpu_clk_parents, ARRAY_SIZE(gpu_clk_parents), 0, 0, SIRFSOC_CLKC_GPU_CLK_SEL, 0, 3 }, | |
1038 | { "gnss_mux", gnss_clk_parents, ARRAY_SIZE(gnss_clk_parents), 0, 0, SIRFSOC_CLKC_GNSS_CLK_SEL, 0, 3 }, | |
1039 | { "sys_mux", sys_clk_parents, ARRAY_SIZE(sys_clk_parents), 0, 0, SIRFSOC_CLKC_SYS_CLK_SEL, 0, 3 }, | |
1040 | { "io_mux", io_clk_parents, ARRAY_SIZE(io_clk_parents), 0, 0, SIRFSOC_CLKC_IO_CLK_SEL, 0, 3 }, | |
1041 | { "g2d_mux", g2d_clk_parents, ARRAY_SIZE(g2d_clk_parents), 0, 0, SIRFSOC_CLKC_G2D_CLK_SEL, 0, 3 }, | |
1042 | { "jpenc_mux", jpenc_clk_parents, ARRAY_SIZE(jpenc_clk_parents), 0, 0, SIRFSOC_CLKC_JPENC_CLK_SEL, 0, 3 }, | |
1043 | { "vdec_mux", vdec_clk_parents, ARRAY_SIZE(vdec_clk_parents), 0, 0, SIRFSOC_CLKC_VDEC_CLK_SEL, 0, 3 }, | |
1044 | { "gmac_mux", gmac_clk_parents, ARRAY_SIZE(gmac_clk_parents), 0, 0, SIRFSOC_CLKC_GMAC_CLK_SEL, 0, 3 }, | |
1045 | { "usb_mux", usb_clk_parents, ARRAY_SIZE(usb_clk_parents), 0, 0, SIRFSOC_CLKC_USB_CLK_SEL, 0, 3 }, | |
1046 | { "kas_mux", kas_clk_parents, ARRAY_SIZE(kas_clk_parents), 0, 0, SIRFSOC_CLKC_KAS_CLK_SEL, 0, 3 }, | |
1047 | { "sec_mux", sec_clk_parents, ARRAY_SIZE(sec_clk_parents), 0, 0, SIRFSOC_CLKC_SEC_CLK_SEL, 0, 3 }, | |
1048 | { "sdr_mux", sdr_clk_parents, ARRAY_SIZE(sdr_clk_parents), 0, 0, SIRFSOC_CLKC_SDR_CLK_SEL, 0, 3 }, | |
1049 | { "vip_mux", vip_clk_parents, ARRAY_SIZE(vip_clk_parents), 0, 0, SIRFSOC_CLKC_VIP_CLK_SEL, 0, 3 }, | |
1050 | { "nocd_mux", nocd_clk_parents, ARRAY_SIZE(nocd_clk_parents), 0, 0, SIRFSOC_CLKC_NOCD_CLK_SEL, 0, 3 }, | |
1051 | { "nocr_mux", nocr_clk_parents, ARRAY_SIZE(nocr_clk_parents), 0, 0, SIRFSOC_CLKC_NOCR_CLK_SEL, 0, 3 }, | |
1052 | { "tpiu_mux", tpiu_clk_parents, ARRAY_SIZE(tpiu_clk_parents), 0, 0, SIRFSOC_CLKC_TPIU_CLK_SEL, 0, 3 }, | |
1053 | }; | |
1054 | ||
1055 | /* new unit should add start from the tail of list */ | |
1056 | static struct atlas7_unit_init_data unit_list[] __initdata = { | |
1057 | /* unit_name, parent_name, flags, regofs, bit, lock */ | |
a3ff2337 GZ |
1058 | { 0, "audmscm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 0, 0, 0, &root0_gate_lock }, |
1059 | { 1, "gnssm_gnss", "gnss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 1, 0, 0, &root0_gate_lock }, | |
1060 | { 2, "gpum_gpu", "gpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 2, 0, 0, &root0_gate_lock }, | |
1061 | { 3, "mediam_g2d", "g2d_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 3, 0, 0, &root0_gate_lock }, | |
1062 | { 4, "mediam_jpenc", "jpenc_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 4, 0, 0, &root0_gate_lock }, | |
1063 | { 5, "vdifm_disp0", "disp0_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 5, 0, 0, &root0_gate_lock }, | |
1064 | { 6, "vdifm_disp1", "disp1_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 6, 0, 0, &root0_gate_lock }, | |
1065 | { 7, "audmscm_i2s", "i2s_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 8, 0, 0, &root0_gate_lock }, | |
1066 | { 8, "audmscm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 11, 0, 0, &root0_gate_lock }, | |
1067 | { 9, "vdifm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 12, 0, 0, &root0_gate_lock }, | |
1068 | { 10, "gnssm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 13, 0, 0, &root0_gate_lock }, | |
1069 | { 11, "mediam_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 14, 0, 0, &root0_gate_lock }, | |
1070 | { 12, "btm_io", "io_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 17, 0, 0, &root0_gate_lock }, | |
1071 | { 13, "mediam_sdphy01", "sdphy01_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 18, 0, 0, &root0_gate_lock }, | |
1072 | { 14, "vdifm_sdphy23", "sdphy23_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 19, 0, 0, &root0_gate_lock }, | |
1073 | { 15, "vdifm_sdphy45", "sdphy45_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 20, 0, 0, &root0_gate_lock }, | |
1074 | { 16, "vdifm_sdphy67", "sdphy67_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 21, 0, 0, &root0_gate_lock }, | |
1075 | { 17, "audmscm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 22, 0, 0, &root0_gate_lock }, | |
1076 | { 18, "mediam_nand", "nand_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 27, 0, 0, &root0_gate_lock }, | |
1077 | { 19, "gnssm_sec", "sec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 28, 0, 0, &root0_gate_lock }, | |
1078 | { 20, "cpum_cpu", "cpu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 29, 0, 0, &root0_gate_lock }, | |
1079 | { 21, "gnssm_xin", "xin", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 30, 0, 0, &root0_gate_lock }, | |
1080 | { 22, "vdifm_vip", "vip_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN0_SET, 31, 0, 0, &root0_gate_lock }, | |
1081 | { 23, "btm_btss", "btss_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 0, 0, 0, &root1_gate_lock }, | |
1082 | { 24, "mediam_usbphy", "usbphy_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 1, 0, 0, &root1_gate_lock }, | |
1083 | { 25, "rtcm_kas", "kas_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 2, 0, 0, &root1_gate_lock }, | |
1084 | { 26, "audmscm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 3, 0, 0, &root1_gate_lock }, | |
1085 | { 27, "vdifm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 4, 0, 0, &root1_gate_lock }, | |
1086 | { 28, "gnssm_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 5, 0, 0, &root1_gate_lock }, | |
1087 | { 29, "mediam_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 6, 0, 0, &root1_gate_lock }, | |
1088 | { 30, "cpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 8, 0, 0, &root1_gate_lock }, | |
1089 | { 31, "gpum_nocd", "nocd_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 9, 0, 0, &root1_gate_lock }, | |
1090 | { 32, "audmscm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 11, 0, 0, &root1_gate_lock }, | |
1091 | { 33, "vdifm_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 12, 0, 0, &root1_gate_lock }, | |
1092 | { 34, "gnssm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 13, 0, 0, &root1_gate_lock }, | |
1093 | { 35, "mediam_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 14, 0, 0, &root1_gate_lock }, | |
1094 | { 36, "ddrm_nocr", "nocr_mux", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 15, 0, 0, &root1_gate_lock }, | |
1095 | { 37, "cpum_tpiu", "tpiu_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 16, 0, 0, &root1_gate_lock }, | |
1096 | { 38, "gpum_nocr", "nocr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 17, 0, 0, &root1_gate_lock }, | |
1097 | { 39, "gnssm_rgmii", "rgmii_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 20, 0, 0, &root1_gate_lock }, | |
1098 | { 40, "mediam_vdec", "vdec_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 21, 0, 0, &root1_gate_lock }, | |
1099 | { 41, "gpum_sdr", "sdr_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 22, 0, 0, &root1_gate_lock }, | |
1100 | { 42, "vdifm_deint", "deint_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 23, 0, 0, &root1_gate_lock }, | |
1101 | { 43, "gnssm_can", "can_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 26, 0, 0, &root1_gate_lock }, | |
1102 | { 44, "mediam_usb", "usb_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 28, 0, 0, &root1_gate_lock }, | |
1103 | { 45, "gnssm_gmac", "gmac_mux", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 29, 0, 0, &root1_gate_lock }, | |
1104 | { 46, "cvd_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 0, CLK_UNIT_NOC_CLOCK, 4, &leaf1_gate_lock }, | |
1105 | { 47, "timer_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 1, 0, 0, &leaf1_gate_lock }, | |
1106 | { 48, "pulse_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 2, 0, 0, &leaf1_gate_lock }, | |
1107 | { 49, "tsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 3, 0, 0, &leaf1_gate_lock }, | |
1108 | { 50, "tsc_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 21, 0, 0, &leaf1_gate_lock }, | |
1109 | { 51, "ioctop_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 4, 0, 0, &leaf1_gate_lock }, | |
1110 | { 52, "rsc_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 5, 0, 0, &leaf1_gate_lock }, | |
1111 | { 53, "dvm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 6, CLK_UNIT_NOC_SOCKET, 7, &leaf1_gate_lock }, | |
1112 | { 54, "lvds_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 7, CLK_UNIT_NOC_SOCKET, 8, &leaf1_gate_lock }, | |
1113 | { 55, "kas_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 8, CLK_UNIT_NOC_CLOCK, 2, &leaf1_gate_lock }, | |
1114 | { 56, "ac97_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 9, 0, 0, &leaf1_gate_lock }, | |
1115 | { 57, "usp0_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 10, CLK_UNIT_NOC_SOCKET, 4, &leaf1_gate_lock }, | |
1116 | { 58, "usp1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 11, CLK_UNIT_NOC_SOCKET, 5, &leaf1_gate_lock }, | |
1117 | { 59, "usp2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 12, CLK_UNIT_NOC_SOCKET, 6, &leaf1_gate_lock }, | |
1118 | { 60, "dmac2_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 13, CLK_UNIT_NOC_SOCKET, 1, &leaf1_gate_lock }, | |
1119 | { 61, "dmac3_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 14, CLK_UNIT_NOC_SOCKET, 2, &leaf1_gate_lock }, | |
1120 | { 62, "audioif_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 15, CLK_UNIT_NOC_SOCKET, 0, &leaf1_gate_lock }, | |
1121 | { 63, "i2s1_kas", "audmscm_kas", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 17, CLK_UNIT_NOC_CLOCK, 2, &leaf1_gate_lock }, | |
1122 | { 64, "thaudmscm_io", "audmscm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 22, 0, 0, &leaf1_gate_lock }, | |
1123 | { 65, "analogtest_xin", "audmscm_xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN1_SET, 23, 0, 0, &leaf1_gate_lock }, | |
1124 | { 66, "sys2pci_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 0, CLK_UNIT_NOC_CLOCK, 20, &leaf2_gate_lock }, | |
1125 | { 67, "pciarb_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 1, 0, 0, &leaf2_gate_lock }, | |
1126 | { 68, "pcicopy_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 2, 0, 0, &leaf2_gate_lock }, | |
1127 | { 69, "rom_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 3, 0, 0, &leaf2_gate_lock }, | |
1128 | { 70, "sdio23_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 4, 0, 0, &leaf2_gate_lock }, | |
1129 | { 71, "sdio45_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 5, 0, 0, &leaf2_gate_lock }, | |
1130 | { 72, "sdio67_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 6, 0, 0, &leaf2_gate_lock }, | |
1131 | { 73, "vip1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 7, 0, 0, &leaf2_gate_lock }, | |
1132 | { 74, "vip1_vip", "vdifm_vip", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 16, CLK_UNIT_NOC_CLOCK, 21, &leaf2_gate_lock }, | |
1133 | { 75, "sdio23_sdphy23", "vdifm_sdphy23", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 8, 0, 0, &leaf2_gate_lock }, | |
1134 | { 76, "sdio45_sdphy45", "vdifm_sdphy45", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 9, 0, 0, &leaf2_gate_lock }, | |
1135 | { 77, "sdio67_sdphy67", "vdifm_sdphy67", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 10, 0, 0, &leaf2_gate_lock }, | |
1136 | { 78, "vpp0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 11, CLK_UNIT_NOC_CLOCK, 22, &leaf2_gate_lock }, | |
1137 | { 79, "lcd0_disp0", "vdifm_disp0", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 12, CLK_UNIT_NOC_CLOCK, 18, &leaf2_gate_lock }, | |
1138 | { 80, "vpp1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 13, CLK_UNIT_NOC_CLOCK, 23, &leaf2_gate_lock }, | |
1139 | { 81, "lcd1_disp1", "vdifm_disp1", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 14, CLK_UNIT_NOC_CLOCK, 19, &leaf2_gate_lock }, | |
1140 | { 82, "dcu_deint", "vdifm_deint", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 15, CLK_UNIT_NOC_CLOCK, 17, &leaf2_gate_lock }, | |
1141 | { 83, "vdifm_dapa_r_nocr", "vdifm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 17, 0, 0, &leaf2_gate_lock }, | |
1142 | { 84, "gpio1_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 18, 0, 0, &leaf2_gate_lock }, | |
1143 | { 85, "thvdifm_io", "vdifm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN2_SET, 19, 0, 0, &leaf2_gate_lock }, | |
1144 | { 86, "gmac_rgmii", "gnssm_rgmii", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 0, 0, 0, &leaf3_gate_lock }, | |
1145 | { 87, "gmac_gmac", "gnssm_gmac", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 1, CLK_UNIT_NOC_CLOCK, 10, &leaf3_gate_lock }, | |
1146 | { 88, "uart1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 2, CLK_UNIT_NOC_SOCKET, 14, &leaf3_gate_lock }, | |
1147 | { 89, "dmac0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 3, CLK_UNIT_NOC_SOCKET, 11, &leaf3_gate_lock }, | |
1148 | { 90, "uart0_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 4, CLK_UNIT_NOC_SOCKET, 13, &leaf3_gate_lock }, | |
1149 | { 91, "uart2_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 5, CLK_UNIT_NOC_SOCKET, 15, &leaf3_gate_lock }, | |
1150 | { 92, "uart3_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 6, CLK_UNIT_NOC_SOCKET, 16, &leaf3_gate_lock }, | |
1151 | { 93, "uart4_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 7, CLK_UNIT_NOC_SOCKET, 17, &leaf3_gate_lock }, | |
1152 | { 94, "uart5_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 8, CLK_UNIT_NOC_SOCKET, 18, &leaf3_gate_lock }, | |
1153 | { 95, "spi1_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 9, CLK_UNIT_NOC_SOCKET, 12, &leaf3_gate_lock }, | |
1154 | { 96, "gnss_gnss", "gnssm_gnss", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 10, 0, 0, &leaf3_gate_lock }, | |
1155 | { 97, "canbus1_can", "gnssm_can", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 12, CLK_UNIT_NOC_CLOCK, 7, &leaf3_gate_lock }, | |
1156 | { 98, "ccsec_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 15, CLK_UNIT_NOC_CLOCK, 9, &leaf3_gate_lock }, | |
1157 | { 99, "ccpub_sec", "gnssm_sec", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 16, CLK_UNIT_NOC_CLOCK, 8, &leaf3_gate_lock }, | |
1158 | { 100, "gnssm_dapa_r_nocr", "gnssm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 13, 0, 0, &leaf3_gate_lock }, | |
1159 | { 101, "thgnssm_io", "gnssm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN3_SET, 14, 0, 0, &leaf3_gate_lock }, | |
1160 | { 102, "media_vdec", "mediam_vdec", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 0, CLK_UNIT_NOC_CLOCK, 3, &leaf4_gate_lock }, | |
1161 | { 103, "media_jpenc", "mediam_jpenc", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 1, CLK_UNIT_NOC_CLOCK, 1, &leaf4_gate_lock }, | |
1162 | { 104, "g2d_g2d", "mediam_g2d", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 2, CLK_UNIT_NOC_CLOCK, 12, &leaf4_gate_lock }, | |
1163 | { 105, "i2c0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 3, CLK_UNIT_NOC_SOCKET, 21, &leaf4_gate_lock }, | |
1164 | { 106, "i2c1_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 4, CLK_UNIT_NOC_SOCKET, 20, &leaf4_gate_lock }, | |
1165 | { 107, "gpio0_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 5, CLK_UNIT_NOC_SOCKET, 19, &leaf4_gate_lock }, | |
1166 | { 108, "nand_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 6, 0, 0, &leaf4_gate_lock }, | |
1167 | { 109, "sdio01_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 7, 0, 0, &leaf4_gate_lock }, | |
1168 | { 110, "sys2pci2_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 8, CLK_UNIT_NOC_CLOCK, 13, &leaf4_gate_lock }, | |
1169 | { 111, "sdio01_sdphy01", "mediam_sdphy01", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 9, 0, 0, &leaf4_gate_lock }, | |
1170 | { 112, "nand_nand", "mediam_nand", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 10, CLK_UNIT_NOC_CLOCK, 14, &leaf4_gate_lock }, | |
1171 | { 113, "usb0_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 11, CLK_UNIT_NOC_CLOCK, 15, &leaf4_gate_lock }, | |
1172 | { 114, "usb1_usb", "mediam_usb", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 12, CLK_UNIT_NOC_CLOCK, 16, &leaf4_gate_lock }, | |
1173 | { 115, "usbphy0_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 13, 0, 0, &leaf4_gate_lock }, | |
1174 | { 116, "usbphy1_usbphy", "mediam_usbphy", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 14, 0, 0, &leaf4_gate_lock }, | |
1175 | { 117, "thmediam_io", "mediam_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN4_SET, 15, 0, 0, &leaf4_gate_lock }, | |
1176 | { 118, "memc_mem", "mempll_clk1", CLK_IGNORE_UNUSED, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 0, 0, 0, &leaf5_gate_lock }, | |
1177 | { 119, "dapa_mem", "mempll_clk1", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 1, 0, 0, &leaf5_gate_lock }, | |
1178 | { 120, "nocddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 2, 0, 0, &leaf5_gate_lock }, | |
1179 | { 121, "thddrm_nocr", "ddrm_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN5_SET, 3, 0, 0, &leaf5_gate_lock }, | |
1180 | { 122, "spram1_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 0, CLK_UNIT_NOC_SOCKET, 9, &leaf6_gate_lock }, | |
1181 | { 123, "spram2_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 1, CLK_UNIT_NOC_SOCKET, 10, &leaf6_gate_lock }, | |
1182 | { 124, "coresight_cpudiv2", "cpum_cpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 2, 0, 0, &leaf6_gate_lock }, | |
1183 | { 125, "coresight_tpiu", "cpum_tpiu", 0, SIRFSOC_CLKC_LEAF_CLK_EN6_SET, 3, 0, 0, &leaf6_gate_lock }, | |
1184 | { 126, "graphic_gpu", "gpum_gpu", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 0, CLK_UNIT_NOC_CLOCK, 0, &leaf7_gate_lock }, | |
1185 | { 127, "vss_sdr", "gpum_sdr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 1, CLK_UNIT_NOC_CLOCK, 11, &leaf7_gate_lock }, | |
1186 | { 128, "thgpum_nocr", "gpum_nocr", 0, SIRFSOC_CLKC_LEAF_CLK_EN7_SET, 2, 0, 0, &leaf7_gate_lock }, | |
1187 | { 129, "a7ca_btss", "btm_btss", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 1, 0, 0, &leaf8_gate_lock }, | |
1188 | { 130, "dmac4_io", "a7ca_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 2, 0, 0, &leaf8_gate_lock }, | |
1189 | { 131, "uart6_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 3, 0, 0, &leaf8_gate_lock }, | |
1190 | { 132, "usp3_io", "dmac4_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 4, 0, 0, &leaf8_gate_lock }, | |
1191 | { 133, "a7ca_io", "noc_btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 5, 0, 0, &leaf8_gate_lock }, | |
1192 | { 134, "noc_btm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 6, 0, 0, &leaf8_gate_lock }, | |
1193 | { 135, "thbtm_io", "btm_io", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 7, 0, 0, &leaf8_gate_lock }, | |
1194 | { 136, "btslow", "xinw_fixdiv_btslow", 0, SIRFSOC_CLKC_ROOT_CLK_EN1_SET, 25, 0, 0, &root1_gate_lock }, | |
1195 | { 137, "a7ca_btslow", "btslow", 0, SIRFSOC_CLKC_LEAF_CLK_EN8_SET, 0, 0, 0, &leaf8_gate_lock }, | |
1196 | { 138, "pwm_io", "io_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 0, 0, 0, &leaf0_gate_lock }, | |
1197 | { 139, "pwm_xin", "xin", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 1, 0, 0, &leaf0_gate_lock }, | |
1198 | { 140, "pwm_xinw", "xinw", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 2, 0, 0, &leaf0_gate_lock }, | |
1199 | { 141, "thcgum_sys", "sys_mux", 0, SIRFSOC_CLKC_LEAF_CLK_EN0_SET, 3, 0, 0, &leaf0_gate_lock }, | |
301c5d29 ZS |
1200 | }; |
1201 | ||
b1062298 | 1202 | static struct clk *atlas7_clks[ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list)]; |
301c5d29 ZS |
1203 | |
1204 | static int unit_clk_is_enabled(struct clk_hw *hw) | |
1205 | { | |
1206 | struct clk_unit *clk = to_unitclk(hw); | |
1207 | u32 reg; | |
1208 | ||
1209 | reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_STAT - SIRFSOC_CLKC_ROOT_CLK_EN0_SET; | |
1210 | ||
1211 | return !!(clkc_readl(reg) & BIT(clk->bit)); | |
1212 | } | |
1213 | ||
1214 | static int unit_clk_enable(struct clk_hw *hw) | |
1215 | { | |
1216 | u32 reg; | |
1217 | struct clk_unit *clk = to_unitclk(hw); | |
1218 | unsigned long flags; | |
1219 | ||
1220 | reg = clk->regofs; | |
1221 | ||
1222 | spin_lock_irqsave(clk->lock, flags); | |
1223 | clkc_writel(BIT(clk->bit), reg); | |
a3ff2337 GZ |
1224 | if (clk->type == CLK_UNIT_NOC_CLOCK) |
1225 | clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR); | |
1226 | else if (clk->type == CLK_UNIT_NOC_SOCKET) | |
1227 | clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_SET); | |
1228 | ||
301c5d29 ZS |
1229 | spin_unlock_irqrestore(clk->lock, flags); |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static void unit_clk_disable(struct clk_hw *hw) | |
1234 | { | |
a3ff2337 GZ |
1235 | u32 reg; |
1236 | u32 i = 0; | |
301c5d29 ZS |
1237 | struct clk_unit *clk = to_unitclk(hw); |
1238 | unsigned long flags; | |
1239 | ||
1240 | reg = clk->regofs + SIRFSOC_CLKC_ROOT_CLK_EN0_CLR - SIRFSOC_CLKC_ROOT_CLK_EN0_SET; | |
301c5d29 | 1241 | spin_lock_irqsave(clk->lock, flags); |
a3ff2337 GZ |
1242 | if (clk->type == CLK_UNIT_NOC_CLOCK) { |
1243 | clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_SET); | |
1244 | while (!(clkc_readl(SIRFSOC_NOC_CLK_IDLE_STATUS) & | |
1245 | BIT(clk->idle_bit)) && (i++ < 100)) { | |
1246 | cpu_relax(); | |
1247 | udelay(10); | |
1248 | } | |
1249 | ||
1250 | if (i == 100) { | |
1251 | pr_err("unit NoC Clock disconnect Error:timeout\n"); | |
1252 | /*once timeout, undo idlereq by CLR*/ | |
1253 | clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_IDLEREQ_CLR); | |
1254 | goto err; | |
1255 | } | |
1256 | ||
1257 | } else if (clk->type == CLK_UNIT_NOC_SOCKET) | |
1258 | clkc_writel(BIT(clk->idle_bit), SIRFSOC_NOC_CLK_SLVRDY_CLR); | |
1259 | ||
301c5d29 | 1260 | clkc_writel(BIT(clk->bit), reg); |
a3ff2337 | 1261 | err: |
301c5d29 ZS |
1262 | spin_unlock_irqrestore(clk->lock, flags); |
1263 | } | |
1264 | ||
1265 | static const struct clk_ops unit_clk_ops = { | |
1266 | .is_enabled = unit_clk_is_enabled, | |
1267 | .enable = unit_clk_enable, | |
1268 | .disable = unit_clk_disable, | |
1269 | }; | |
1270 | ||
1271 | static struct clk * __init | |
1272 | atlas7_unit_clk_register(struct device *dev, const char *name, | |
1273 | const char * const parent_name, unsigned long flags, | |
a3ff2337 | 1274 | u32 regofs, u8 bit, u32 type, u8 idle_bit, spinlock_t *lock) |
301c5d29 ZS |
1275 | { |
1276 | struct clk *clk; | |
1277 | struct clk_unit *unit; | |
1278 | struct clk_init_data init; | |
1279 | ||
1280 | unit = kzalloc(sizeof(*unit), GFP_KERNEL); | |
1281 | if (!unit) | |
1282 | return ERR_PTR(-ENOMEM); | |
1283 | ||
1284 | init.name = name; | |
1285 | init.parent_names = &parent_name; | |
1286 | init.num_parents = 1; | |
1287 | init.ops = &unit_clk_ops; | |
1288 | init.flags = flags; | |
1289 | ||
1290 | unit->hw.init = &init; | |
1291 | unit->regofs = regofs; | |
1292 | unit->bit = bit; | |
a3ff2337 GZ |
1293 | |
1294 | unit->type = type; | |
1295 | unit->idle_bit = idle_bit; | |
301c5d29 ZS |
1296 | unit->lock = lock; |
1297 | ||
1298 | clk = clk_register(dev, &unit->hw); | |
1299 | if (IS_ERR(clk)) | |
1300 | kfree(unit); | |
1301 | ||
1302 | return clk; | |
1303 | } | |
1304 | ||
1305 | static struct atlas7_reset_desc atlas7_reset_unit[] = { | |
1306 | { "PWM", 0x0244, 0, 0x0320, 0, &leaf0_gate_lock }, /* 0-5 */ | |
1307 | { "THCGUM", 0x0244, 3, 0x0320, 1, &leaf0_gate_lock }, | |
1308 | { "CVD", 0x04A0, 0, 0x032C, 0, &leaf1_gate_lock }, | |
1309 | { "TIMER", 0x04A0, 1, 0x032C, 1, &leaf1_gate_lock }, | |
1310 | { "PULSEC", 0x04A0, 2, 0x032C, 2, &leaf1_gate_lock }, | |
1311 | { "TSC", 0x04A0, 3, 0x032C, 3, &leaf1_gate_lock }, | |
1312 | { "IOCTOP", 0x04A0, 4, 0x032C, 4, &leaf1_gate_lock }, /* 6-10 */ | |
1313 | { "RSC", 0x04A0, 5, 0x032C, 5, &leaf1_gate_lock }, | |
1314 | { "DVM", 0x04A0, 6, 0x032C, 6, &leaf1_gate_lock }, | |
1315 | { "LVDS", 0x04A0, 7, 0x032C, 7, &leaf1_gate_lock }, | |
1316 | { "KAS", 0x04A0, 8, 0x032C, 8, &leaf1_gate_lock }, | |
1317 | { "AC97", 0x04A0, 9, 0x032C, 9, &leaf1_gate_lock }, /* 11-15 */ | |
1318 | { "USP0", 0x04A0, 10, 0x032C, 10, &leaf1_gate_lock }, | |
1319 | { "USP1", 0x04A0, 11, 0x032C, 11, &leaf1_gate_lock }, | |
1320 | { "USP2", 0x04A0, 12, 0x032C, 12, &leaf1_gate_lock }, | |
1321 | { "DMAC2", 0x04A0, 13, 0x032C, 13, &leaf1_gate_lock }, | |
1322 | { "DMAC3", 0x04A0, 14, 0x032C, 14, &leaf1_gate_lock }, /* 16-20 */ | |
1323 | { "AUDIO", 0x04A0, 15, 0x032C, 15, &leaf1_gate_lock }, | |
1324 | { "I2S1", 0x04A0, 17, 0x032C, 16, &leaf1_gate_lock }, | |
1325 | { "PMU_AUDIO", 0x04A0, 22, 0x032C, 17, &leaf1_gate_lock }, | |
1326 | { "THAUDMSCM", 0x04A0, 23, 0x032C, 18, &leaf1_gate_lock }, | |
1327 | { "SYS2PCI", 0x04B8, 0, 0x0338, 0, &leaf2_gate_lock }, /* 21-25 */ | |
1328 | { "PCIARB", 0x04B8, 1, 0x0338, 1, &leaf2_gate_lock }, | |
1329 | { "PCICOPY", 0x04B8, 2, 0x0338, 2, &leaf2_gate_lock }, | |
1330 | { "ROM", 0x04B8, 3, 0x0338, 3, &leaf2_gate_lock }, | |
1331 | { "SDIO23", 0x04B8, 4, 0x0338, 4, &leaf2_gate_lock }, | |
1332 | { "SDIO45", 0x04B8, 5, 0x0338, 5, &leaf2_gate_lock }, /* 26-30 */ | |
1333 | { "SDIO67", 0x04B8, 6, 0x0338, 6, &leaf2_gate_lock }, | |
1334 | { "VIP1", 0x04B8, 7, 0x0338, 7, &leaf2_gate_lock }, | |
1335 | { "VPP0", 0x04B8, 11, 0x0338, 8, &leaf2_gate_lock }, | |
1336 | { "LCD0", 0x04B8, 12, 0x0338, 9, &leaf2_gate_lock }, | |
1337 | { "VPP1", 0x04B8, 13, 0x0338, 10, &leaf2_gate_lock }, /* 31-35 */ | |
1338 | { "LCD1", 0x04B8, 14, 0x0338, 11, &leaf2_gate_lock }, | |
1339 | { "DCU", 0x04B8, 15, 0x0338, 12, &leaf2_gate_lock }, | |
1340 | { "GPIO", 0x04B8, 18, 0x0338, 13, &leaf2_gate_lock }, | |
1341 | { "DAPA_VDIFM", 0x04B8, 17, 0x0338, 15, &leaf2_gate_lock }, | |
1342 | { "THVDIFM", 0x04B8, 19, 0x0338, 16, &leaf2_gate_lock }, /* 36-40 */ | |
1343 | { "RGMII", 0x04D0, 0, 0x0344, 0, &leaf3_gate_lock }, | |
1344 | { "GMAC", 0x04D0, 1, 0x0344, 1, &leaf3_gate_lock }, | |
1345 | { "UART1", 0x04D0, 2, 0x0344, 2, &leaf3_gate_lock }, | |
1346 | { "DMAC0", 0x04D0, 3, 0x0344, 3, &leaf3_gate_lock }, | |
1347 | { "UART0", 0x04D0, 4, 0x0344, 4, &leaf3_gate_lock }, /* 41-45 */ | |
1348 | { "UART2", 0x04D0, 5, 0x0344, 5, &leaf3_gate_lock }, | |
1349 | { "UART3", 0x04D0, 6, 0x0344, 6, &leaf3_gate_lock }, | |
1350 | { "UART4", 0x04D0, 7, 0x0344, 7, &leaf3_gate_lock }, | |
1351 | { "UART5", 0x04D0, 8, 0x0344, 8, &leaf3_gate_lock }, | |
1352 | { "SPI1", 0x04D0, 9, 0x0344, 9, &leaf3_gate_lock }, /* 46-50 */ | |
1353 | { "GNSS_SYS_M0", 0x04D0, 10, 0x0344, 10, &leaf3_gate_lock }, | |
1354 | { "CANBUS1", 0x04D0, 12, 0x0344, 11, &leaf3_gate_lock }, | |
1355 | { "CCSEC", 0x04D0, 15, 0x0344, 12, &leaf3_gate_lock }, | |
1356 | { "CCPUB", 0x04D0, 16, 0x0344, 13, &leaf3_gate_lock }, | |
1357 | { "DAPA_GNSSM", 0x04D0, 13, 0x0344, 14, &leaf3_gate_lock }, /* 51-55 */ | |
1358 | { "THGNSSM", 0x04D0, 14, 0x0344, 15, &leaf3_gate_lock }, | |
1359 | { "VDEC", 0x04E8, 0, 0x0350, 0, &leaf4_gate_lock }, | |
1360 | { "JPENC", 0x04E8, 1, 0x0350, 1, &leaf4_gate_lock }, | |
1361 | { "G2D", 0x04E8, 2, 0x0350, 2, &leaf4_gate_lock }, | |
1362 | { "I2C0", 0x04E8, 3, 0x0350, 3, &leaf4_gate_lock }, /* 56-60 */ | |
1363 | { "I2C1", 0x04E8, 4, 0x0350, 4, &leaf4_gate_lock }, | |
1364 | { "GPIO0", 0x04E8, 5, 0x0350, 5, &leaf4_gate_lock }, | |
1365 | { "NAND", 0x04E8, 6, 0x0350, 6, &leaf4_gate_lock }, | |
1366 | { "SDIO01", 0x04E8, 7, 0x0350, 7, &leaf4_gate_lock }, | |
1367 | { "SYS2PCI2", 0x04E8, 8, 0x0350, 8, &leaf4_gate_lock }, /* 61-65 */ | |
1368 | { "USB0", 0x04E8, 11, 0x0350, 9, &leaf4_gate_lock }, | |
1369 | { "USB1", 0x04E8, 12, 0x0350, 10, &leaf4_gate_lock }, | |
1370 | { "THMEDIAM", 0x04E8, 15, 0x0350, 11, &leaf4_gate_lock }, | |
1371 | { "MEMC_DDRPHY", 0x0500, 0, 0x035C, 0, &leaf5_gate_lock }, | |
1372 | { "MEMC_UPCTL", 0x0500, 0, 0x035C, 1, &leaf5_gate_lock }, /* 66-70 */ | |
1373 | { "DAPA_MEM", 0x0500, 1, 0x035C, 2, &leaf5_gate_lock }, | |
1374 | { "MEMC_MEMDIV", 0x0500, 0, 0x035C, 3, &leaf5_gate_lock }, | |
1375 | { "THDDRM", 0x0500, 3, 0x035C, 4, &leaf5_gate_lock }, | |
1376 | { "CORESIGHT", 0x0518, 3, 0x0368, 13, &leaf6_gate_lock }, | |
1377 | { "THCPUM", 0x0518, 4, 0x0368, 17, &leaf6_gate_lock }, /* 71-75 */ | |
1378 | { "GRAPHIC", 0x0530, 0, 0x0374, 0, &leaf7_gate_lock }, | |
1379 | { "VSS_SDR", 0x0530, 1, 0x0374, 1, &leaf7_gate_lock }, | |
1380 | { "THGPUM", 0x0530, 2, 0x0374, 2, &leaf7_gate_lock }, | |
1381 | { "DMAC4", 0x0548, 2, 0x0380, 1, &leaf8_gate_lock }, | |
1382 | { "UART6", 0x0548, 3, 0x0380, 2, &leaf8_gate_lock }, /* 76- */ | |
1383 | { "USP3", 0x0548, 4, 0x0380, 3, &leaf8_gate_lock }, | |
1384 | { "THBTM", 0x0548, 5, 0x0380, 5, &leaf8_gate_lock }, | |
1385 | { "A7CA", 0x0548, 1, 0x0380, 0, &leaf8_gate_lock }, | |
1386 | { "A7CA_APB", 0x0548, 5, 0x0380, 4, &leaf8_gate_lock }, | |
1387 | }; | |
1388 | ||
1389 | static int atlas7_reset_module(struct reset_controller_dev *rcdev, | |
1390 | unsigned long reset_idx) | |
1391 | { | |
1392 | struct atlas7_reset_desc *reset = &atlas7_reset_unit[reset_idx]; | |
1393 | unsigned long flags; | |
1394 | ||
1395 | /* | |
1396 | * HW suggest unit reset sequence: | |
1397 | * assert sw reset (0) | |
1398 | * setting sw clk_en to if the clock was disabled before reset | |
1399 | * delay 16 clocks | |
1400 | * disable clock (sw clk_en = 0) | |
1401 | * de-assert reset (1) | |
1402 | * after this sequence, restore clock or not is decided by SW | |
1403 | */ | |
1404 | ||
1405 | spin_lock_irqsave(reset->lock, flags); | |
1406 | /* clock enable or not */ | |
1407 | if (clkc_readl(reset->clk_ofs + 8) & (1 << reset->clk_bit)) { | |
1408 | clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4); | |
1409 | udelay(2); | |
1410 | clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4); | |
1411 | clkc_writel(1 << reset->rst_bit, reset->rst_ofs); | |
1412 | /* restore clock enable */ | |
1413 | clkc_writel(1 << reset->clk_bit, reset->clk_ofs); | |
1414 | } else { | |
1415 | clkc_writel(1 << reset->rst_bit, reset->rst_ofs + 4); | |
1416 | clkc_writel(1 << reset->clk_bit, reset->clk_ofs); | |
1417 | udelay(2); | |
1418 | clkc_writel(1 << reset->clk_bit, reset->clk_ofs + 4); | |
1419 | clkc_writel(1 << reset->rst_bit, reset->rst_ofs); | |
1420 | } | |
1421 | spin_unlock_irqrestore(reset->lock, flags); | |
1422 | ||
1423 | return 0; | |
1424 | } | |
1425 | ||
b1b69c5d | 1426 | static const struct reset_control_ops atlas7_rst_ops = { |
301c5d29 ZS |
1427 | .reset = atlas7_reset_module, |
1428 | }; | |
1429 | ||
1430 | static struct reset_controller_dev atlas7_rst_ctlr = { | |
1431 | .ops = &atlas7_rst_ops, | |
1432 | .owner = THIS_MODULE, | |
1433 | .of_reset_n_cells = 1, | |
1434 | }; | |
1435 | ||
1436 | static void __init atlas7_clk_init(struct device_node *np) | |
1437 | { | |
1438 | struct clk *clk; | |
1439 | struct atlas7_div_init_data *div; | |
1440 | struct atlas7_mux_init_data *mux; | |
1441 | struct atlas7_unit_init_data *unit; | |
1442 | int i; | |
1443 | int ret; | |
1444 | ||
1445 | sirfsoc_clk_vbase = of_iomap(np, 0); | |
1446 | if (!sirfsoc_clk_vbase) | |
1447 | panic("unable to map clkc registers\n"); | |
1448 | ||
1449 | of_node_put(np); | |
1450 | ||
1451 | clk = clk_register(NULL, &clk_cpupll.hw); | |
1452 | BUG_ON(!clk); | |
1453 | clk = clk_register(NULL, &clk_mempll.hw); | |
1454 | BUG_ON(!clk); | |
1455 | clk = clk_register(NULL, &clk_sys0pll.hw); | |
1456 | BUG_ON(!clk); | |
1457 | clk = clk_register(NULL, &clk_sys1pll.hw); | |
1458 | BUG_ON(!clk); | |
1459 | clk = clk_register(NULL, &clk_sys2pll.hw); | |
1460 | BUG_ON(!clk); | |
1461 | clk = clk_register(NULL, &clk_sys3pll.hw); | |
1462 | BUG_ON(!clk); | |
1463 | ||
1464 | clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0, | |
1465 | sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 0, 3, 0, | |
1466 | pll_div_table, &cpupll_ctrl1_lock); | |
1467 | BUG_ON(!clk); | |
1468 | clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0, | |
1469 | sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 4, 3, 0, | |
1470 | pll_div_table, &cpupll_ctrl1_lock); | |
1471 | BUG_ON(!clk); | |
1472 | clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0, | |
1473 | sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, 8, 3, 0, | |
1474 | pll_div_table, &cpupll_ctrl1_lock); | |
1475 | BUG_ON(!clk); | |
1476 | ||
1477 | clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0, | |
1478 | sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 0, 3, 0, | |
1479 | pll_div_table, &mempll_ctrl1_lock); | |
1480 | BUG_ON(!clk); | |
1481 | clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0, | |
1482 | sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 4, 3, 0, | |
1483 | pll_div_table, &mempll_ctrl1_lock); | |
1484 | BUG_ON(!clk); | |
1485 | clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0, | |
1486 | sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, 8, 3, 0, | |
1487 | pll_div_table, &mempll_ctrl1_lock); | |
1488 | BUG_ON(!clk); | |
1489 | ||
1490 | clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0, | |
1491 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 0, 3, 0, | |
1492 | pll_div_table, &sys0pll_ctrl1_lock); | |
1493 | BUG_ON(!clk); | |
1494 | clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0, | |
1495 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 4, 3, 0, | |
1496 | pll_div_table, &sys0pll_ctrl1_lock); | |
1497 | BUG_ON(!clk); | |
1498 | clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0, | |
1499 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, 8, 3, 0, | |
1500 | pll_div_table, &sys0pll_ctrl1_lock); | |
1501 | BUG_ON(!clk); | |
1502 | clk = clk_register_fixed_factor(NULL, "sys0pll_fixdiv", "sys0pll_vco", | |
1503 | CLK_SET_RATE_PARENT, 1, 2); | |
1504 | ||
1505 | clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0, | |
1506 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 0, 3, 0, | |
1507 | pll_div_table, &sys1pll_ctrl1_lock); | |
1508 | BUG_ON(!clk); | |
1509 | clk = clk_register_divider_table(NULL, "sys1pll_div2", "sys1pll_vco", 0, | |
1510 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 4, 3, 0, | |
1511 | pll_div_table, &sys1pll_ctrl1_lock); | |
1512 | BUG_ON(!clk); | |
1513 | clk = clk_register_divider_table(NULL, "sys1pll_div3", "sys1pll_vco", 0, | |
1514 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, 8, 3, 0, | |
1515 | pll_div_table, &sys1pll_ctrl1_lock); | |
1516 | BUG_ON(!clk); | |
1517 | clk = clk_register_fixed_factor(NULL, "sys1pll_fixdiv", "sys1pll_vco", | |
1518 | CLK_SET_RATE_PARENT, 1, 2); | |
1519 | ||
1520 | clk = clk_register_divider_table(NULL, "sys2pll_div1", "sys2pll_vco", 0, | |
1521 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 0, 3, 0, | |
1522 | pll_div_table, &sys2pll_ctrl1_lock); | |
1523 | BUG_ON(!clk); | |
1524 | clk = clk_register_divider_table(NULL, "sys2pll_div2", "sys2pll_vco", 0, | |
1525 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 4, 3, 0, | |
1526 | pll_div_table, &sys2pll_ctrl1_lock); | |
1527 | BUG_ON(!clk); | |
1528 | clk = clk_register_divider_table(NULL, "sys2pll_div3", "sys2pll_vco", 0, | |
1529 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, 8, 3, 0, | |
1530 | pll_div_table, &sys2pll_ctrl1_lock); | |
1531 | BUG_ON(!clk); | |
1532 | clk = clk_register_fixed_factor(NULL, "sys2pll_fixdiv", "sys2pll_vco", | |
1533 | CLK_SET_RATE_PARENT, 1, 2); | |
1534 | ||
1535 | clk = clk_register_divider_table(NULL, "sys3pll_div1", "sys3pll_vco", 0, | |
1536 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 0, 3, 0, | |
1537 | pll_div_table, &sys3pll_ctrl1_lock); | |
1538 | BUG_ON(!clk); | |
1539 | clk = clk_register_divider_table(NULL, "sys3pll_div2", "sys3pll_vco", 0, | |
1540 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 4, 3, 0, | |
1541 | pll_div_table, &sys3pll_ctrl1_lock); | |
1542 | BUG_ON(!clk); | |
1543 | clk = clk_register_divider_table(NULL, "sys3pll_div3", "sys3pll_vco", 0, | |
1544 | sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, 8, 3, 0, | |
1545 | pll_div_table, &sys3pll_ctrl1_lock); | |
1546 | BUG_ON(!clk); | |
1547 | clk = clk_register_fixed_factor(NULL, "sys3pll_fixdiv", "sys3pll_vco", | |
1548 | CLK_SET_RATE_PARENT, 1, 2); | |
1549 | ||
1550 | BUG_ON(!clk); | |
1551 | clk = clk_register_fixed_factor(NULL, "xinw_fixdiv_btslow", "xinw", | |
1552 | CLK_SET_RATE_PARENT, 1, 4); | |
1553 | ||
1554 | BUG_ON(!clk); | |
1555 | clk = clk_register_gate(NULL, "cpupll_clk1", "cpupll_div1", | |
1556 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, | |
1557 | 12, 0, &cpupll_ctrl1_lock); | |
1558 | BUG_ON(!clk); | |
1559 | clk = clk_register_gate(NULL, "cpupll_clk2", "cpupll_div2", | |
1560 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, | |
1561 | 13, 0, &cpupll_ctrl1_lock); | |
1562 | BUG_ON(!clk); | |
1563 | clk = clk_register_gate(NULL, "cpupll_clk3", "cpupll_div3", | |
1564 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_CPUPLL_AB_CTRL1, | |
1565 | 14, 0, &cpupll_ctrl1_lock); | |
1566 | BUG_ON(!clk); | |
1567 | ||
1568 | clk = clk_register_gate(NULL, "mempll_clk1", "mempll_div1", | |
1569 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
1570 | sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, | |
1571 | 12, 0, &mempll_ctrl1_lock); | |
1572 | BUG_ON(!clk); | |
1573 | clk = clk_register_gate(NULL, "mempll_clk2", "mempll_div2", | |
1574 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, | |
1575 | 13, 0, &mempll_ctrl1_lock); | |
1576 | BUG_ON(!clk); | |
1577 | clk = clk_register_gate(NULL, "mempll_clk3", "mempll_div3", | |
1578 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_MEMPLL_AB_CTRL1, | |
1579 | 14, 0, &mempll_ctrl1_lock); | |
1580 | BUG_ON(!clk); | |
1581 | ||
1582 | clk = clk_register_gate(NULL, "sys0pll_clk1", "sys0pll_div1", | |
1583 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, | |
1584 | 12, 0, &sys0pll_ctrl1_lock); | |
1585 | BUG_ON(!clk); | |
1586 | clk = clk_register_gate(NULL, "sys0pll_clk2", "sys0pll_div2", | |
1587 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, | |
1588 | 13, 0, &sys0pll_ctrl1_lock); | |
1589 | BUG_ON(!clk); | |
1590 | clk = clk_register_gate(NULL, "sys0pll_clk3", "sys0pll_div3", | |
1591 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS0PLL_AB_CTRL1, | |
1592 | 14, 0, &sys0pll_ctrl1_lock); | |
1593 | BUG_ON(!clk); | |
1594 | ||
1595 | clk = clk_register_gate(NULL, "sys1pll_clk1", "sys1pll_div1", | |
1596 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, | |
1597 | 12, 0, &sys1pll_ctrl1_lock); | |
1598 | BUG_ON(!clk); | |
1599 | clk = clk_register_gate(NULL, "sys1pll_clk2", "sys1pll_div2", | |
1600 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, | |
1601 | 13, 0, &sys1pll_ctrl1_lock); | |
1602 | BUG_ON(!clk); | |
1603 | clk = clk_register_gate(NULL, "sys1pll_clk3", "sys1pll_div3", | |
1604 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS1PLL_AB_CTRL1, | |
1605 | 14, 0, &sys1pll_ctrl1_lock); | |
1606 | BUG_ON(!clk); | |
1607 | ||
1608 | clk = clk_register_gate(NULL, "sys2pll_clk1", "sys2pll_div1", | |
1609 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, | |
1610 | 12, 0, &sys2pll_ctrl1_lock); | |
1611 | BUG_ON(!clk); | |
1612 | clk = clk_register_gate(NULL, "sys2pll_clk2", "sys2pll_div2", | |
1613 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, | |
1614 | 13, 0, &sys2pll_ctrl1_lock); | |
1615 | BUG_ON(!clk); | |
1616 | clk = clk_register_gate(NULL, "sys2pll_clk3", "sys2pll_div3", | |
1617 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS2PLL_AB_CTRL1, | |
1618 | 14, 0, &sys2pll_ctrl1_lock); | |
1619 | BUG_ON(!clk); | |
1620 | ||
1621 | clk = clk_register_gate(NULL, "sys3pll_clk1", "sys3pll_div1", | |
1622 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, | |
1623 | 12, 0, &sys3pll_ctrl1_lock); | |
1624 | BUG_ON(!clk); | |
1625 | clk = clk_register_gate(NULL, "sys3pll_clk2", "sys3pll_div2", | |
1626 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, | |
1627 | 13, 0, &sys3pll_ctrl1_lock); | |
1628 | BUG_ON(!clk); | |
1629 | clk = clk_register_gate(NULL, "sys3pll_clk3", "sys3pll_div3", | |
1630 | CLK_SET_RATE_PARENT, sirfsoc_clk_vbase + SIRFSOC_CLKC_SYS3PLL_AB_CTRL1, | |
1631 | 14, 0, &sys3pll_ctrl1_lock); | |
1632 | BUG_ON(!clk); | |
1633 | ||
1634 | clk = clk_register(NULL, &clk_audio_dto.hw); | |
1635 | BUG_ON(!clk); | |
1636 | ||
1637 | clk = clk_register(NULL, &clk_disp0_dto.hw); | |
1638 | BUG_ON(!clk); | |
1639 | ||
1640 | clk = clk_register(NULL, &clk_disp1_dto.hw); | |
1641 | BUG_ON(!clk); | |
1642 | ||
1643 | for (i = 0; i < ARRAY_SIZE(divider_list); i++) { | |
1644 | div = ÷r_list[i]; | |
1645 | clk = clk_register_divider(NULL, div->div_name, | |
1646 | div->parent_name, div->divider_flags, sirfsoc_clk_vbase + div->div_offset, | |
1647 | div->shift, div->width, 0, div->lock); | |
1648 | BUG_ON(!clk); | |
1649 | clk = clk_register_gate(NULL, div->gate_name, div->div_name, | |
1650 | div->gate_flags, sirfsoc_clk_vbase + div->gate_offset, | |
1651 | div->gate_bit, 0, div->lock); | |
1652 | BUG_ON(!clk); | |
1653 | } | |
1654 | /* ignore selector status register check */ | |
1655 | for (i = 0; i < ARRAY_SIZE(mux_list); i++) { | |
1656 | mux = &mux_list[i]; | |
1657 | clk = clk_register_mux(NULL, mux->mux_name, mux->parent_names, | |
1658 | mux->parent_num, mux->flags, | |
1659 | sirfsoc_clk_vbase + mux->mux_offset, | |
1660 | mux->shift, mux->width, | |
1661 | mux->mux_flags, NULL); | |
b1062298 | 1662 | atlas7_clks[ARRAY_SIZE(unit_list) + i] = clk; |
301c5d29 ZS |
1663 | BUG_ON(!clk); |
1664 | } | |
1665 | ||
1666 | for (i = 0; i < ARRAY_SIZE(unit_list); i++) { | |
1667 | unit = &unit_list[i]; | |
1668 | atlas7_clks[i] = atlas7_unit_clk_register(NULL, unit->unit_name, unit->parent_name, | |
a3ff2337 | 1669 | unit->flags, unit->regofs, unit->bit, unit->type, unit->idle_bit, unit->lock); |
301c5d29 ZS |
1670 | BUG_ON(!atlas7_clks[i]); |
1671 | } | |
1672 | ||
1673 | clk_data.clks = atlas7_clks; | |
b1062298 | 1674 | clk_data.clk_num = ARRAY_SIZE(unit_list) + ARRAY_SIZE(mux_list); |
301c5d29 ZS |
1675 | |
1676 | ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
1677 | BUG_ON(ret); | |
1678 | ||
1679 | atlas7_rst_ctlr.of_node = np; | |
1680 | atlas7_rst_ctlr.nr_resets = ARRAY_SIZE(atlas7_reset_unit); | |
1681 | reset_controller_register(&atlas7_rst_ctlr); | |
1682 | } | |
1683 | CLK_OF_DECLARE(atlas7_clk, "sirf,atlas7-car", atlas7_clk_init); |