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97259e99 ST |
1 | /* |
2 | * Copyright 2011-2012 Calxeda, Inc. | |
3 | * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * Based from clk-highbank.c | |
16 | * | |
17 | */ | |
b0af24b5 | 18 | #include <linux/slab.h> |
97259e99 ST |
19 | #include <linux/clk-provider.h> |
20 | #include <linux/io.h> | |
21 | #include <linux/of.h> | |
a30d27ed | 22 | #include <linux/of_address.h> |
97259e99 ST |
23 | |
24 | #include "clk.h" | |
25 | ||
26 | /* Clock bypass bits */ | |
27 | #define MAINPLL_BYPASS (1<<0) | |
28 | #define SDRAMPLL_BYPASS (1<<1) | |
29 | #define SDRAMPLL_SRC_BYPASS (1<<2) | |
30 | #define PERPLL_BYPASS (1<<3) | |
31 | #define PERPLL_SRC_BYPASS (1<<4) | |
32 | ||
33 | #define SOCFPGA_PLL_BG_PWRDWN 0 | |
34 | #define SOCFPGA_PLL_EXT_ENA 1 | |
35 | #define SOCFPGA_PLL_PWR_DOWN 2 | |
36 | #define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8 | |
37 | #define SOCFPGA_PLL_DIVF_SHIFT 3 | |
38 | #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 | |
39 | #define SOCFPGA_PLL_DIVQ_SHIFT 16 | |
40 | ||
b89cd950 DN |
41 | #define CLK_MGR_PLL_CLK_SRC_SHIFT 22 |
42 | #define CLK_MGR_PLL_CLK_SRC_MASK 0x3 | |
43 | ||
97259e99 ST |
44 | #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw) |
45 | ||
a30d27ed DN |
46 | void __iomem *clk_mgr_base_addr; |
47 | ||
97259e99 ST |
48 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, |
49 | unsigned long parent_rate) | |
50 | { | |
51 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); | |
5585f731 DN |
52 | unsigned long divf, divq, reg; |
53 | unsigned long long vco_freq; | |
97259e99 ST |
54 | unsigned long bypass; |
55 | ||
56 | reg = readl(socfpgaclk->hw.reg); | |
57 | bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); | |
58 | if (bypass & MAINPLL_BYPASS) | |
59 | return parent_rate; | |
60 | ||
61 | divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; | |
62 | divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; | |
5585f731 DN |
63 | vco_freq = (unsigned long long)parent_rate * (divf + 1); |
64 | do_div(vco_freq, (1 + divq)); | |
65 | return (unsigned long)vco_freq; | |
97259e99 ST |
66 | } |
67 | ||
b89cd950 DN |
68 | static u8 clk_pll_get_parent(struct clk_hw *hwclk) |
69 | { | |
70 | u32 pll_src; | |
71 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); | |
72 | ||
73 | pll_src = readl(socfpgaclk->hw.reg); | |
74 | return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) & | |
75 | CLK_MGR_PLL_CLK_SRC_MASK; | |
76 | } | |
77 | ||
97259e99 ST |
78 | static struct clk_ops clk_pll_ops = { |
79 | .recalc_rate = clk_pll_recalc_rate, | |
b89cd950 | 80 | .get_parent = clk_pll_get_parent, |
97259e99 ST |
81 | }; |
82 | ||
83 | static __init struct clk *__socfpga_pll_init(struct device_node *node, | |
84 | const struct clk_ops *ops) | |
85 | { | |
86 | u32 reg; | |
87 | struct clk *clk; | |
88 | struct socfpga_pll *pll_clk; | |
89 | const char *clk_name = node->name; | |
b89cd950 | 90 | const char *parent_name[SOCFPGA_MAX_PARENTS]; |
97259e99 | 91 | struct clk_init_data init; |
a30d27ed | 92 | struct device_node *clkmgr_np; |
97259e99 ST |
93 | int rc; |
94 | ||
95 | of_property_read_u32(node, "reg", ®); | |
96 | ||
97 | pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); | |
98 | if (WARN_ON(!pll_clk)) | |
99 | return NULL; | |
100 | ||
a30d27ed DN |
101 | clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); |
102 | clk_mgr_base_addr = of_iomap(clkmgr_np, 0); | |
103 | BUG_ON(!clk_mgr_base_addr); | |
97259e99 ST |
104 | pll_clk->hw.reg = clk_mgr_base_addr + reg; |
105 | ||
106 | of_property_read_string(node, "clock-output-names", &clk_name); | |
107 | ||
108 | init.name = clk_name; | |
109 | init.ops = ops; | |
110 | init.flags = 0; | |
97259e99 | 111 | |
761d3e32 | 112 | init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); |
b89cd950 | 113 | init.parent_names = parent_name; |
97259e99 ST |
114 | pll_clk->hw.hw.init = &init; |
115 | ||
116 | pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; | |
117 | clk_pll_ops.enable = clk_gate_ops.enable; | |
118 | clk_pll_ops.disable = clk_gate_ops.disable; | |
119 | ||
120 | clk = clk_register(NULL, &pll_clk->hw.hw); | |
121 | if (WARN_ON(IS_ERR(clk))) { | |
122 | kfree(pll_clk); | |
123 | return NULL; | |
124 | } | |
125 | rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
126 | return clk; | |
127 | } | |
128 | ||
129 | void __init socfpga_pll_init(struct device_node *node) | |
130 | { | |
131 | __socfpga_pll_init(node, &clk_pll_ops); | |
132 | } |