Commit | Line | Data |
---|---|---|
5df33a62 VK |
1 | /* |
2 | * SPEAr3xx machines clock framework source file | |
3 | * | |
4 | * Copyright (C) 2012 ST Microelectronics | |
da89947b | 5 | * Viresh Kumar <vireshk@kernel.org> |
5df33a62 VK |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/clkdev.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/of_platform.h> | |
17 | #include <linux/spinlock_types.h> | |
5df33a62 VK |
18 | #include "clk.h" |
19 | ||
20 | static DEFINE_SPINLOCK(_lock); | |
21 | ||
d9909ebe AB |
22 | #define PLL1_CTR (misc_base + 0x008) |
23 | #define PLL1_FRQ (misc_base + 0x00C) | |
24 | #define PLL2_CTR (misc_base + 0x014) | |
25 | #define PLL2_FRQ (misc_base + 0x018) | |
26 | #define PLL_CLK_CFG (misc_base + 0x020) | |
5df33a62 VK |
27 | /* PLL_CLK_CFG register masks */ |
28 | #define MCTR_CLK_SHIFT 28 | |
29 | #define MCTR_CLK_MASK 3 | |
30 | ||
d9909ebe | 31 | #define CORE_CLK_CFG (misc_base + 0x024) |
5df33a62 VK |
32 | /* CORE CLK CFG register masks */ |
33 | #define GEN_SYNTH2_3_CLK_SHIFT 18 | |
34 | #define GEN_SYNTH2_3_CLK_MASK 1 | |
35 | ||
36 | #define HCLK_RATIO_SHIFT 10 | |
37 | #define HCLK_RATIO_MASK 2 | |
38 | #define PCLK_RATIO_SHIFT 8 | |
39 | #define PCLK_RATIO_MASK 2 | |
40 | ||
d9909ebe | 41 | #define PERIP_CLK_CFG (misc_base + 0x028) |
5df33a62 VK |
42 | /* PERIP_CLK_CFG register masks */ |
43 | #define UART_CLK_SHIFT 4 | |
44 | #define UART_CLK_MASK 1 | |
45 | #define FIRDA_CLK_SHIFT 5 | |
46 | #define FIRDA_CLK_MASK 2 | |
47 | #define GPT0_CLK_SHIFT 8 | |
48 | #define GPT1_CLK_SHIFT 11 | |
49 | #define GPT2_CLK_SHIFT 12 | |
50 | #define GPT_CLK_MASK 1 | |
51 | ||
d9909ebe | 52 | #define PERIP1_CLK_ENB (misc_base + 0x02C) |
5df33a62 VK |
53 | /* PERIP1_CLK_ENB register masks */ |
54 | #define UART_CLK_ENB 3 | |
55 | #define SSP_CLK_ENB 5 | |
56 | #define I2C_CLK_ENB 7 | |
57 | #define JPEG_CLK_ENB 8 | |
58 | #define FIRDA_CLK_ENB 10 | |
59 | #define GPT1_CLK_ENB 11 | |
60 | #define GPT2_CLK_ENB 12 | |
61 | #define ADC_CLK_ENB 15 | |
62 | #define RTC_CLK_ENB 17 | |
63 | #define GPIO_CLK_ENB 18 | |
64 | #define DMA_CLK_ENB 19 | |
65 | #define SMI_CLK_ENB 21 | |
66 | #define GMAC_CLK_ENB 23 | |
67 | #define USBD_CLK_ENB 24 | |
68 | #define USBH_CLK_ENB 25 | |
69 | #define C3_CLK_ENB 31 | |
70 | ||
d9909ebe | 71 | #define RAS_CLK_ENB (misc_base + 0x034) |
5df33a62 VK |
72 | #define RAS_AHB_CLK_ENB 0 |
73 | #define RAS_PLL1_CLK_ENB 1 | |
74 | #define RAS_APB_CLK_ENB 2 | |
75 | #define RAS_32K_CLK_ENB 3 | |
76 | #define RAS_24M_CLK_ENB 4 | |
77 | #define RAS_48M_CLK_ENB 5 | |
78 | #define RAS_PLL2_CLK_ENB 7 | |
79 | #define RAS_SYNT0_CLK_ENB 8 | |
80 | #define RAS_SYNT1_CLK_ENB 9 | |
81 | #define RAS_SYNT2_CLK_ENB 10 | |
82 | #define RAS_SYNT3_CLK_ENB 11 | |
83 | ||
d9909ebe AB |
84 | #define PRSC0_CLK_CFG (misc_base + 0x044) |
85 | #define PRSC1_CLK_CFG (misc_base + 0x048) | |
86 | #define PRSC2_CLK_CFG (misc_base + 0x04C) | |
87 | #define AMEM_CLK_CFG (misc_base + 0x050) | |
5df33a62 VK |
88 | #define AMEM_CLK_ENB 0 |
89 | ||
d9909ebe AB |
90 | #define CLCD_CLK_SYNT (misc_base + 0x05C) |
91 | #define FIRDA_CLK_SYNT (misc_base + 0x060) | |
92 | #define UART_CLK_SYNT (misc_base + 0x064) | |
93 | #define GMAC_CLK_SYNT (misc_base + 0x068) | |
94 | #define GEN0_CLK_SYNT (misc_base + 0x06C) | |
95 | #define GEN1_CLK_SYNT (misc_base + 0x070) | |
96 | #define GEN2_CLK_SYNT (misc_base + 0x074) | |
97 | #define GEN3_CLK_SYNT (misc_base + 0x078) | |
5df33a62 VK |
98 | |
99 | /* pll rate configuration table, in ascending order of rates */ | |
100 | static struct pll_rate_tbl pll_rtbl[] = { | |
101 | {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */ | |
102 | {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */ | |
103 | {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */ | |
104 | }; | |
105 | ||
106 | /* aux rate configuration table, in ascending order of rates */ | |
107 | static struct aux_rate_tbl aux_rtbl[] = { | |
108 | /* For PLL1 = 332 MHz */ | |
ef0fd0a2 DS |
109 | {.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */ |
110 | {.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */ | |
111 | {.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */ | |
112 | {.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */ | |
113 | {.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */ | |
114 | {.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */ | |
5df33a62 VK |
115 | {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */ |
116 | {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ | |
117 | {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ | |
118 | {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ | |
119 | }; | |
120 | ||
121 | /* gpt rate configuration table, in ascending order of rates */ | |
122 | static struct gpt_rate_tbl gpt_rtbl[] = { | |
123 | /* For pll1 = 332 MHz */ | |
124 | {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ | |
125 | {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ | |
126 | {.mscale = 1, .nscale = 0}, /* 83 MHz */ | |
127 | }; | |
128 | ||
129 | /* clock parents */ | |
5cfc545f VKS |
130 | static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", }; |
131 | static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", | |
5df33a62 | 132 | }; |
5cfc545f VKS |
133 | static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", }; |
134 | static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", }; | |
135 | static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", }; | |
5df33a62 VK |
136 | static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", }; |
137 | static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", | |
138 | "pll2_clk", }; | |
139 | ||
140 | #ifdef CONFIG_MACH_SPEAR300 | |
141 | static void __init spear300_clk_init(void) | |
142 | { | |
143 | struct clk *clk; | |
144 | ||
5cfc545f | 145 | clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, |
5df33a62 VK |
146 | 1, 1); |
147 | clk_register_clkdev(clk, NULL, "60000000.clcd"); | |
148 | ||
149 | clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, | |
150 | 1); | |
151 | clk_register_clkdev(clk, NULL, "94000000.flash"); | |
152 | ||
153 | clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, | |
154 | 1); | |
155 | clk_register_clkdev(clk, NULL, "70000000.sdhci"); | |
156 | ||
157 | clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, | |
158 | 1); | |
159 | clk_register_clkdev(clk, NULL, "a9000000.gpio"); | |
160 | ||
161 | clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, | |
162 | 1); | |
163 | clk_register_clkdev(clk, NULL, "a0000000.kbd"); | |
164 | } | |
90d4971d AL |
165 | #else |
166 | static inline void spear300_clk_init(void) { } | |
5df33a62 VK |
167 | #endif |
168 | ||
169 | /* array of all spear 310 clock lookups */ | |
170 | #ifdef CONFIG_MACH_SPEAR310 | |
171 | static void __init spear310_clk_init(void) | |
172 | { | |
173 | struct clk *clk; | |
174 | ||
175 | clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, | |
176 | 1); | |
177 | clk_register_clkdev(clk, "emi", NULL); | |
178 | ||
179 | clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, | |
180 | 1); | |
181 | clk_register_clkdev(clk, NULL, "44000000.flash"); | |
182 | ||
183 | clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1, | |
184 | 1); | |
185 | clk_register_clkdev(clk, NULL, "tdm"); | |
186 | ||
187 | clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1, | |
188 | 1); | |
189 | clk_register_clkdev(clk, NULL, "b2000000.serial"); | |
190 | ||
191 | clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1, | |
192 | 1); | |
193 | clk_register_clkdev(clk, NULL, "b2080000.serial"); | |
194 | ||
195 | clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1, | |
196 | 1); | |
197 | clk_register_clkdev(clk, NULL, "b2100000.serial"); | |
198 | ||
199 | clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1, | |
200 | 1); | |
201 | clk_register_clkdev(clk, NULL, "b2180000.serial"); | |
202 | ||
203 | clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1, | |
204 | 1); | |
205 | clk_register_clkdev(clk, NULL, "b2200000.serial"); | |
206 | } | |
90d4971d AL |
207 | #else |
208 | static inline void spear310_clk_init(void) { } | |
5df33a62 VK |
209 | #endif |
210 | ||
211 | /* array of all spear 320 clock lookups */ | |
212 | #ifdef CONFIG_MACH_SPEAR320 | |
d9909ebe | 213 | |
15ebb052 | 214 | #define SPEAR320_CONTROL_REG (soc_config_base + 0x0010) |
d9909ebe AB |
215 | #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) |
216 | ||
217 | #define SPEAR320_UARTX_PCLK_MASK 0x1 | |
218 | #define SPEAR320_UART2_PCLK_SHIFT 8 | |
219 | #define SPEAR320_UART3_PCLK_SHIFT 9 | |
220 | #define SPEAR320_UART4_PCLK_SHIFT 10 | |
221 | #define SPEAR320_UART5_PCLK_SHIFT 11 | |
222 | #define SPEAR320_UART6_PCLK_SHIFT 12 | |
223 | #define SPEAR320_RS485_PCLK_SHIFT 13 | |
5df33a62 VK |
224 | #define SMII_PCLK_SHIFT 18 |
225 | #define SMII_PCLK_MASK 2 | |
226 | #define SMII_PCLK_VAL_PAD 0x0 | |
227 | #define SMII_PCLK_VAL_PLL2 0x1 | |
228 | #define SMII_PCLK_VAL_SYNTH0 0x2 | |
229 | #define SDHCI_PCLK_SHIFT 15 | |
230 | #define SDHCI_PCLK_MASK 1 | |
231 | #define SDHCI_PCLK_VAL_48M 0x0 | |
232 | #define SDHCI_PCLK_VAL_SYNTH3 0x1 | |
233 | #define I2S_REF_PCLK_SHIFT 8 | |
234 | #define I2S_REF_PCLK_MASK 1 | |
235 | #define I2S_REF_PCLK_SYNTH_VAL 0x1 | |
236 | #define I2S_REF_PCLK_PLL2_VAL 0x0 | |
237 | #define UART1_PCLK_SHIFT 6 | |
238 | #define UART1_PCLK_MASK 1 | |
239 | #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0 | |
240 | #define SPEAR320_UARTX_PCLK_VAL_APB 0x1 | |
241 | ||
5cfc545f VKS |
242 | static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", }; |
243 | static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", }; | |
5df33a62 | 244 | static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", |
5cfc545f VKS |
245 | "ras_syn0_gclk", }; |
246 | static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; | |
5df33a62 | 247 | |
44943777 TG |
248 | static void __init spear320_clk_init(void __iomem *soc_config_base, |
249 | struct clk *ras_apb_clk) | |
5df33a62 VK |
250 | { |
251 | struct clk *clk; | |
252 | ||
253 | clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, | |
254 | CLK_IS_ROOT, 125000000); | |
255 | clk_register_clkdev(clk, "smii_125m_pad", NULL); | |
256 | ||
5cfc545f | 257 | clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, |
5df33a62 VK |
258 | 1, 1); |
259 | clk_register_clkdev(clk, NULL, "90000000.clcd"); | |
260 | ||
261 | clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, | |
262 | 1); | |
263 | clk_register_clkdev(clk, "emi", NULL); | |
264 | ||
265 | clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, | |
266 | 1); | |
267 | clk_register_clkdev(clk, NULL, "4c000000.flash"); | |
268 | ||
269 | clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1, | |
270 | 1); | |
271 | clk_register_clkdev(clk, NULL, "a7000000.i2c"); | |
272 | ||
273 | clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1, | |
274 | 1); | |
df2449ab | 275 | clk_register_clkdev(clk, NULL, "a8000000.pwm"); |
5df33a62 VK |
276 | |
277 | clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1, | |
278 | 1); | |
279 | clk_register_clkdev(clk, NULL, "a5000000.spi"); | |
280 | ||
281 | clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1, | |
282 | 1); | |
283 | clk_register_clkdev(clk, NULL, "a6000000.spi"); | |
284 | ||
285 | clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1, | |
286 | 1); | |
287 | clk_register_clkdev(clk, NULL, "c_can_platform.0"); | |
288 | ||
289 | clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1, | |
290 | 1); | |
291 | clk_register_clkdev(clk, NULL, "c_can_platform.1"); | |
292 | ||
293 | clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1, | |
294 | 1); | |
df2449ab | 295 | clk_register_clkdev(clk, NULL, "a9400000.i2s"); |
5df33a62 VK |
296 | |
297 | clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, | |
819c1de3 JH |
298 | ARRAY_SIZE(i2s_ref_parents), |
299 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
300 | SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT, |
301 | I2S_REF_PCLK_MASK, 0, &_lock); | |
5df33a62 VK |
302 | clk_register_clkdev(clk, "i2s_ref_clk", NULL); |
303 | ||
12499792 VKS |
304 | clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", |
305 | CLK_SET_RATE_PARENT, 1, | |
5df33a62 VK |
306 | 4); |
307 | clk_register_clkdev(clk, "i2s_sclk", NULL); | |
308 | ||
cd4b519a VKS |
309 | clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1, |
310 | 1); | |
311 | clk_register_clkdev(clk, "hclk", "aa000000.eth"); | |
312 | ||
313 | clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1, | |
314 | 1); | |
315 | clk_register_clkdev(clk, "hclk", "ab000000.eth"); | |
316 | ||
5df33a62 | 317 | clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, |
819c1de3 JH |
318 | ARRAY_SIZE(uartx_parents), |
319 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
320 | SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT, |
321 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); | |
5df33a62 VK |
322 | clk_register_clkdev(clk, NULL, "a9300000.serial"); |
323 | ||
324 | clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, | |
819c1de3 JH |
325 | ARRAY_SIZE(sdhci_parents), |
326 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
327 | SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, |
328 | 0, &_lock); | |
5df33a62 VK |
329 | clk_register_clkdev(clk, NULL, "70000000.sdhci"); |
330 | ||
331 | clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, | |
819c1de3 JH |
332 | ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT, |
333 | SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK, | |
334 | 0, &_lock); | |
5df33a62 VK |
335 | clk_register_clkdev(clk, NULL, "smii_pclk"); |
336 | ||
337 | clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1); | |
338 | clk_register_clkdev(clk, NULL, "smii"); | |
339 | ||
340 | clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, | |
819c1de3 JH |
341 | ARRAY_SIZE(uartx_parents), |
342 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
343 | SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK, |
344 | 0, &_lock); | |
5df33a62 | 345 | clk_register_clkdev(clk, NULL, "a3000000.serial"); |
44943777 TG |
346 | /* Enforce ras_apb_clk */ |
347 | clk_set_parent(clk, ras_apb_clk); | |
5df33a62 VK |
348 | |
349 | clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, | |
819c1de3 JH |
350 | ARRAY_SIZE(uartx_parents), |
351 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
352 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT, |
353 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); | |
5df33a62 | 354 | clk_register_clkdev(clk, NULL, "a4000000.serial"); |
44943777 TG |
355 | /* Enforce ras_apb_clk */ |
356 | clk_set_parent(clk, ras_apb_clk); | |
5df33a62 VK |
357 | |
358 | clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, | |
819c1de3 JH |
359 | ARRAY_SIZE(uartx_parents), |
360 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
361 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT, |
362 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); | |
5df33a62 VK |
363 | clk_register_clkdev(clk, NULL, "a9100000.serial"); |
364 | ||
365 | clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, | |
819c1de3 JH |
366 | ARRAY_SIZE(uartx_parents), |
367 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
368 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT, |
369 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); | |
5df33a62 VK |
370 | clk_register_clkdev(clk, NULL, "a9200000.serial"); |
371 | ||
372 | clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, | |
819c1de3 JH |
373 | ARRAY_SIZE(uartx_parents), |
374 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
375 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT, |
376 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); | |
5df33a62 VK |
377 | clk_register_clkdev(clk, NULL, "60000000.serial"); |
378 | ||
379 | clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, | |
819c1de3 JH |
380 | ARRAY_SIZE(uartx_parents), |
381 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
382 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT, |
383 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); | |
5df33a62 VK |
384 | clk_register_clkdev(clk, NULL, "60100000.serial"); |
385 | } | |
90d4971d | 386 | #else |
44943777 | 387 | static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } |
5df33a62 VK |
388 | #endif |
389 | ||
d9909ebe | 390 | void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) |
5df33a62 | 391 | { |
44943777 | 392 | struct clk *clk, *clk1, *ras_apb_clk; |
5df33a62 | 393 | |
5df33a62 VK |
394 | clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, |
395 | 32000); | |
396 | clk_register_clkdev(clk, "osc_32k_clk", NULL); | |
397 | ||
398 | clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, | |
399 | 24000000); | |
400 | clk_register_clkdev(clk, "osc_24m_clk", NULL); | |
401 | ||
402 | /* clock derived from 32 KHz osc clk */ | |
403 | clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, | |
404 | PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); | |
405 | clk_register_clkdev(clk, NULL, "fc900000.rtc"); | |
406 | ||
407 | /* clock derived from 24 MHz osc clk */ | |
5cfc545f | 408 | clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, |
5df33a62 | 409 | 48000000); |
5cfc545f | 410 | clk_register_clkdev(clk, "pll3_clk", NULL); |
5df33a62 VK |
411 | |
412 | clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, | |
413 | 1); | |
414 | clk_register_clkdev(clk, NULL, "fc880000.wdt"); | |
415 | ||
416 | clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, | |
417 | "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, | |
418 | ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); | |
419 | clk_register_clkdev(clk, "vco1_clk", NULL); | |
420 | clk_register_clkdev(clk1, "pll1_clk", NULL); | |
421 | ||
422 | clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, | |
423 | "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, | |
424 | ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); | |
425 | clk_register_clkdev(clk, "vco2_clk", NULL); | |
426 | clk_register_clkdev(clk1, "pll2_clk", NULL); | |
427 | ||
428 | /* clock derived from pll1 clk */ | |
12499792 VKS |
429 | clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", |
430 | CLK_SET_RATE_PARENT, 1, 1); | |
5df33a62 VK |
431 | clk_register_clkdev(clk, "cpu_clk", NULL); |
432 | ||
433 | clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", | |
434 | CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, | |
435 | HCLK_RATIO_MASK, 0, &_lock); | |
436 | clk_register_clkdev(clk, "ahb_clk", NULL); | |
437 | ||
5cfc545f VKS |
438 | clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, |
439 | UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), | |
440 | &_lock, &clk1); | |
441 | clk_register_clkdev(clk, "uart_syn_clk", NULL); | |
442 | clk_register_clkdev(clk1, "uart_syn_gclk", NULL); | |
5df33a62 | 443 | |
5cfc545f | 444 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, |
819c1de3 JH |
445 | ARRAY_SIZE(uart0_parents), |
446 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
447 | PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, |
448 | &_lock); | |
5cfc545f | 449 | clk_register_clkdev(clk, "uart0_mclk", NULL); |
5df33a62 | 450 | |
12499792 VKS |
451 | clk = clk_register_gate(NULL, "uart0", "uart0_mclk", |
452 | CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0, | |
453 | &_lock); | |
5df33a62 VK |
454 | clk_register_clkdev(clk, NULL, "d0000000.serial"); |
455 | ||
5cfc545f VKS |
456 | clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, |
457 | FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), | |
458 | &_lock, &clk1); | |
459 | clk_register_clkdev(clk, "firda_syn_clk", NULL); | |
460 | clk_register_clkdev(clk1, "firda_syn_gclk", NULL); | |
5df33a62 | 461 | |
5cfc545f | 462 | clk = clk_register_mux(NULL, "firda_mclk", firda_parents, |
819c1de3 JH |
463 | ARRAY_SIZE(firda_parents), |
464 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 VKS |
465 | PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, |
466 | &_lock); | |
5cfc545f | 467 | clk_register_clkdev(clk, "firda_mclk", NULL); |
5df33a62 | 468 | |
12499792 VKS |
469 | clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", |
470 | CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, | |
471 | &_lock); | |
5df33a62 VK |
472 | clk_register_clkdev(clk, NULL, "firda"); |
473 | ||
474 | /* gpt clocks */ | |
5cfc545f VKS |
475 | clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, |
476 | ARRAY_SIZE(gpt_rtbl), &_lock); | |
5df33a62 | 477 | clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, |
819c1de3 JH |
478 | ARRAY_SIZE(gpt0_parents), |
479 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 | 480 | PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
5df33a62 VK |
481 | clk_register_clkdev(clk, NULL, "gpt0"); |
482 | ||
5cfc545f VKS |
483 | clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, |
484 | ARRAY_SIZE(gpt_rtbl), &_lock); | |
485 | clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, | |
819c1de3 JH |
486 | ARRAY_SIZE(gpt1_parents), |
487 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 | 488 | PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
5cfc545f | 489 | clk_register_clkdev(clk, "gpt1_mclk", NULL); |
12499792 VKS |
490 | clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", |
491 | CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, | |
492 | &_lock); | |
5df33a62 VK |
493 | clk_register_clkdev(clk, NULL, "gpt1"); |
494 | ||
5cfc545f VKS |
495 | clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, |
496 | ARRAY_SIZE(gpt_rtbl), &_lock); | |
497 | clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, | |
819c1de3 JH |
498 | ARRAY_SIZE(gpt2_parents), |
499 | CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, | |
12499792 | 500 | PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
5cfc545f | 501 | clk_register_clkdev(clk, "gpt2_mclk", NULL); |
12499792 VKS |
502 | clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", |
503 | CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, | |
504 | &_lock); | |
5df33a62 VK |
505 | clk_register_clkdev(clk, NULL, "gpt2"); |
506 | ||
507 | /* general synths clocks */ | |
5cfc545f VKS |
508 | clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk", |
509 | 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), | |
510 | &_lock, &clk1); | |
511 | clk_register_clkdev(clk, "gen0_syn_clk", NULL); | |
512 | clk_register_clkdev(clk1, "gen0_syn_gclk", NULL); | |
513 | ||
514 | clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk", | |
515 | 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), | |
516 | &_lock, &clk1); | |
517 | clk_register_clkdev(clk, "gen1_syn_clk", NULL); | |
518 | clk_register_clkdev(clk1, "gen1_syn_gclk", NULL); | |
519 | ||
520 | clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, | |
819c1de3 JH |
521 | ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT, |
522 | CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT, | |
523 | GEN_SYNTH2_3_CLK_MASK, 0, &_lock); | |
5cfc545f | 524 | clk_register_clkdev(clk, "gen2_3_par_clk", NULL); |
5df33a62 | 525 | |
5cfc545f VKS |
526 | clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", |
527 | "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl, | |
5df33a62 | 528 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); |
5cfc545f VKS |
529 | clk_register_clkdev(clk, "gen2_syn_clk", NULL); |
530 | clk_register_clkdev(clk1, "gen2_syn_gclk", NULL); | |
5df33a62 | 531 | |
5cfc545f VKS |
532 | clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk", |
533 | "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl, | |
5df33a62 | 534 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); |
5cfc545f VKS |
535 | clk_register_clkdev(clk, "gen3_syn_clk", NULL); |
536 | clk_register_clkdev(clk1, "gen3_syn_gclk", NULL); | |
5df33a62 VK |
537 | |
538 | /* clock derived from pll3 clk */ | |
5cfc545f VKS |
539 | clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, |
540 | USBH_CLK_ENB, 0, &_lock); | |
df2449ab RK |
541 | clk_register_clkdev(clk, NULL, "e1800000.ehci"); |
542 | clk_register_clkdev(clk, NULL, "e1900000.ohci"); | |
543 | clk_register_clkdev(clk, NULL, "e2100000.ohci"); | |
5df33a62 VK |
544 | |
545 | clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, | |
546 | 1); | |
547 | clk_register_clkdev(clk, "usbh.0_clk", NULL); | |
548 | ||
549 | clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1, | |
550 | 1); | |
551 | clk_register_clkdev(clk, "usbh.1_clk", NULL); | |
552 | ||
5cfc545f VKS |
553 | clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, |
554 | USBD_CLK_ENB, 0, &_lock); | |
df2449ab | 555 | clk_register_clkdev(clk, NULL, "e1100000.usbd"); |
5df33a62 VK |
556 | |
557 | /* clock derived from ahb clk */ | |
558 | clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, | |
559 | 1); | |
560 | clk_register_clkdev(clk, "ahbmult2_clk", NULL); | |
561 | ||
562 | clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, | |
819c1de3 JH |
563 | ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT, |
564 | PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock); | |
5df33a62 VK |
565 | clk_register_clkdev(clk, "ddr_clk", NULL); |
566 | ||
567 | clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", | |
568 | CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, | |
569 | PCLK_RATIO_MASK, 0, &_lock); | |
570 | clk_register_clkdev(clk, "apb_clk", NULL); | |
571 | ||
572 | clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG, | |
573 | AMEM_CLK_ENB, 0, &_lock); | |
574 | clk_register_clkdev(clk, "amem_clk", NULL); | |
575 | ||
576 | clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB, | |
577 | C3_CLK_ENB, 0, &_lock); | |
578 | clk_register_clkdev(clk, NULL, "c3_clk"); | |
579 | ||
580 | clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, | |
581 | DMA_CLK_ENB, 0, &_lock); | |
582 | clk_register_clkdev(clk, NULL, "fc400000.dma"); | |
583 | ||
584 | clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, | |
585 | GMAC_CLK_ENB, 0, &_lock); | |
586 | clk_register_clkdev(clk, NULL, "e0800000.eth"); | |
587 | ||
588 | clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB, | |
589 | I2C_CLK_ENB, 0, &_lock); | |
590 | clk_register_clkdev(clk, NULL, "d0180000.i2c"); | |
591 | ||
592 | clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, | |
593 | JPEG_CLK_ENB, 0, &_lock); | |
594 | clk_register_clkdev(clk, NULL, "jpeg"); | |
595 | ||
596 | clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, | |
597 | SMI_CLK_ENB, 0, &_lock); | |
598 | clk_register_clkdev(clk, NULL, "fc000000.flash"); | |
599 | ||
600 | /* clock derived from apb clk */ | |
601 | clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, | |
602 | ADC_CLK_ENB, 0, &_lock); | |
df2449ab | 603 | clk_register_clkdev(clk, NULL, "d0080000.adc"); |
5df33a62 VK |
604 | |
605 | clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB, | |
606 | GPIO_CLK_ENB, 0, &_lock); | |
607 | clk_register_clkdev(clk, NULL, "fc980000.gpio"); | |
608 | ||
609 | clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, | |
610 | SSP_CLK_ENB, 0, &_lock); | |
611 | clk_register_clkdev(clk, NULL, "d0100000.spi"); | |
612 | ||
613 | /* RAS clk enable */ | |
614 | clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB, | |
615 | RAS_AHB_CLK_ENB, 0, &_lock); | |
616 | clk_register_clkdev(clk, "ras_ahb_clk", NULL); | |
617 | ||
618 | clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, | |
619 | RAS_APB_CLK_ENB, 0, &_lock); | |
620 | clk_register_clkdev(clk, "ras_apb_clk", NULL); | |
44943777 | 621 | ras_apb_clk = clk; |
5df33a62 VK |
622 | |
623 | clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, | |
624 | RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock); | |
625 | clk_register_clkdev(clk, "ras_32k_clk", NULL); | |
626 | ||
627 | clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0, | |
628 | RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock); | |
629 | clk_register_clkdev(clk, "ras_24m_clk", NULL); | |
630 | ||
631 | clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0, | |
632 | RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock); | |
633 | clk_register_clkdev(clk, "ras_pll1_clk", NULL); | |
634 | ||
635 | clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, | |
636 | RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); | |
637 | clk_register_clkdev(clk, "ras_pll2_clk", NULL); | |
638 | ||
5cfc545f | 639 | clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, |
5df33a62 | 640 | RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); |
5cfc545f VKS |
641 | clk_register_clkdev(clk, "ras_pll3_clk", NULL); |
642 | ||
12499792 VKS |
643 | clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", |
644 | CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, | |
645 | &_lock); | |
5cfc545f VKS |
646 | clk_register_clkdev(clk, "ras_syn0_gclk", NULL); |
647 | ||
12499792 VKS |
648 | clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", |
649 | CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, | |
650 | &_lock); | |
5cfc545f VKS |
651 | clk_register_clkdev(clk, "ras_syn1_gclk", NULL); |
652 | ||
12499792 VKS |
653 | clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", |
654 | CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, | |
655 | &_lock); | |
5cfc545f VKS |
656 | clk_register_clkdev(clk, "ras_syn2_gclk", NULL); |
657 | ||
12499792 VKS |
658 | clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", |
659 | CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, | |
660 | &_lock); | |
5cfc545f | 661 | clk_register_clkdev(clk, "ras_syn3_gclk", NULL); |
5df33a62 VK |
662 | |
663 | if (of_machine_is_compatible("st,spear300")) | |
664 | spear300_clk_init(); | |
665 | else if (of_machine_is_compatible("st,spear310")) | |
666 | spear310_clk_init(); | |
667 | else if (of_machine_is_compatible("st,spear320")) | |
44943777 | 668 | spear320_clk_init(soc_config_base, ras_apb_clk); |
5df33a62 | 669 | } |