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1d80c142 MR |
1 | #ifndef _CCU_MULT_H_ |
2 | #define _CCU_MULT_H_ | |
3 | ||
aa152335 MR |
4 | #include "ccu_common.h" |
5 | #include "ccu_mux.h" | |
6 | ||
1d80c142 MR |
7 | struct _ccu_mult { |
8 | u8 shift; | |
9 | u8 width; | |
10 | }; | |
11 | ||
12 | #define _SUNXI_CCU_MULT(_shift, _width) \ | |
13 | { \ | |
14 | .shift = _shift, \ | |
15 | .width = _width, \ | |
16 | } | |
17 | ||
aa152335 MR |
18 | struct ccu_mult { |
19 | u32 enable; | |
20 | ||
21 | struct _ccu_mult mult; | |
22 | struct ccu_mux_internal mux; | |
23 | struct ccu_common common; | |
24 | }; | |
25 | ||
26 | #define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ | |
27 | _mshift, _mwidth, _gate, _lock, \ | |
28 | _flags) \ | |
29 | struct ccu_mult _struct = { \ | |
30 | .enable = _gate, \ | |
31 | .mult = _SUNXI_CCU_MULT(_mshift, _mwidth), \ | |
32 | .common = { \ | |
33 | .reg = _reg, \ | |
34 | .hw.init = CLK_HW_INIT(_name, \ | |
35 | _parent, \ | |
36 | &ccu_mult_ops, \ | |
37 | _flags), \ | |
38 | }, \ | |
39 | } | |
40 | ||
41 | static inline struct ccu_mult *hw_to_ccu_mult(struct clk_hw *hw) | |
42 | { | |
43 | struct ccu_common *common = hw_to_ccu_common(hw); | |
44 | ||
45 | return container_of(common, struct ccu_mult, common); | |
46 | } | |
47 | ||
48 | extern const struct clk_ops ccu_mult_ops; | |
49 | ||
1d80c142 | 50 | #endif /* _CCU_MULT_H_ */ |