Commit | Line | Data |
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c1d1939c | 1 | /* |
8f8f484b PG |
2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #ifndef __TEGRA_CLK_H | |
18 | #define __TEGRA_CLK_H | |
19 | ||
20 | #include <linux/clk-provider.h> | |
21 | #include <linux/clkdev.h> | |
22 | ||
23 | /** | |
24 | * struct tegra_clk_sync_source - external clock source from codec | |
25 | * | |
26 | * @hw: handle between common and hardware-specific interfaces | |
27 | * @rate: input frequency from source | |
28 | * @max_rate: max rate allowed | |
29 | */ | |
30 | struct tegra_clk_sync_source { | |
31 | struct clk_hw hw; | |
32 | unsigned long rate; | |
33 | unsigned long max_rate; | |
34 | }; | |
35 | ||
36 | #define to_clk_sync_source(_hw) \ | |
37 | container_of(_hw, struct tegra_clk_sync_source, hw) | |
38 | ||
39 | extern const struct clk_ops tegra_clk_sync_source_ops; | |
40 | struct clk *tegra_clk_register_sync_source(const char *name, | |
41 | unsigned long fixed_rate, unsigned long max_rate); | |
42 | ||
43 | /** | |
44 | * struct tegra_clk_frac_div - fractional divider clock | |
45 | * | |
46 | * @hw: handle between common and hardware-specific interfaces | |
47 | * @reg: register containing divider | |
48 | * @flags: hardware-specific flags | |
49 | * @shift: shift to the divider bit field | |
50 | * @width: width of the divider bit field | |
51 | * @frac_width: width of the fractional bit field | |
52 | * @lock: register lock | |
53 | * | |
54 | * Flags: | |
55 | * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. | |
56 | * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this | |
57 | * flag indicates that this divider is for fixed rate PLL. | |
58 | * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when | |
59 | * fraction bit is set. This flags indicates to calculate divider for which | |
60 | * fracton bit will be zero. | |
61 | * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is | |
62 | * set when divider value is not 0. This flags indicates that the divider | |
63 | * is for UART module. | |
64 | */ | |
65 | struct tegra_clk_frac_div { | |
66 | struct clk_hw hw; | |
67 | void __iomem *reg; | |
68 | u8 flags; | |
69 | u8 shift; | |
70 | u8 width; | |
71 | u8 frac_width; | |
72 | spinlock_t *lock; | |
73 | }; | |
74 | ||
75 | #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) | |
76 | ||
77 | #define TEGRA_DIVIDER_ROUND_UP BIT(0) | |
78 | #define TEGRA_DIVIDER_FIXED BIT(1) | |
79 | #define TEGRA_DIVIDER_INT BIT(2) | |
80 | #define TEGRA_DIVIDER_UART BIT(3) | |
81 | ||
82 | extern const struct clk_ops tegra_clk_frac_div_ops; | |
83 | struct clk *tegra_clk_register_divider(const char *name, | |
84 | const char *parent_name, void __iomem *reg, | |
85 | unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, | |
86 | u8 frac_width, spinlock_t *lock); | |
87 | ||
88 | /* | |
89 | * Tegra PLL: | |
90 | * | |
91 | * In general, there are 3 requirements for each PLL | |
92 | * that SW needs to be comply with. | |
93 | * (1) Input frequency range (REF). | |
94 | * (2) Comparison frequency range (CF). CF = REF/DIVM. | |
95 | * (3) VCO frequency range (VCO). VCO = CF * DIVN. | |
96 | * | |
97 | * The final PLL output frequency (FO) = VCO >> DIVP. | |
98 | */ | |
99 | ||
100 | /** | |
101 | * struct tegra_clk_pll_freq_table - PLL frequecy table | |
102 | * | |
103 | * @input_rate: input rate from source | |
104 | * @output_rate: output rate from PLL for the input rate | |
105 | * @n: feedback divider | |
106 | * @m: input divider | |
107 | * @p: post divider | |
108 | * @cpcon: charge pump current | |
109 | */ | |
110 | struct tegra_clk_pll_freq_table { | |
111 | unsigned long input_rate; | |
112 | unsigned long output_rate; | |
113 | u16 n; | |
114 | u16 m; | |
115 | u8 p; | |
116 | u8 cpcon; | |
117 | }; | |
118 | ||
0b6525ac PDS |
119 | /** |
120 | * struct pdiv_map - map post divider to hw value | |
121 | * | |
122 | * @pdiv: post divider | |
123 | * @hw_val: value to be written to the PLL hw | |
124 | */ | |
125 | struct pdiv_map { | |
126 | u8 pdiv; | |
127 | u8 hw_val; | |
128 | }; | |
129 | ||
aa6fefde PDS |
130 | /** |
131 | * struct div_nmp - offset and width of m,n and p fields | |
132 | * | |
133 | * @divn_shift: shift to the feedback divider bit field | |
134 | * @divn_width: width of the feedback divider bit field | |
135 | * @divm_shift: shift to the input divider bit field | |
136 | * @divm_width: width of the input divider bit field | |
137 | * @divp_shift: shift to the post divider bit field | |
138 | * @divp_width: width of the post divider bit field | |
7b781c72 PDS |
139 | * @override_divn_shift: shift to the feedback divider bitfield in override reg |
140 | * @override_divm_shift: shift to the input divider bitfield in override reg | |
141 | * @override_divp_shift: shift to the post divider bitfield in override reg | |
aa6fefde PDS |
142 | */ |
143 | struct div_nmp { | |
144 | u8 divn_shift; | |
145 | u8 divn_width; | |
146 | u8 divm_shift; | |
147 | u8 divm_width; | |
148 | u8 divp_shift; | |
149 | u8 divp_width; | |
7b781c72 PDS |
150 | u8 override_divn_shift; |
151 | u8 override_divm_shift; | |
152 | u8 override_divp_shift; | |
aa6fefde PDS |
153 | }; |
154 | ||
8f8f484b PG |
155 | /** |
156 | * struct clk_pll_params - PLL parameters | |
157 | * | |
158 | * @input_min: Minimum input frequency | |
159 | * @input_max: Maximum input frequency | |
160 | * @cf_min: Minimum comparison frequency | |
161 | * @cf_max: Maximum comparison frequency | |
162 | * @vco_min: Minimum VCO frequency | |
163 | * @vco_max: Maximum VCO frequency | |
164 | * @base_reg: PLL base reg offset | |
165 | * @misc_reg: PLL misc reg offset | |
166 | * @lock_reg: PLL lock reg offset | |
167 | * @lock_bit_idx: Bit index for PLL lock status | |
168 | * @lock_enable_bit_idx: Bit index to enable PLL lock | |
169 | * @lock_delay: Delay in us if PLL lock is not used | |
170 | */ | |
171 | struct tegra_clk_pll_params { | |
172 | unsigned long input_min; | |
173 | unsigned long input_max; | |
174 | unsigned long cf_min; | |
175 | unsigned long cf_max; | |
176 | unsigned long vco_min; | |
177 | unsigned long vco_max; | |
178 | ||
179 | u32 base_reg; | |
180 | u32 misc_reg; | |
181 | u32 lock_reg; | |
3e72771e | 182 | u32 lock_mask; |
8f8f484b | 183 | u32 lock_enable_bit_idx; |
c1d1939c PDS |
184 | u32 iddq_reg; |
185 | u32 iddq_bit_idx; | |
186 | u32 aux_reg; | |
187 | u32 dyn_ramp_reg; | |
188 | u32 ext_misc_reg[3]; | |
7b781c72 PDS |
189 | u32 pmc_divnm_reg; |
190 | u32 pmc_divp_reg; | |
c1d1939c PDS |
191 | int stepa_shift; |
192 | int stepb_shift; | |
8f8f484b | 193 | int lock_delay; |
0b6525ac PDS |
194 | int max_p; |
195 | struct pdiv_map *pdiv_tohw; | |
aa6fefde | 196 | struct div_nmp *div_nmp; |
8f8f484b PG |
197 | }; |
198 | ||
199 | /** | |
200 | * struct tegra_clk_pll - Tegra PLL clock | |
201 | * | |
202 | * @hw: handle between common and hardware-specifix interfaces | |
203 | * @clk_base: address of CAR controller | |
204 | * @pmc: address of PMC, required to read override bits | |
205 | * @freq_table: array of frequencies supported by PLL | |
206 | * @params: PLL parameters | |
207 | * @flags: PLL flags | |
208 | * @fixed_rate: PLL rate if it is fixed | |
209 | * @lock: register lock | |
8f8f484b PG |
210 | * |
211 | * Flags: | |
212 | * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for | |
213 | * PLL locking. If not set it will use lock_delay value to wait. | |
214 | * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs | |
215 | * to be programmed to change output frequency of the PLL. | |
216 | * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs | |
217 | * to be programmed to change output frequency of the PLL. | |
218 | * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs | |
219 | * to be programmed to change output frequency of the PLL. | |
220 | * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated | |
221 | * that it is PLLU and invert post divider value. | |
222 | * TEGRA_PLLM - PLLM has additional override settings in PMC. This | |
223 | * flag indicates that it is PLLM and use override settings. | |
224 | * TEGRA_PLL_FIXED - We are not supposed to change output frequency | |
225 | * of some plls. | |
226 | * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. | |
dba4072a PDS |
227 | * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the |
228 | * base register. | |
dd93587b | 229 | * TEGRA_PLL_BYPASS - PLL has bypass bit |
7ba28813 | 230 | * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring |
8f8f484b PG |
231 | */ |
232 | struct tegra_clk_pll { | |
233 | struct clk_hw hw; | |
234 | void __iomem *clk_base; | |
235 | void __iomem *pmc; | |
dba4072a | 236 | u32 flags; |
8f8f484b PG |
237 | unsigned long fixed_rate; |
238 | spinlock_t *lock; | |
8f8f484b PG |
239 | struct tegra_clk_pll_freq_table *freq_table; |
240 | struct tegra_clk_pll_params *params; | |
241 | }; | |
242 | ||
243 | #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) | |
244 | ||
245 | #define TEGRA_PLL_USE_LOCK BIT(0) | |
246 | #define TEGRA_PLL_HAS_CPCON BIT(1) | |
247 | #define TEGRA_PLL_SET_LFCON BIT(2) | |
248 | #define TEGRA_PLL_SET_DCCON BIT(3) | |
249 | #define TEGRA_PLLU BIT(4) | |
250 | #define TEGRA_PLLM BIT(5) | |
251 | #define TEGRA_PLL_FIXED BIT(6) | |
252 | #define TEGRA_PLLE_CONFIGURE BIT(7) | |
dba4072a | 253 | #define TEGRA_PLL_LOCK_MISC BIT(8) |
dd93587b | 254 | #define TEGRA_PLL_BYPASS BIT(9) |
7ba28813 | 255 | #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) |
8f8f484b PG |
256 | |
257 | extern const struct clk_ops tegra_clk_pll_ops; | |
258 | extern const struct clk_ops tegra_clk_plle_ops; | |
259 | struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, | |
260 | void __iomem *clk_base, void __iomem *pmc, | |
261 | unsigned long flags, unsigned long fixed_rate, | |
dba4072a | 262 | struct tegra_clk_pll_params *pll_params, u32 pll_flags, |
8f8f484b | 263 | struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); |
c1d1939c | 264 | |
8f8f484b PG |
265 | struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, |
266 | void __iomem *clk_base, void __iomem *pmc, | |
267 | unsigned long flags, unsigned long fixed_rate, | |
dba4072a | 268 | struct tegra_clk_pll_params *pll_params, u32 pll_flags, |
8f8f484b PG |
269 | struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); |
270 | ||
c1d1939c PDS |
271 | struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, |
272 | void __iomem *clk_base, void __iomem *pmc, | |
273 | unsigned long flags, unsigned long fixed_rate, | |
274 | struct tegra_clk_pll_params *pll_params, | |
275 | u32 pll_flags, | |
276 | struct tegra_clk_pll_freq_table *freq_table, | |
277 | spinlock_t *lock); | |
278 | ||
279 | struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, | |
280 | void __iomem *clk_base, void __iomem *pmc, | |
281 | unsigned long flags, unsigned long fixed_rate, | |
282 | struct tegra_clk_pll_params *pll_params, | |
283 | u32 pll_flags, | |
284 | struct tegra_clk_pll_freq_table *freq_table, | |
285 | spinlock_t *lock); | |
286 | ||
287 | struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, | |
288 | void __iomem *clk_base, void __iomem *pmc, | |
289 | unsigned long flags, unsigned long fixed_rate, | |
290 | struct tegra_clk_pll_params *pll_params, | |
291 | u32 pll_flags, | |
292 | struct tegra_clk_pll_freq_table *freq_table, | |
293 | spinlock_t *lock); | |
294 | ||
295 | struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, | |
296 | void __iomem *clk_base, void __iomem *pmc, | |
297 | unsigned long flags, unsigned long fixed_rate, | |
298 | struct tegra_clk_pll_params *pll_params, | |
299 | u32 pll_flags, | |
300 | struct tegra_clk_pll_freq_table *freq_table, | |
301 | spinlock_t *lock, unsigned long parent_rate); | |
302 | ||
303 | struct clk *tegra_clk_register_plle_tegra114(const char *name, | |
304 | const char *parent_name, | |
305 | void __iomem *clk_base, unsigned long flags, | |
306 | unsigned long fixed_rate, | |
307 | struct tegra_clk_pll_params *pll_params, | |
308 | struct tegra_clk_pll_freq_table *freq_table, | |
309 | spinlock_t *lock); | |
310 | ||
8f8f484b PG |
311 | /** |
312 | * struct tegra_clk_pll_out - PLL divider down clock | |
313 | * | |
314 | * @hw: handle between common and hardware-specific interfaces | |
315 | * @reg: register containing the PLL divider | |
316 | * @enb_bit_idx: bit to enable/disable PLL divider | |
317 | * @rst_bit_idx: bit to reset PLL divider | |
318 | * @lock: register lock | |
319 | * @flags: hardware-specific flags | |
320 | */ | |
321 | struct tegra_clk_pll_out { | |
322 | struct clk_hw hw; | |
323 | void __iomem *reg; | |
324 | u8 enb_bit_idx; | |
325 | u8 rst_bit_idx; | |
326 | spinlock_t *lock; | |
327 | u8 flags; | |
328 | }; | |
329 | ||
330 | #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) | |
331 | ||
332 | extern const struct clk_ops tegra_clk_pll_out_ops; | |
333 | struct clk *tegra_clk_register_pll_out(const char *name, | |
334 | const char *parent_name, void __iomem *reg, u8 enb_bit_idx, | |
335 | u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, | |
336 | spinlock_t *lock); | |
337 | ||
338 | /** | |
339 | * struct tegra_clk_periph_regs - Registers controlling peripheral clock | |
340 | * | |
341 | * @enb_reg: read the enable status | |
342 | * @enb_set_reg: write 1 to enable clock | |
343 | * @enb_clr_reg: write 1 to disable clock | |
344 | * @rst_reg: read the reset status | |
345 | * @rst_set_reg: write 1 to assert the reset of peripheral | |
346 | * @rst_clr_reg: write 1 to deassert the reset of peripheral | |
347 | */ | |
348 | struct tegra_clk_periph_regs { | |
349 | u32 enb_reg; | |
350 | u32 enb_set_reg; | |
351 | u32 enb_clr_reg; | |
352 | u32 rst_reg; | |
353 | u32 rst_set_reg; | |
354 | u32 rst_clr_reg; | |
355 | }; | |
356 | ||
357 | /** | |
358 | * struct tegra_clk_periph_gate - peripheral gate clock | |
359 | * | |
360 | * @magic: magic number to validate type | |
361 | * @hw: handle between common and hardware-specific interfaces | |
362 | * @clk_base: address of CAR controller | |
363 | * @regs: Registers to control the peripheral | |
364 | * @flags: hardware-specific flags | |
365 | * @clk_num: Clock number | |
366 | * @enable_refcnt: array to maintain reference count of the clock | |
367 | * | |
368 | * Flags: | |
369 | * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed | |
370 | * for this module. | |
371 | * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module | |
372 | * after clock enable and driver for the module is responsible for | |
373 | * doing reset. | |
374 | * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the | |
375 | * bus to flush the write operation in apb bus. This flag indicates | |
376 | * that this peripheral is in apb bus. | |
fdcccbd8 | 377 | * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug |
8f8f484b PG |
378 | */ |
379 | struct tegra_clk_periph_gate { | |
380 | u32 magic; | |
381 | struct clk_hw hw; | |
382 | void __iomem *clk_base; | |
383 | u8 flags; | |
384 | int clk_num; | |
385 | int *enable_refcnt; | |
386 | struct tegra_clk_periph_regs *regs; | |
387 | }; | |
388 | ||
389 | #define to_clk_periph_gate(_hw) \ | |
390 | container_of(_hw, struct tegra_clk_periph_gate, hw) | |
391 | ||
392 | #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 | |
393 | ||
394 | #define TEGRA_PERIPH_NO_RESET BIT(0) | |
395 | #define TEGRA_PERIPH_MANUAL_RESET BIT(1) | |
396 | #define TEGRA_PERIPH_ON_APB BIT(2) | |
fdcccbd8 | 397 | #define TEGRA_PERIPH_WAR_1005168 BIT(3) |
8f8f484b PG |
398 | |
399 | void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); | |
400 | extern const struct clk_ops tegra_clk_periph_gate_ops; | |
401 | struct clk *tegra_clk_register_periph_gate(const char *name, | |
402 | const char *parent_name, u8 gate_flags, void __iomem *clk_base, | |
403 | unsigned long flags, int clk_num, | |
404 | struct tegra_clk_periph_regs *pregs, int *enable_refcnt); | |
405 | ||
406 | /** | |
407 | * struct clk-periph - peripheral clock | |
408 | * | |
409 | * @magic: magic number to validate type | |
410 | * @hw: handle between common and hardware-specific interfaces | |
411 | * @mux: mux clock | |
412 | * @divider: divider clock | |
413 | * @gate: gate clock | |
414 | * @mux_ops: mux clock ops | |
415 | * @div_ops: divider clock ops | |
416 | * @gate_ops: gate clock ops | |
417 | */ | |
418 | struct tegra_clk_periph { | |
419 | u32 magic; | |
420 | struct clk_hw hw; | |
421 | struct clk_mux mux; | |
422 | struct tegra_clk_frac_div divider; | |
423 | struct tegra_clk_periph_gate gate; | |
424 | ||
425 | const struct clk_ops *mux_ops; | |
426 | const struct clk_ops *div_ops; | |
427 | const struct clk_ops *gate_ops; | |
428 | }; | |
429 | ||
430 | #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) | |
431 | ||
432 | #define TEGRA_CLK_PERIPH_MAGIC 0x18221223 | |
433 | ||
434 | extern const struct clk_ops tegra_clk_periph_ops; | |
435 | struct clk *tegra_clk_register_periph(const char *name, | |
436 | const char **parent_names, int num_parents, | |
437 | struct tegra_clk_periph *periph, void __iomem *clk_base, | |
a26a0298 | 438 | u32 offset, unsigned long flags); |
8f8f484b PG |
439 | struct clk *tegra_clk_register_periph_nodiv(const char *name, |
440 | const char **parent_names, int num_parents, | |
441 | struct tegra_clk_periph *periph, void __iomem *clk_base, | |
442 | u32 offset); | |
443 | ||
ce4f3313 | 444 | #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ |
8f8f484b PG |
445 | _div_shift, _div_width, _div_frac_width, \ |
446 | _div_flags, _clk_num, _enb_refcnt, _regs, \ | |
ce4f3313 | 447 | _gate_flags, _table) \ |
8f8f484b PG |
448 | { \ |
449 | .mux = { \ | |
450 | .flags = _mux_flags, \ | |
451 | .shift = _mux_shift, \ | |
ce4f3313 PDS |
452 | .mask = _mux_mask, \ |
453 | .table = _table, \ | |
8f8f484b PG |
454 | }, \ |
455 | .divider = { \ | |
456 | .flags = _div_flags, \ | |
457 | .shift = _div_shift, \ | |
458 | .width = _div_width, \ | |
459 | .frac_width = _div_frac_width, \ | |
460 | }, \ | |
461 | .gate = { \ | |
462 | .flags = _gate_flags, \ | |
463 | .clk_num = _clk_num, \ | |
464 | .enable_refcnt = _enb_refcnt, \ | |
465 | .regs = _regs, \ | |
466 | }, \ | |
467 | .mux_ops = &clk_mux_ops, \ | |
468 | .div_ops = &tegra_clk_frac_div_ops, \ | |
469 | .gate_ops = &tegra_clk_periph_gate_ops, \ | |
470 | } | |
471 | ||
472 | struct tegra_periph_init_data { | |
473 | const char *name; | |
474 | int clk_id; | |
475 | const char **parent_names; | |
476 | int num_parents; | |
477 | struct tegra_clk_periph periph; | |
478 | u32 offset; | |
479 | const char *con_id; | |
480 | const char *dev_id; | |
a26a0298 | 481 | unsigned long flags; |
8f8f484b PG |
482 | }; |
483 | ||
ce4f3313 PDS |
484 | #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ |
485 | _mux_shift, _mux_mask, _mux_flags, _div_shift, \ | |
8f8f484b | 486 | _div_width, _div_frac_width, _div_flags, _regs, \ |
a26a0298 PDS |
487 | _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\ |
488 | _flags) \ | |
8f8f484b PG |
489 | { \ |
490 | .name = _name, \ | |
491 | .clk_id = _clk_id, \ | |
492 | .parent_names = _parent_names, \ | |
493 | .num_parents = ARRAY_SIZE(_parent_names), \ | |
ce4f3313 | 494 | .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ |
8f8f484b PG |
495 | _mux_flags, _div_shift, \ |
496 | _div_width, _div_frac_width, \ | |
497 | _div_flags, _clk_num, \ | |
498 | _enb_refcnt, _regs, \ | |
ce4f3313 | 499 | _gate_flags, _table), \ |
8f8f484b PG |
500 | .offset = _offset, \ |
501 | .con_id = _con_id, \ | |
502 | .dev_id = _dev_id, \ | |
a26a0298 | 503 | .flags = _flags \ |
8f8f484b PG |
504 | } |
505 | ||
ce4f3313 PDS |
506 | #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ |
507 | _mux_shift, _mux_width, _mux_flags, _div_shift, \ | |
508 | _div_width, _div_frac_width, _div_flags, _regs, \ | |
509 | _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ | |
510 | TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ | |
511 | _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ | |
512 | _div_shift, _div_width, _div_frac_width, _div_flags, \ | |
513 | _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ | |
a26a0298 | 514 | NULL, 0) |
ce4f3313 | 515 | |
8f8f484b PG |
516 | /** |
517 | * struct clk_super_mux - super clock | |
518 | * | |
519 | * @hw: handle between common and hardware-specific interfaces | |
520 | * @reg: register controlling multiplexer | |
521 | * @width: width of the multiplexer bit field | |
522 | * @flags: hardware-specific flags | |
523 | * @div2_index: bit controlling divide-by-2 | |
524 | * @pllx_index: PLLX index in the parent list | |
525 | * @lock: register lock | |
526 | * | |
527 | * Flags: | |
528 | * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates | |
529 | * that this is LP cluster clock. | |
530 | */ | |
531 | struct tegra_clk_super_mux { | |
532 | struct clk_hw hw; | |
533 | void __iomem *reg; | |
534 | u8 width; | |
535 | u8 flags; | |
536 | u8 div2_index; | |
537 | u8 pllx_index; | |
538 | spinlock_t *lock; | |
539 | }; | |
540 | ||
541 | #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) | |
542 | ||
543 | #define TEGRA_DIVIDER_2 BIT(0) | |
544 | ||
545 | extern const struct clk_ops tegra_clk_super_ops; | |
546 | struct clk *tegra_clk_register_super_mux(const char *name, | |
547 | const char **parent_names, u8 num_parents, | |
548 | unsigned long flags, void __iomem *reg, u8 clk_super_flags, | |
549 | u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); | |
550 | ||
551 | /** | |
552 | * struct clk_init_tabel - clock initialization table | |
553 | * @clk_id: clock id as mentioned in device tree bindings | |
554 | * @parent_id: parent clock id as mentioned in device tree bindings | |
555 | * @rate: rate to set | |
556 | * @state: enable/disable | |
557 | */ | |
558 | struct tegra_clk_init_table { | |
559 | unsigned int clk_id; | |
560 | unsigned int parent_id; | |
561 | unsigned long rate; | |
562 | int state; | |
563 | }; | |
564 | ||
565 | /** | |
566 | * struct clk_duplicate - duplicate clocks | |
567 | * @clk_id: clock id as mentioned in device tree bindings | |
568 | * @lookup: duplicate lookup entry for the clock | |
569 | */ | |
570 | struct tegra_clk_duplicate { | |
571 | int clk_id; | |
572 | struct clk_lookup lookup; | |
573 | }; | |
574 | ||
575 | #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ | |
576 | { \ | |
577 | .clk_id = _clk_id, \ | |
578 | .lookup = { \ | |
579 | .dev_id = _dev, \ | |
580 | .con_id = _con, \ | |
581 | }, \ | |
582 | } | |
583 | ||
584 | void tegra_init_from_table(struct tegra_clk_init_table *tbl, | |
585 | struct clk *clks[], int clk_max); | |
586 | ||
587 | void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, | |
588 | struct clk *clks[], int clk_max); | |
589 | ||
25c9ded6 PW |
590 | void tegra114_clock_tune_cpu_trimmers_high(void); |
591 | void tegra114_clock_tune_cpu_trimmers_low(void); | |
592 | void tegra114_clock_tune_cpu_trimmers_init(void); | |
1c472d8e PW |
593 | void tegra114_clock_assert_dfll_dvco_reset(void); |
594 | void tegra114_clock_deassert_dfll_dvco_reset(void); | |
25c9ded6 | 595 | |
441f199a SW |
596 | typedef void (*tegra_clk_apply_init_table_func)(void); |
597 | extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; | |
598 | ||
8f8f484b | 599 | #endif /* TEGRA_CLK_H */ |