Commit | Line | Data |
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251a449d TK |
1 | /* |
2 | * DRA7 Clock init | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * Tero Kristo (t-kristo@ti.com) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/list.h> | |
e387088a | 15 | #include <linux/clk.h> |
251a449d TK |
16 | #include <linux/clkdev.h> |
17 | #include <linux/clk/ti.h> | |
18 | ||
a3314e9c TK |
19 | #include "clock.h" |
20 | ||
251a449d | 21 | #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 |
94e72ae5 | 22 | #define DRA7_DPLL_USB_DEFFREQ 960000000 |
251a449d | 23 | |
251a449d TK |
24 | static struct ti_dt_clk dra7xx_clks[] = { |
25 | DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), | |
26 | DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), | |
27 | DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"), | |
0cccd919 | 28 | DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"), |
251a449d TK |
29 | DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"), |
30 | DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"), | |
31 | DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"), | |
32 | DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"), | |
33 | DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"), | |
34 | DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"), | |
35 | DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"), | |
36 | DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"), | |
37 | DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"), | |
38 | DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"), | |
39 | DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), | |
40 | DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), | |
41 | DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), | |
42 | DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), | |
43 | DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), | |
44 | DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), | |
45 | DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"), | |
46 | DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), | |
47 | DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), | |
48 | DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), | |
49 | DT_CLK(NULL, "sys_clkin1", "sys_clkin1"), | |
50 | DT_CLK(NULL, "sys_clkin2", "sys_clkin2"), | |
51 | DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"), | |
52 | DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"), | |
53 | DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"), | |
54 | DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"), | |
55 | DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"), | |
56 | DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"), | |
57 | DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"), | |
58 | DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"), | |
59 | DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), | |
60 | DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), | |
61 | DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), | |
62 | DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), | |
63 | DT_CLK(NULL, "abe_clk", "abe_clk"), | |
64 | DT_CLK(NULL, "aess_fclk", "aess_fclk"), | |
65 | DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"), | |
66 | DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"), | |
67 | DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"), | |
68 | DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"), | |
69 | DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"), | |
70 | DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"), | |
71 | DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"), | |
72 | DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"), | |
73 | DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"), | |
74 | DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"), | |
75 | DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"), | |
76 | DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"), | |
77 | DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"), | |
78 | DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"), | |
79 | DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), | |
80 | DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), | |
81 | DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), | |
82 | DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"), | |
83 | DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"), | |
84 | DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), | |
85 | DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), | |
86 | DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"), | |
87 | DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"), | |
88 | DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"), | |
89 | DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"), | |
90 | DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"), | |
91 | DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"), | |
92 | DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), | |
93 | DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"), | |
94 | DT_CLK(NULL, "iva_dclk", "iva_dclk"), | |
95 | DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"), | |
96 | DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"), | |
97 | DT_CLK(NULL, "gpu_dclk", "gpu_dclk"), | |
98 | DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), | |
99 | DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"), | |
100 | DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"), | |
101 | DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"), | |
102 | DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"), | |
103 | DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"), | |
104 | DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"), | |
105 | DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"), | |
106 | DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"), | |
107 | DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"), | |
108 | DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"), | |
109 | DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"), | |
110 | DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), | |
111 | DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), | |
112 | DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"), | |
113 | DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"), | |
114 | DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), | |
115 | DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), | |
116 | DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"), | |
117 | DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"), | |
118 | DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"), | |
119 | DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"), | |
120 | DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"), | |
121 | DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"), | |
122 | DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"), | |
123 | DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"), | |
124 | DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"), | |
125 | DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"), | |
126 | DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"), | |
127 | DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"), | |
128 | DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"), | |
129 | DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"), | |
130 | DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"), | |
131 | DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"), | |
132 | DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"), | |
133 | DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"), | |
134 | DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"), | |
135 | DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"), | |
136 | DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"), | |
137 | DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"), | |
138 | DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"), | |
139 | DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"), | |
140 | DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"), | |
141 | DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"), | |
142 | DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"), | |
143 | DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"), | |
144 | DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"), | |
145 | DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"), | |
146 | DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), | |
147 | DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"), | |
148 | DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"), | |
149 | DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"), | |
150 | DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"), | |
151 | DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), | |
152 | DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"), | |
153 | DT_CLK(NULL, "eve_clk", "eve_clk"), | |
154 | DT_CLK(NULL, "func_128m_clk", "func_128m_clk"), | |
155 | DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), | |
156 | DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), | |
157 | DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), | |
158 | DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), | |
159 | DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"), | |
160 | DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"), | |
161 | DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"), | |
162 | DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"), | |
163 | DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"), | |
164 | DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"), | |
165 | DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"), | |
166 | DT_CLK(NULL, "mlb_clk", "mlb_clk"), | |
167 | DT_CLK(NULL, "mlbp_clk", "mlbp_clk"), | |
168 | DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"), | |
169 | DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"), | |
170 | DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"), | |
171 | DT_CLK(NULL, "video1_div_clk", "video1_div_clk"), | |
172 | DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"), | |
173 | DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"), | |
174 | DT_CLK(NULL, "video2_div_clk", "video2_div_clk"), | |
175 | DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"), | |
176 | DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"), | |
177 | DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"), | |
178 | DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), | |
179 | DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), | |
180 | DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"), | |
181 | DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"), | |
182 | DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"), | |
183 | DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), | |
184 | DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), | |
185 | DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), | |
186 | DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), | |
187 | DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), | |
188 | DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), | |
189 | DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"), | |
190 | DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"), | |
191 | DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"), | |
192 | DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"), | |
193 | DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"), | |
194 | DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"), | |
195 | DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"), | |
196 | DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"), | |
197 | DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"), | |
198 | DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"), | |
199 | DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"), | |
200 | DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"), | |
201 | DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"), | |
202 | DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"), | |
203 | DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"), | |
204 | DT_CLK(NULL, "gmac_gmii_ref_clk_div", "gmac_gmii_ref_clk_div"), | |
205 | DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"), | |
206 | DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"), | |
207 | DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"), | |
208 | DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"), | |
209 | DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"), | |
210 | DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"), | |
211 | DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"), | |
212 | DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"), | |
213 | DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"), | |
214 | DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"), | |
215 | DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"), | |
216 | DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"), | |
217 | DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"), | |
218 | DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"), | |
219 | DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"), | |
220 | DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"), | |
221 | DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"), | |
222 | DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"), | |
223 | DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"), | |
224 | DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"), | |
225 | DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"), | |
226 | DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"), | |
227 | DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"), | |
228 | DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), | |
229 | DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"), | |
230 | DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"), | |
231 | DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"), | |
232 | DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"), | |
233 | DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"), | |
234 | DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"), | |
235 | DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"), | |
236 | DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"), | |
237 | DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"), | |
238 | DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"), | |
239 | DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"), | |
240 | DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"), | |
241 | DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"), | |
242 | DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"), | |
243 | DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"), | |
244 | DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"), | |
245 | DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"), | |
246 | DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"), | |
247 | DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"), | |
248 | DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"), | |
249 | DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"), | |
250 | DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"), | |
251 | DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"), | |
252 | DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"), | |
253 | DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"), | |
254 | DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"), | |
255 | DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"), | |
256 | DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"), | |
257 | DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"), | |
258 | DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"), | |
259 | DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"), | |
260 | DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"), | |
261 | DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"), | |
262 | DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"), | |
263 | DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"), | |
264 | DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"), | |
265 | DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"), | |
251a449d TK |
266 | DT_CLK("omap_i2c.1", "ick", "dummy_ck"), |
267 | DT_CLK("omap_i2c.2", "ick", "dummy_ck"), | |
268 | DT_CLK("omap_i2c.3", "ick", "dummy_ck"), | |
269 | DT_CLK("omap_i2c.4", "ick", "dummy_ck"), | |
270 | DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), | |
271 | DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), | |
272 | DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), | |
273 | DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), | |
274 | DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), | |
275 | DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), | |
276 | DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), | |
277 | DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), | |
278 | DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), | |
279 | DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), | |
280 | DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), | |
281 | DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), | |
282 | DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), | |
283 | DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), | |
284 | DT_CLK(NULL, "uart1_ick", "dummy_ck"), | |
285 | DT_CLK(NULL, "uart2_ick", "dummy_ck"), | |
286 | DT_CLK(NULL, "uart3_ick", "dummy_ck"), | |
287 | DT_CLK(NULL, "uart4_ick", "dummy_ck"), | |
288 | DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), | |
289 | DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), | |
290 | DT_CLK("omap_wdt", "ick", "dummy_ck"), | |
291 | DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), | |
d4295be3 SA |
292 | DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"), |
293 | DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
294 | DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
295 | DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
296 | DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
297 | DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
298 | DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
251a449d TK |
299 | DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"), |
300 | DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
301 | DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
302 | DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
712f7d64 SA |
303 | DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"), |
304 | DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
305 | DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
306 | DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"), | |
251a449d | 307 | DT_CLK(NULL, "sys_clkin", "sys_clkin1"), |
2d5a3c80 | 308 | DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"), |
251a449d TK |
309 | { .node_name = NULL }, |
310 | }; | |
311 | ||
312 | int __init dra7xx_dt_clk_init(void) | |
313 | { | |
314 | int rc; | |
4b3061b3 | 315 | struct clk *dpll_ck, *hdcp_ck; |
251a449d TK |
316 | |
317 | ti_dt_clocks_register(dra7xx_clks); | |
318 | ||
319 | omap2_clk_disable_autoidle_all(); | |
320 | ||
251a449d TK |
321 | dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); |
322 | rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); | |
323 | if (rc) | |
324 | pr_err("%s: failed to configure GMAC DPLL!\n", __func__); | |
325 | ||
94e72ae5 RQ |
326 | dpll_ck = clk_get_sys(NULL, "dpll_usb_ck"); |
327 | rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ); | |
328 | if (rc) | |
329 | pr_err("%s: failed to configure USB DPLL!\n", __func__); | |
330 | ||
331 | dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck"); | |
332 | rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2); | |
333 | if (rc) | |
334 | pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); | |
335 | ||
f892b203 TV |
336 | hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); |
337 | rc = clk_prepare_enable(hdcp_ck); | |
338 | if (rc) | |
339 | pr_err("%s: failed to set dss_deshdcp_clk\n", __func__); | |
340 | ||
251a449d TK |
341 | return rc; |
342 | } |