[deliverable/linux.git] / drivers / clk / ti / dpll44xx.c

/*
 * OMAP4-specific DPLL control functions
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Rajendra Nayak
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/clk/ti.h>

#include "clock.h"

/*
 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
 * can supported when using the DPLL low-power mode. Frequencies are
 * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
 * Status, and Low-Power Operation Mode".
 */
#define OMAP4_DPLL_LP_FINT_MAX	1000000
#define OMAP4_DPLL_LP_FOUT_MAX	100000000

/*
 * Bitfield declarations
 */
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK		BIT(8)
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK		BIT(10)
#define OMAP4430_DPLL_REGM4XEN_MASK			BIT(11)

/* Static rate multiplier for OMAP4 REGM4XEN clocks */
#define OMAP4430_REGM4XEN_MULT				4

static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
{
	u32 v;
	u32 mask;

	if (!clk || !clk->clksel_reg)
		return;

	mask = clk->flags & CLOCK_CLKOUTX2 ?
			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;

	v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);
	/* Clear the bit to allow gatectrl */
	v &= ~mask;
	ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);
}

static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
{
	u32 v;
	u32 mask;

	if (!clk || !clk->clksel_reg)
		return;

	mask = clk->flags & CLOCK_CLKOUTX2 ?
			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;

	v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);
	/* Set the bit to deny gatectrl */
	v |= mask;
	ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);
}

const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
	.allow_idle	= omap4_dpllmx_allow_gatectrl,
	.deny_idle      = omap4_dpllmx_deny_gatectrl,
};

/**
 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
 * @dd: pointer to the dpll data structure
 *
 * Calculates if low-power mode can be enabled based upon the last
 * multiplier and divider values calculated. If low-power mode can be
 * enabled, then the bit to enable low-power mode is stored in the
 * last_rounded_lpmode variable. This implementation is based upon the
 * criteria for enabling low-power mode as described in the OMAP4430/60
 * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
 * Operation Mode".
 */
static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
{
	long fint, fout;

	fint = clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
	fout = fint * dd->last_rounded_m;

	if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
		dd->last_rounded_lpmode = 1;
	else
		dd->last_rounded_lpmode = 0;
}

/**
 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
 * @clk: struct clk * of the DPLL to compute the rate for
 *
 * Compute the output rate for the OMAP4 DPLL represented by @clk.
 * Takes the REGM4XEN bit into consideration, which is needed for the
 * OMAP4 ABE DPLL.  Returns the DPLL's output rate (before M-dividers)
 * upon success, or 0 upon error.
 */
unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
					 unsigned long parent_rate)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	u32 v;
	unsigned long rate;
	struct dpll_data *dd;

	if (!clk || !clk->dpll_data)
		return 0;

	dd = clk->dpll_data;

	rate = omap2_get_dpll_rate(clk);

	/* regm4xen adds a multiplier of 4 to DPLL calculations */
	v = ti_clk_ll_ops->clk_readl(dd->control_reg);
	if (v & OMAP4430_DPLL_REGM4XEN_MASK)
		rate *= OMAP4430_REGM4XEN_MULT;

	return rate;
}

/**
 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
 * @clk: struct clk * of the DPLL to round a rate for
 * @target_rate: the desired rate of the DPLL
 *
 * Compute the rate that would be programmed into the DPLL hardware
 * for @clk if set_rate() were to be provided with the rate
 * @target_rate.  Takes the REGM4XEN bit into consideration, which is
 * needed for the OMAP4 ABE DPLL.  Returns the rounded rate (before
 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
 * ~0 if an error occurred in omap2_dpll_round_rate().
 */
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
				    unsigned long target_rate,
				    unsigned long *parent_rate)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	struct dpll_data *dd;
	long r;

	if (!clk || !clk->dpll_data)
		return -EINVAL;

	dd = clk->dpll_data;

	dd->last_rounded_m4xen = 0;

	/*
	 * First try to compute the DPLL configuration for
	 * target rate without using the 4X multiplier.
	 */
	r = omap2_dpll_round_rate(hw, target_rate, NULL);
	if (r != ~0)
		goto out;

	/*
	 * If we did not find a valid DPLL configuration, try again, but
	 * this time see if using the 4X multiplier can help. Enabling the
	 * 4X multiplier is equivalent to dividing the target rate by 4.
	 */
	r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
				  NULL);
	if (r == ~0)
		return r;

	dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
	dd->last_rounded_m4xen = 1;

out:
	omap4_dpll_lpmode_recalc(dd);

	return dd->last_rounded_rate;
}

/**
 * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
 * @hw: pointer to the clock to determine rate for
 * @req: target rate request
 *
 * Determines which DPLL mode to use for reaching a desired rate.
 * Checks whether the DPLL shall be in bypass or locked mode, and if
 * locked, calculates the M,N values for the DPLL via round-rate.
 * Returns 0 on success and a negative error value otherwise.
 */
int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
				       struct clk_rate_request *req)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	struct dpll_data *dd;

	if (!req->rate)
		return -EINVAL;

	dd = clk->dpll_data;
	if (!dd)
		return -EINVAL;

	if (clk_get_rate(dd->clk_bypass) == req->rate &&
	    (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
		req->best_parent_hw = __clk_get_hw(dd->clk_bypass);
	} else {
		req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
						&req->best_parent_rate);
		req->best_parent_hw = __clk_get_hw(dd->clk_ref);
	}

	req->best_parent_rate = req->rate;

	return 0;
}
Commit	Line	Data
97f67898 RN	1	/*
	2	* OMAP4-specific DPLL control functions
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Rajendra Nayak
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/errno.h>
	14	#include <linux/clk.h>
	15	#include <linux/io.h>
	16	#include <linux/bitops.h>
59245ce0	17	#include <linux/clk/ti.h>
97f67898	18
97f67898	19	#include "clock.h"
97f67898	20
3ff51ed8 JH	21	/*
	22	* Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
	23	* can supported when using the DPLL low-power mode. Frequencies are
	24	* defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
	25	* Status, and Low-Power Operation Mode".
	26	*/
	27	#define OMAP4_DPLL_LP_FINT_MAX 1000000
	28	#define OMAP4_DPLL_LP_FOUT_MAX 100000000
	29
44b65e76 TK	30	/*
	31	* Bitfield declarations
	32	*/
59245ce0 TK	33	#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8)
	34	#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10)
	35	#define OMAP4430_DPLL_REGM4XEN_MASK BIT(11)
44b65e76 TK	36
	37	/* Static rate multiplier for OMAP4 REGM4XEN clocks */
	38	#define OMAP4430_REGM4XEN_MULT 4
	39
59245ce0	40	static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
97f67898 RN	41	{
	42	u32 v;
	43	u32 mask;
	44
74b9b62b	45	if (!clk \|\| !clk->clksel_reg)
97f67898 RN	46	return;
	47
	48	mask = clk->flags & CLOCK_CLKOUTX2 ?
	49	OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
	50	OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
	51
59245ce0	52	v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);
97f67898 RN	53	/* Clear the bit to allow gatectrl */
97f67898 RN	54	v &= ~mask;
59245ce0	55	ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);
97f67898 RN	56	}
97f67898 RN	57
59245ce0	58	static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
97f67898 RN	59	{
	60	u32 v;
	61	u32 mask;
	62
74b9b62b	63	if (!clk \|\| !clk->clksel_reg)
97f67898 RN	64	return;
	65
	66	mask = clk->flags & CLOCK_CLKOUTX2 ?
	67	OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
	68	OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
	69
59245ce0	70	v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);
97f67898 RN	71	/* Set the bit to deny gatectrl */
97f67898 RN	72	v \|= mask;
59245ce0	73	ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);
97f67898	74	}
70db8a62	75
32cc0021 MT	76	const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
	77	.allow_idle = omap4_dpllmx_allow_gatectrl,
	78	.deny_idle = omap4_dpllmx_deny_gatectrl,
	79	};
70db8a62	80
3ff51ed8 JH	81	/**
	82	* omap4_dpll_lpmode_recalc - compute DPLL low-power setting
	83	* @dd: pointer to the dpll data structure
	84	*
	85	* Calculates if low-power mode can be enabled based upon the last
	86	* multiplier and divider values calculated. If low-power mode can be
	87	* enabled, then the bit to enable low-power mode is stored in the
	88	* last_rounded_lpmode variable. This implementation is based upon the
	89	* criteria for enabling low-power mode as described in the OMAP4430/60
	90	* Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
	91	* Operation Mode".
	92	*/
	93	static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
	94	{
	95	long fint, fout;
	96
a53ad8ef	97	fint = clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
3ff51ed8 JH	98	fout = fint * dd->last_rounded_m;
	99
	100	if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
	101	dd->last_rounded_lpmode = 1;
	102	else
	103	dd->last_rounded_lpmode = 0;
	104	}
	105
a1900f2e MT	106	/**
	107	* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
	108	* @clk: struct clk * of the DPLL to compute the rate for
	109	*
	110	* Compute the output rate for the OMAP4 DPLL represented by @clk.
	111	* Takes the REGM4XEN bit into consideration, which is needed for the
	112	* OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
	113	* upon success, or 0 upon error.
	114	*/
32cc0021	115	unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
59245ce0	116	unsigned long parent_rate)
32cc0021 MT	117	{
32cc0021 MT	118	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
a1900f2e MT	119	u32 v;
	120	unsigned long rate;
	121	struct dpll_data *dd;
	122
	123	if (!clk \|\| !clk->dpll_data)
	124	return 0;
	125
	126	dd = clk->dpll_data;
	127
	128	rate = omap2_get_dpll_rate(clk);
	129
	130	/* regm4xen adds a multiplier of 4 to DPLL calculations */
59245ce0	131	v = ti_clk_ll_ops->clk_readl(dd->control_reg);
a1900f2e MT	132	if (v & OMAP4430_DPLL_REGM4XEN_MASK)
	133	rate *= OMAP4430_REGM4XEN_MULT;
	134
	135	return rate;
	136	}
	137
	138	/**
	139	* omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
	140	* @clk: struct clk * of the DPLL to round a rate for
	141	* @target_rate: the desired rate of the DPLL
	142	*
	143	* Compute the rate that would be programmed into the DPLL hardware
	144	* for @clk if set_rate() were to be provided with the rate
	145	* @target_rate. Takes the REGM4XEN bit into consideration, which is
	146	* needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
	147	* M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
	148	* ~0 if an error occurred in omap2_dpll_round_rate().
	149	*/
32cc0021 MT	150	long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
	151	unsigned long target_rate,
	152	unsigned long *parent_rate)
	153	{
	154	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
a1900f2e MT	155	struct dpll_data *dd;
	156	long r;
	157
	158	if (!clk \|\| !clk->dpll_data)
	159	return -EINVAL;
	160
	161	dd = clk->dpll_data;
	162
3ff51ed8	163	dd->last_rounded_m4xen = 0;
a1900f2e	164
3ff51ed8 JH	165	/*
	166	* First try to compute the DPLL configuration for
	167	* target rate without using the 4X multiplier.
	168	*/
32cc0021	169	r = omap2_dpll_round_rate(hw, target_rate, NULL);
3ff51ed8 JH	170	if (r != ~0)
	171	goto out;
	172
	173	/*
	174	* If we did not find a valid DPLL configuration, try again, but
	175	* this time see if using the 4X multiplier can help. Enabling the
	176	* 4X multiplier is equivalent to dividing the target rate by 4.
	177	*/
	178	r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
	179	NULL);
a1900f2e MT	180	if (r == ~0)
	181	return r;
	182
3ff51ed8 JH	183	dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
	184	dd->last_rounded_m4xen = 1;
	185
	186	out:
	187	omap4_dpll_lpmode_recalc(dd);
a1900f2e	188
3ff51ed8	189	return dd->last_rounded_rate;
a1900f2e	190	}
83501ff0 TK	191
	192	/**
	193	* omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
	194	* @hw: pointer to the clock to determine rate for
0817b62c	195	* @req: target rate request
83501ff0 TK	196	*
	197	* Determines which DPLL mode to use for reaching a desired rate.
	198	* Checks whether the DPLL shall be in bypass or locked mode, and if
	199	* locked, calculates the M,N values for the DPLL via round-rate.
0817b62c	200	* Returns 0 on success and a negative error value otherwise.
83501ff0	201	*/
0817b62c BB	202	int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
0817b62c BB	203	struct clk_rate_request *req)
83501ff0 TK	204	{
	205	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	206	struct dpll_data *dd;
	207
0817b62c	208	if (!req->rate)
83501ff0 TK	209	return -EINVAL;
	210
	211	dd = clk->dpll_data;
	212	if (!dd)
	213	return -EINVAL;
	214
a53ad8ef	215	if (clk_get_rate(dd->clk_bypass) == req->rate &&
83501ff0	216	(dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
0817b62c	217	req->best_parent_hw = __clk_get_hw(dd->clk_bypass);
83501ff0	218	} else {
0817b62c BB	219	req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
	220	&req->best_parent_rate);
	221	req->best_parent_hw = __clk_get_hw(dd->clk_ref);
83501ff0 TK	222	}
83501ff0 TK	223
0817b62c	224	req->best_parent_rate = req->rate;
83501ff0	225
0817b62c	226	return 0;
83501ff0	227	}