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6a369c58 TK |
1 | /* |
2 | * TI Multiplexer Clock | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments, Inc. | |
5 | * | |
6 | * Tero Kristo <t-kristo@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
13 | * kind, whether express or implied; without even the implied warranty | |
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/clk-provider.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/clk/ti.h> | |
7c18a65c | 24 | #include "clock.h" |
6a369c58 TK |
25 | |
26 | #undef pr_fmt | |
27 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
28 | ||
29 | #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) | |
30 | ||
31 | static u8 ti_clk_mux_get_parent(struct clk_hw *hw) | |
32 | { | |
33 | struct clk_mux *mux = to_clk_mux(hw); | |
497295af | 34 | int num_parents = clk_hw_get_num_parents(hw); |
6a369c58 TK |
35 | u32 val; |
36 | ||
37 | /* | |
38 | * FIXME need a mux-specific flag to determine if val is bitwise or | |
39 | * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges | |
40 | * from 0x1 to 0x7 (index starts at one) | |
41 | * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so | |
42 | * val = 0x4 really means "bit 2, index starts at bit 0" | |
43 | */ | |
44 | val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift; | |
45 | val &= mux->mask; | |
46 | ||
47 | if (mux->table) { | |
48 | int i; | |
49 | ||
50 | for (i = 0; i < num_parents; i++) | |
51 | if (mux->table[i] == val) | |
52 | return i; | |
53 | return -EINVAL; | |
54 | } | |
55 | ||
56 | if (val && (mux->flags & CLK_MUX_INDEX_BIT)) | |
57 | val = ffs(val) - 1; | |
58 | ||
59 | if (val && (mux->flags & CLK_MUX_INDEX_ONE)) | |
60 | val--; | |
61 | ||
62 | if (val >= num_parents) | |
63 | return -EINVAL; | |
64 | ||
65 | return val; | |
66 | } | |
67 | ||
68 | static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |
69 | { | |
70 | struct clk_mux *mux = to_clk_mux(hw); | |
71 | u32 val; | |
6a369c58 TK |
72 | |
73 | if (mux->table) { | |
74 | index = mux->table[index]; | |
75 | } else { | |
76 | if (mux->flags & CLK_MUX_INDEX_BIT) | |
77 | index = (1 << ffs(index)); | |
78 | ||
79 | if (mux->flags & CLK_MUX_INDEX_ONE) | |
80 | index++; | |
81 | } | |
82 | ||
6a369c58 TK |
83 | if (mux->flags & CLK_MUX_HIWORD_MASK) { |
84 | val = mux->mask << (mux->shift + 16); | |
85 | } else { | |
86 | val = ti_clk_ll_ops->clk_readl(mux->reg); | |
87 | val &= ~(mux->mask << mux->shift); | |
88 | } | |
89 | val |= index << mux->shift; | |
90 | ti_clk_ll_ops->clk_writel(val, mux->reg); | |
91 | ||
6a369c58 TK |
92 | return 0; |
93 | } | |
94 | ||
95 | const struct clk_ops ti_clk_mux_ops = { | |
96 | .get_parent = ti_clk_mux_get_parent, | |
97 | .set_parent = ti_clk_mux_set_parent, | |
98 | .determine_rate = __clk_mux_determine_rate, | |
99 | }; | |
100 | ||
101 | static struct clk *_register_mux(struct device *dev, const char *name, | |
102 | const char **parent_names, u8 num_parents, | |
103 | unsigned long flags, void __iomem *reg, | |
104 | u8 shift, u32 mask, u8 clk_mux_flags, | |
167af5ef | 105 | u32 *table) |
6a369c58 TK |
106 | { |
107 | struct clk_mux *mux; | |
108 | struct clk *clk; | |
109 | struct clk_init_data init; | |
110 | ||
111 | /* allocate the mux */ | |
112 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
113 | if (!mux) { | |
114 | pr_err("%s: could not allocate mux clk\n", __func__); | |
115 | return ERR_PTR(-ENOMEM); | |
116 | } | |
117 | ||
118 | init.name = name; | |
119 | init.ops = &ti_clk_mux_ops; | |
120 | init.flags = flags | CLK_IS_BASIC; | |
121 | init.parent_names = parent_names; | |
122 | init.num_parents = num_parents; | |
123 | ||
124 | /* struct clk_mux assignments */ | |
125 | mux->reg = reg; | |
126 | mux->shift = shift; | |
127 | mux->mask = mask; | |
128 | mux->flags = clk_mux_flags; | |
6a369c58 TK |
129 | mux->table = table; |
130 | mux->hw.init = &init; | |
131 | ||
132 | clk = clk_register(dev, &mux->hw); | |
133 | ||
134 | if (IS_ERR(clk)) | |
135 | kfree(mux); | |
136 | ||
137 | return clk; | |
138 | } | |
139 | ||
7c18a65c TK |
140 | struct clk *ti_clk_register_mux(struct ti_clk *setup) |
141 | { | |
142 | struct ti_clk_mux *mux; | |
143 | u32 flags; | |
144 | u8 mux_flags = 0; | |
145 | struct clk_omap_reg *reg_setup; | |
146 | u32 reg; | |
147 | u32 mask; | |
148 | ||
149 | reg_setup = (struct clk_omap_reg *)® | |
150 | ||
151 | mux = setup->data; | |
152 | flags = CLK_SET_RATE_NO_REPARENT; | |
153 | ||
154 | mask = mux->num_parents; | |
155 | if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE)) | |
156 | mask--; | |
157 | ||
158 | mask = (1 << fls(mask)) - 1; | |
159 | reg_setup->index = mux->module; | |
160 | reg_setup->offset = mux->reg; | |
161 | ||
162 | if (mux->flags & CLKF_INDEX_STARTS_AT_ONE) | |
163 | mux_flags |= CLK_MUX_INDEX_ONE; | |
164 | ||
165 | if (mux->flags & CLKF_SET_RATE_PARENT) | |
166 | flags |= CLK_SET_RATE_PARENT; | |
167 | ||
168 | return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, | |
169 | flags, (void __iomem *)reg, mux->bit_shift, mask, | |
167af5ef | 170 | mux_flags, NULL); |
7c18a65c TK |
171 | } |
172 | ||
6a369c58 TK |
173 | /** |
174 | * of_mux_clk_setup - Setup function for simple mux rate clock | |
175 | * @node: DT node for the clock | |
176 | * | |
177 | * Sets up a basic clock multiplexer. | |
178 | */ | |
179 | static void of_mux_clk_setup(struct device_node *node) | |
180 | { | |
181 | struct clk *clk; | |
182 | void __iomem *reg; | |
183 | int num_parents; | |
184 | const char **parent_names; | |
6a369c58 TK |
185 | u8 clk_mux_flags = 0; |
186 | u32 mask = 0; | |
187 | u32 shift = 0; | |
7d5fc85d | 188 | u32 flags = CLK_SET_RATE_NO_REPARENT; |
6a369c58 TK |
189 | |
190 | num_parents = of_clk_get_parent_count(node); | |
191 | if (num_parents < 2) { | |
192 | pr_err("mux-clock %s must have parents\n", node->name); | |
193 | return; | |
194 | } | |
195 | parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); | |
196 | if (!parent_names) | |
197 | goto cleanup; | |
198 | ||
9da9e761 | 199 | of_clk_parent_fill(node, parent_names, num_parents); |
6a369c58 TK |
200 | |
201 | reg = ti_clk_get_reg_addr(node, 0); | |
202 | ||
c807dbed | 203 | if (IS_ERR(reg)) |
6a369c58 TK |
204 | goto cleanup; |
205 | ||
206 | of_property_read_u32(node, "ti,bit-shift", &shift); | |
207 | ||
208 | if (of_property_read_bool(node, "ti,index-starts-at-one")) | |
209 | clk_mux_flags |= CLK_MUX_INDEX_ONE; | |
210 | ||
211 | if (of_property_read_bool(node, "ti,set-rate-parent")) | |
212 | flags |= CLK_SET_RATE_PARENT; | |
213 | ||
214 | /* Generate bit-mask based on parent info */ | |
215 | mask = num_parents; | |
216 | if (!(clk_mux_flags & CLK_MUX_INDEX_ONE)) | |
217 | mask--; | |
218 | ||
219 | mask = (1 << fls(mask)) - 1; | |
220 | ||
7c18a65c | 221 | clk = _register_mux(NULL, node->name, parent_names, num_parents, |
167af5ef | 222 | flags, reg, shift, mask, clk_mux_flags, NULL); |
6a369c58 TK |
223 | |
224 | if (!IS_ERR(clk)) | |
225 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | |
226 | ||
227 | cleanup: | |
228 | kfree(parent_names); | |
229 | } | |
230 | CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup); | |
231 | ||
7c18a65c TK |
232 | struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup) |
233 | { | |
234 | struct clk_mux *mux; | |
235 | struct clk_omap_reg *reg; | |
236 | int num_parents; | |
237 | ||
238 | if (!setup) | |
239 | return NULL; | |
240 | ||
241 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
242 | if (!mux) | |
243 | return ERR_PTR(-ENOMEM); | |
244 | ||
245 | reg = (struct clk_omap_reg *)&mux->reg; | |
246 | ||
247 | mux->shift = setup->bit_shift; | |
248 | ||
249 | reg->index = setup->module; | |
250 | reg->offset = setup->reg; | |
251 | ||
252 | if (setup->flags & CLKF_INDEX_STARTS_AT_ONE) | |
253 | mux->flags |= CLK_MUX_INDEX_ONE; | |
254 | ||
255 | num_parents = setup->num_parents; | |
256 | ||
257 | mux->mask = num_parents - 1; | |
258 | mux->mask = (1 << fls(mux->mask)) - 1; | |
259 | ||
260 | return &mux->hw; | |
261 | } | |
262 | ||
6a369c58 TK |
263 | static void __init of_ti_composite_mux_clk_setup(struct device_node *node) |
264 | { | |
265 | struct clk_mux *mux; | |
266 | int num_parents; | |
267 | u32 val; | |
268 | ||
269 | mux = kzalloc(sizeof(*mux), GFP_KERNEL); | |
270 | if (!mux) | |
271 | return; | |
272 | ||
273 | mux->reg = ti_clk_get_reg_addr(node, 0); | |
274 | ||
c807dbed | 275 | if (IS_ERR(mux->reg)) |
6a369c58 TK |
276 | goto cleanup; |
277 | ||
278 | if (!of_property_read_u32(node, "ti,bit-shift", &val)) | |
279 | mux->shift = val; | |
280 | ||
281 | if (of_property_read_bool(node, "ti,index-starts-at-one")) | |
282 | mux->flags |= CLK_MUX_INDEX_ONE; | |
283 | ||
284 | num_parents = of_clk_get_parent_count(node); | |
285 | ||
286 | if (num_parents < 2) { | |
287 | pr_err("%s must have parents\n", node->name); | |
288 | goto cleanup; | |
289 | } | |
290 | ||
291 | mux->mask = num_parents - 1; | |
292 | mux->mask = (1 << fls(mux->mask)) - 1; | |
293 | ||
294 | if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX)) | |
295 | return; | |
296 | ||
297 | cleanup: | |
298 | kfree(mux); | |
299 | } | |
300 | CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock", | |
301 | of_ti_composite_mux_clk_setup); |