[deliverable/linux.git] / drivers / clocksource / arm_arch_timer.c

/*
 *  linux/drivers/clocksource/arm_arch_timer.c
 *
 *  Copyright (C) 2011 ARM Ltd.
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/cpu.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
#include <linux/io.h>

#include <asm/arch_timer.h>

#include <clocksource/arm_arch_timer.h>

static u32 arch_timer_rate;

enum ppi_nr {
	PHYS_SECURE_PPI,
	PHYS_NONSECURE_PPI,
	VIRT_PPI,
	HYP_PPI,
	MAX_TIMER_PPI
};

static int arch_timer_ppi[MAX_TIMER_PPI];

static struct clock_event_device __percpu *arch_timer_evt;

static bool arch_timer_use_virtual = true;

/*
 * Architected system timer support.
 */

static inline irqreturn_t timer_handler(const int access,
					struct clock_event_device *evt)
{
	unsigned long ctrl;
	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
		evt->event_handler(evt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
}

static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
}

static inline void timer_set_mode(const int access, int mode)
{
	unsigned long ctrl;
	switch (mode) {
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
		ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
		break;
	default:
		break;
	}
}

static void arch_timer_set_mode_virt(enum clock_event_mode mode,
				     struct clock_event_device *clk)
{
	timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
}

static void arch_timer_set_mode_phys(enum clock_event_mode mode,
				     struct clock_event_device *clk)
{
	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
}

static inline void set_next_event(const int access, unsigned long evt)
{
	unsigned long ctrl;
	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
	ctrl |= ARCH_TIMER_CTRL_ENABLE;
	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
}

static int arch_timer_set_next_event_virt(unsigned long evt,
					  struct clock_event_device *unused)
{
	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
	return 0;
}

static int arch_timer_set_next_event_phys(unsigned long evt,
					  struct clock_event_device *unused)
{
	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
	return 0;
}

static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
{
	clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
	clk->name = "arch_sys_timer";
	clk->rating = 450;
	if (arch_timer_use_virtual) {
		clk->irq = arch_timer_ppi[VIRT_PPI];
		clk->set_mode = arch_timer_set_mode_virt;
		clk->set_next_event = arch_timer_set_next_event_virt;
	} else {
		clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
		clk->set_mode = arch_timer_set_mode_phys;
		clk->set_next_event = arch_timer_set_next_event_phys;
	}

	clk->cpumask = cpumask_of(smp_processor_id());

	clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);

	clockevents_config_and_register(clk, arch_timer_rate,
					0xf, 0x7fffffff);

	if (arch_timer_use_virtual)
		enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
	else {
		enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
			enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
	}

	arch_counter_set_user_access();

	return 0;
}

static int arch_timer_available(void)
{
	u32 freq;

	if (arch_timer_rate == 0) {
		freq = arch_timer_get_cntfrq();

		/* Check the timer frequency. */
		if (freq == 0) {
			pr_warn("Architected timer frequency not available\n");
			return -EINVAL;
		}

		arch_timer_rate = freq;
	}

	pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
		     (unsigned long)arch_timer_rate / 1000000,
		     (unsigned long)(arch_timer_rate / 10000) % 100,
		     arch_timer_use_virtual ? "virt" : "phys");
	return 0;
}

u32 arch_timer_get_rate(void)
{
	return arch_timer_rate;
}

/*
 * Some external users of arch_timer_read_counter (e.g. sched_clock) may try to
 * call it before it has been initialised. Rather than incur a performance
 * penalty checking for initialisation, provide a default implementation that
 * won't lead to time appearing to jump backwards.
 */
static u64 arch_timer_read_zero(void)
{
	return 0;
}

u64 (*arch_timer_read_counter)(void) = arch_timer_read_zero;

static cycle_t arch_counter_read(struct clocksource *cs)
{
	return arch_timer_read_counter();
}

static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
{
	return arch_timer_read_counter();
}

static struct clocksource clocksource_counter = {
	.name	= "arch_sys_counter",
	.rating	= 400,
	.read	= arch_counter_read,
	.mask	= CLOCKSOURCE_MASK(56),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct cyclecounter cyclecounter = {
	.read	= arch_counter_read_cc,
	.mask	= CLOCKSOURCE_MASK(56),
};

static struct timecounter timecounter;

struct timecounter *arch_timer_get_timecounter(void)
{
	return &timecounter;
}

static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
{
	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
		 clk->irq, smp_processor_id());

	if (arch_timer_use_virtual)
		disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
	else {
		disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
			disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
	}

	clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
}

static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
					   unsigned long action, void *hcpu)
{
	struct clock_event_device *evt = this_cpu_ptr(arch_timer_evt);

	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		arch_timer_setup(evt);
		break;
	case CPU_DYING:
		arch_timer_stop(evt);
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block arch_timer_cpu_nb __cpuinitdata = {
	.notifier_call = arch_timer_cpu_notify,
};

static int __init arch_timer_register(void)
{
	int err;
	int ppi;

	err = arch_timer_available();
	if (err)
		goto out;

	arch_timer_evt = alloc_percpu(struct clock_event_device);
	if (!arch_timer_evt) {
		err = -ENOMEM;
		goto out;
	}

	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
	cyclecounter.mult = clocksource_counter.mult;
	cyclecounter.shift = clocksource_counter.shift;
	timecounter_init(&timecounter, &cyclecounter,
			 arch_counter_get_cntpct());

	if (arch_timer_use_virtual) {
		ppi = arch_timer_ppi[VIRT_PPI];
		err = request_percpu_irq(ppi, arch_timer_handler_virt,
					 "arch_timer", arch_timer_evt);
	} else {
		ppi = arch_timer_ppi[PHYS_SECURE_PPI];
		err = request_percpu_irq(ppi, arch_timer_handler_phys,
					 "arch_timer", arch_timer_evt);
		if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
			ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
			err = request_percpu_irq(ppi, arch_timer_handler_phys,
						 "arch_timer", arch_timer_evt);
			if (err)
				free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
						arch_timer_evt);
		}
	}

	if (err) {
		pr_err("arch_timer: can't register interrupt %d (%d)\n",
		       ppi, err);
		goto out_free;
	}

	err = register_cpu_notifier(&arch_timer_cpu_nb);
	if (err)
		goto out_free_irq;

	/* Immediately configure the timer on the boot CPU */
	arch_timer_setup(this_cpu_ptr(arch_timer_evt));

	return 0;

out_free_irq:
	if (arch_timer_use_virtual)
		free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
	else {
		free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
				arch_timer_evt);
		if (arch_timer_ppi[PHYS_NONSECURE_PPI])
			free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
					arch_timer_evt);
	}

out_free:
	free_percpu(arch_timer_evt);
out:
	return err;
}

static const struct of_device_id arch_timer_of_match[] __initconst = {
	{ .compatible	= "arm,armv7-timer",	},
	{ .compatible	= "arm,armv8-timer",	},
	{},
};

int __init arch_timer_init(void)
{
	struct device_node *np;
	u32 freq;
	int i;

	np = of_find_matching_node(NULL, arch_timer_of_match);
	if (!np) {
		pr_err("arch_timer: can't find DT node\n");
		return -ENODEV;
	}

	/* Try to determine the frequency from the device tree or CNTFRQ */
	if (!of_property_read_u32(np, "clock-frequency", &freq))
		arch_timer_rate = freq;

	for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
		arch_timer_ppi[i] = irq_of_parse_and_map(np, i);

	of_node_put(np);

	/*
	 * If no interrupt provided for virtual timer, we'll have to
	 * stick to the physical timer. It'd better be accessible...
	 */
	if (!arch_timer_ppi[VIRT_PPI]) {
		arch_timer_use_virtual = false;

		if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
		    !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
			pr_warn("arch_timer: No interrupt available, giving up\n");
			return -EINVAL;
		}
	}

	if (arch_timer_use_virtual)
		arch_timer_read_counter = arch_counter_get_cntvct;
	else
		arch_timer_read_counter = arch_counter_get_cntpct;

	return arch_timer_register();
}
Commit	Line	Data
8a4da6e3 MR	1	/*
	2	* linux/drivers/clocksource/arm_arch_timer.c
	3	*
	4	* Copyright (C) 2011 ARM Ltd.
	5	* All Rights Reserved
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/device.h>
	14	#include <linux/smp.h>
	15	#include <linux/cpu.h>
	16	#include <linux/clockchips.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/of_irq.h>
	19	#include <linux/io.h>
	20
	21	#include <asm/arch_timer.h>
	22
	23	#include <clocksource/arm_arch_timer.h>
	24
	25	static u32 arch_timer_rate;
	26
	27	enum ppi_nr {
	28	PHYS_SECURE_PPI,
	29	PHYS_NONSECURE_PPI,
	30	VIRT_PPI,
	31	HYP_PPI,
	32	MAX_TIMER_PPI
	33	};
	34
	35	static int arch_timer_ppi[MAX_TIMER_PPI];
	36
	37	static struct clock_event_device __percpu *arch_timer_evt;
	38
	39	static bool arch_timer_use_virtual = true;
	40
	41	/*
	42	* Architected system timer support.
	43	*/
	44
	45	static inline irqreturn_t timer_handler(const int access,
	46	struct clock_event_device *evt)
	47	{
	48	unsigned long ctrl;
	49	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
	50	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
	51	ctrl \|= ARCH_TIMER_CTRL_IT_MASK;
	52	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
	53	evt->event_handler(evt);
	54	return IRQ_HANDLED;
	55	}
	56
	57	return IRQ_NONE;
	58	}
	59
	60	static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
	61	{
	62	struct clock_event_device *evt = dev_id;
	63
	64	return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
65	}
66
67	static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
68	{
69	struct clock_event_device *evt = dev_id;
70
71	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
72	}
73
74	static inline void timer_set_mode(const int access, int mode)
75	{
76	unsigned long ctrl;
77	switch (mode) {
78	case CLOCK_EVT_MODE_UNUSED:
79	case CLOCK_EVT_MODE_SHUTDOWN:
80	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
81	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
82	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
83	break;
84	default:
85	break;
86	}
87	}
88
89	static void arch_timer_set_mode_virt(enum clock_event_mode mode,
90	struct clock_event_device *clk)
91	{
92	timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
93	}
94
95	static void arch_timer_set_mode_phys(enum clock_event_mode mode,
96	struct clock_event_device *clk)
97	{
98	timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
99	}
100
101	static inline void set_next_event(const int access, unsigned long evt)
102	{
103	unsigned long ctrl;
104	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
105	ctrl \|= ARCH_TIMER_CTRL_ENABLE;
106	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
107	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
108	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
109	}
110
111	static int arch_timer_set_next_event_virt(unsigned long evt,
112	struct clock_event_device *unused)
113	{
114	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
115	return 0;
116	}
117
118	static int arch_timer_set_next_event_phys(unsigned long evt,
119	struct clock_event_device *unused)
120	{
121	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
122	return 0;
123	}
124
125	static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
126	{
127	clk->features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_C3STOP;
128	clk->name = "arch_sys_timer";
129	clk->rating = 450;
130	if (arch_timer_use_virtual) {
131	clk->irq = arch_timer_ppi[VIRT_PPI];
132	clk->set_mode = arch_timer_set_mode_virt;
133	clk->set_next_event = arch_timer_set_next_event_virt;
134	} else {
135	clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
136	clk->set_mode = arch_timer_set_mode_phys;
137	clk->set_next_event = arch_timer_set_next_event_phys;
138	}
139
140	clk->cpumask = cpumask_of(smp_processor_id());
141
142	clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
143
144	clockevents_config_and_register(clk, arch_timer_rate,
145	0xf, 0x7fffffff);
146
147	if (arch_timer_use_virtual)
148	enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
149	else {
150	enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
151	if (arch_timer_ppi[PHYS_NONSECURE_PPI])
152	enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
153	}
154
155	arch_counter_set_user_access();
156
157	return 0;
158	}
159
160	static int arch_timer_available(void)
161	{
162	u32 freq;
163
164	if (arch_timer_rate == 0) {
165	freq = arch_timer_get_cntfrq();
166
167	/* Check the timer frequency. */
168	if (freq == 0) {
169	pr_warn("Architected timer frequency not available\n");
170	return -EINVAL;
171	}
172
173	arch_timer_rate = freq;
174	}
175
176	pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
177	(unsigned long)arch_timer_rate / 1000000,
178	(unsigned long)(arch_timer_rate / 10000) % 100,
179	arch_timer_use_virtual ? "virt" : "phys");
180	return 0;
181	}
182
183	u32 arch_timer_get_rate(void)
184	{
185	return arch_timer_rate;
186	}
187
188	/*
189	* Some external users of arch_timer_read_counter (e.g. sched_clock) may try to
190	* call it before it has been initialised. Rather than incur a performance
191	* penalty checking for initialisation, provide a default implementation that
192	* won't lead to time appearing to jump backwards.
193	*/
194	static u64 arch_timer_read_zero(void)
195	{
196	return 0;
197	}
198
199	u64 (*arch_timer_read_counter)(void) = arch_timer_read_zero;
200
201	static cycle_t arch_counter_read(struct clocksource *cs)
202	{
203	return arch_timer_read_counter();
204	}
205
206	static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
207	{
208	return arch_timer_read_counter();
209	}
210
211	static struct clocksource clocksource_counter = {
212	.name = "arch_sys_counter",
213	.rating = 400,
214	.read = arch_counter_read,
215	.mask = CLOCKSOURCE_MASK(56),
216	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
217	};
218
219	static struct cyclecounter cyclecounter = {
220	.read = arch_counter_read_cc,
221	.mask = CLOCKSOURCE_MASK(56),
222	};
223
224	static struct timecounter timecounter;
225
226	struct timecounter *arch_timer_get_timecounter(void)
227	{
228	return &timecounter;
229	}
230
231	static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
232	{
233	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
234	clk->irq, smp_processor_id());
235
236	if (arch_timer_use_virtual)
237	disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
238	else {
239	disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
240	if (arch_timer_ppi[PHYS_NONSECURE_PPI])
241	disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
242	}
243
244	clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
245	}
246
247	static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
248	unsigned long action, void *hcpu)
249	{
250	struct clock_event_device *evt = this_cpu_ptr(arch_timer_evt);
251
252	switch (action & ~CPU_TASKS_FROZEN) {
253	case CPU_STARTING:
254	arch_timer_setup(evt);
255	break;
256	case CPU_DYING:
257	arch_timer_stop(evt);
258	break;
259	}
260
261	return NOTIFY_OK;
262	}
263
264	static struct notifier_block arch_timer_cpu_nb __cpuinitdata = {
265	.notifier_call = arch_timer_cpu_notify,
266	};
267
268	static int __init arch_timer_register(void)
269	{
270	int err;
271	int ppi;
272
273	err = arch_timer_available();
274	if (err)
275	goto out;
276
277	arch_timer_evt = alloc_percpu(struct clock_event_device);
278	if (!arch_timer_evt) {
279	err = -ENOMEM;
280	goto out;
281	}
282
283	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
284	cyclecounter.mult = clocksource_counter.mult;
285	cyclecounter.shift = clocksource_counter.shift;
286	timecounter_init(&timecounter, &cyclecounter,
287	arch_counter_get_cntpct());
288
289	if (arch_timer_use_virtual) {
290	ppi = arch_timer_ppi[VIRT_PPI];
291	err = request_percpu_irq(ppi, arch_timer_handler_virt,
292	"arch_timer", arch_timer_evt);
293	} else {
294	ppi = arch_timer_ppi[PHYS_SECURE_PPI];
295	err = request_percpu_irq(ppi, arch_timer_handler_phys,
296	"arch_timer", arch_timer_evt);
297	if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
298	ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
299	err = request_percpu_irq(ppi, arch_timer_handler_phys,
300	"arch_timer", arch_timer_evt);
301	if (err)
302	free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
303	arch_timer_evt);
304	}
305	}
306
307	if (err) {
308	pr_err("arch_timer: can't register interrupt %d (%d)\n",
309	ppi, err);
310	goto out_free;
311	}
312
313	err = register_cpu_notifier(&arch_timer_cpu_nb);
314	if (err)
315	goto out_free_irq;
316
317	/* Immediately configure the timer on the boot CPU */
318	arch_timer_setup(this_cpu_ptr(arch_timer_evt));
319
320	return 0;
321
322	out_free_irq:
323	if (arch_timer_use_virtual)
324	free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
325	else {
326	free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
327	arch_timer_evt);
328	if (arch_timer_ppi[PHYS_NONSECURE_PPI])
329	free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
330	arch_timer_evt);
331	}
332
333	out_free:
334	free_percpu(arch_timer_evt);
335	out:
336	return err;
337	}
338
339	static const struct of_device_id arch_timer_of_match[] __initconst = {
340	{ .compatible = "arm,armv7-timer", },
1aee5d7a	341	{ .compatible = "arm,armv8-timer", },
8a4da6e3 MR	342	{},
	343	};
	344
	345	int __init arch_timer_init(void)
	346	{
	347	struct device_node *np;
	348	u32 freq;
	349	int i;
	350
	351	np = of_find_matching_node(NULL, arch_timer_of_match);
	352	if (!np) {
	353	pr_err("arch_timer: can't find DT node\n");
	354	return -ENODEV;
	355	}
	356
	357	/* Try to determine the frequency from the device tree or CNTFRQ */
	358	if (!of_property_read_u32(np, "clock-frequency", &freq))
	359	arch_timer_rate = freq;
	360
	361	for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
	362	arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
	363
	364	of_node_put(np);
	365
	366	/*
	367	* If no interrupt provided for virtual timer, we'll have to
	368	* stick to the physical timer. It'd better be accessible...
	369	*/
	370	if (!arch_timer_ppi[VIRT_PPI]) {
	371	arch_timer_use_virtual = false;
	372
	373	if (!arch_timer_ppi[PHYS_SECURE_PPI] \|\|
	374	!arch_timer_ppi[PHYS_NONSECURE_PPI]) {
	375	pr_warn("arch_timer: No interrupt available, giving up\n");
	376	return -EINVAL;
	377	}
	378	}
	379
	380	if (arch_timer_use_virtual)
	381	arch_timer_read_counter = arch_counter_get_cntvct;
	382	else
	383	arch_timer_read_counter = arch_counter_get_cntpct;
	384
	385	return arch_timer_register();
	386	}