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8011657b CD |
1 | /* |
2 | * Copyright (C) 2012 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation version 2. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/jiffies.h> | |
18 | #include <linux/clockchips.h> | |
19 | #include <linux/types.h> | |
50ac2061 | 20 | #include <linux/clk.h> |
8011657b CD |
21 | |
22 | #include <linux/io.h> | |
8011657b CD |
23 | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_address.h> | |
26 | #include <linux/of_irq.h> | |
27 | ||
28 | ||
29 | #define KONA_GPTIMER_STCS_OFFSET 0x00000000 | |
30 | #define KONA_GPTIMER_STCLO_OFFSET 0x00000004 | |
31 | #define KONA_GPTIMER_STCHI_OFFSET 0x00000008 | |
32 | #define KONA_GPTIMER_STCM0_OFFSET 0x0000000C | |
33 | ||
34 | #define KONA_GPTIMER_STCS_TIMER_MATCH_SHIFT 0 | |
35 | #define KONA_GPTIMER_STCS_COMPARE_ENABLE_SHIFT 4 | |
36 | ||
37 | struct kona_bcm_timers { | |
38 | int tmr_irq; | |
39 | void __iomem *tmr_regs; | |
40 | }; | |
41 | ||
42 | static struct kona_bcm_timers timers; | |
43 | ||
44 | static u32 arch_timer_rate; | |
45 | ||
46 | /* | |
47 | * We use the peripheral timers for system tick, the cpu global timer for | |
48 | * profile tick | |
49 | */ | |
50 | static void kona_timer_disable_and_clear(void __iomem *base) | |
51 | { | |
52 | uint32_t reg; | |
53 | ||
54 | /* | |
55 | * clear and disable interrupts | |
56 | * We are using compare/match register 0 for our system interrupts | |
57 | */ | |
58 | reg = readl(base + KONA_GPTIMER_STCS_OFFSET); | |
59 | ||
60 | /* Clear compare (0) interrupt */ | |
61 | reg |= 1 << KONA_GPTIMER_STCS_TIMER_MATCH_SHIFT; | |
62 | /* disable compare */ | |
63 | reg &= ~(1 << KONA_GPTIMER_STCS_COMPARE_ENABLE_SHIFT); | |
64 | ||
65 | writel(reg, base + KONA_GPTIMER_STCS_OFFSET); | |
66 | ||
67 | } | |
68 | ||
69 | static void | |
ff4bcc84 | 70 | kona_timer_get_counter(void __iomem *timer_base, uint32_t *msw, uint32_t *lsw) |
8011657b | 71 | { |
8011657b CD |
72 | int loop_limit = 4; |
73 | ||
74 | /* | |
75 | * Read 64-bit free running counter | |
76 | * 1. Read hi-word | |
77 | * 2. Read low-word | |
78 | * 3. Read hi-word again | |
79 | * 4.1 | |
80 | * if new hi-word is not equal to previously read hi-word, then | |
81 | * start from #1 | |
82 | * 4.2 | |
83 | * if new hi-word is equal to previously read hi-word then stop. | |
84 | */ | |
85 | ||
86 | while (--loop_limit) { | |
ff4bcc84 OJ |
87 | *msw = readl(timer_base + KONA_GPTIMER_STCHI_OFFSET); |
88 | *lsw = readl(timer_base + KONA_GPTIMER_STCLO_OFFSET); | |
89 | if (*msw == readl(timer_base + KONA_GPTIMER_STCHI_OFFSET)) | |
8011657b CD |
90 | break; |
91 | } | |
92 | if (!loop_limit) { | |
93 | pr_err("bcm_kona_timer: getting counter failed.\n"); | |
94 | pr_err(" Timer will be impacted\n"); | |
95 | } | |
96 | ||
97 | return; | |
98 | } | |
99 | ||
8011657b CD |
100 | static int kona_timer_set_next_event(unsigned long clc, |
101 | struct clock_event_device *unused) | |
102 | { | |
103 | /* | |
104 | * timer (0) is disabled by the timer interrupt already | |
105 | * so, here we reload the next event value and re-enable | |
106 | * the timer. | |
107 | * | |
108 | * This way, we are potentially losing the time between | |
109 | * timer-interrupt->set_next_event. CPU local timers, when | |
110 | * they come in should get rid of skew. | |
111 | */ | |
112 | ||
113 | uint32_t lsw, msw; | |
114 | uint32_t reg; | |
115 | ||
116 | kona_timer_get_counter(timers.tmr_regs, &msw, &lsw); | |
117 | ||
118 | /* Load the "next" event tick value */ | |
119 | writel(lsw + clc, timers.tmr_regs + KONA_GPTIMER_STCM0_OFFSET); | |
120 | ||
121 | /* Enable compare */ | |
122 | reg = readl(timers.tmr_regs + KONA_GPTIMER_STCS_OFFSET); | |
123 | reg |= (1 << KONA_GPTIMER_STCS_COMPARE_ENABLE_SHIFT); | |
124 | writel(reg, timers.tmr_regs + KONA_GPTIMER_STCS_OFFSET); | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
b4cf5d71 | 129 | static int kona_timer_shutdown(struct clock_event_device *evt) |
8011657b | 130 | { |
b4cf5d71 VK |
131 | kona_timer_disable_and_clear(timers.tmr_regs); |
132 | return 0; | |
8011657b CD |
133 | } |
134 | ||
135 | static struct clock_event_device kona_clockevent_timer = { | |
136 | .name = "timer 1", | |
137 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
138 | .set_next_event = kona_timer_set_next_event, | |
b4cf5d71 VK |
139 | .set_state_shutdown = kona_timer_shutdown, |
140 | .tick_resume = kona_timer_shutdown, | |
8011657b CD |
141 | }; |
142 | ||
143 | static void __init kona_timer_clockevents_init(void) | |
144 | { | |
145 | kona_clockevent_timer.cpumask = cpumask_of(0); | |
146 | clockevents_config_and_register(&kona_clockevent_timer, | |
147 | arch_timer_rate, 6, 0xffffffff); | |
148 | } | |
149 | ||
150 | static irqreturn_t kona_timer_interrupt(int irq, void *dev_id) | |
151 | { | |
152 | struct clock_event_device *evt = &kona_clockevent_timer; | |
153 | ||
154 | kona_timer_disable_and_clear(timers.tmr_regs); | |
155 | evt->event_handler(evt); | |
156 | return IRQ_HANDLED; | |
157 | } | |
158 | ||
159 | static struct irqaction kona_timer_irq = { | |
160 | .name = "Kona Timer Tick", | |
161 | .flags = IRQF_TIMER, | |
162 | .handler = kona_timer_interrupt, | |
163 | }; | |
164 | ||
59519774 | 165 | static int __init kona_timer_init(struct device_node *node) |
8011657b | 166 | { |
ad037c1f TK |
167 | u32 freq; |
168 | struct clk *external_clk; | |
169 | ||
ad037c1f TK |
170 | external_clk = of_clk_get_by_name(node, NULL); |
171 | ||
172 | if (!IS_ERR(external_clk)) { | |
173 | arch_timer_rate = clk_get_rate(external_clk); | |
174 | clk_prepare_enable(external_clk); | |
175 | } else if (!of_property_read_u32(node, "clock-frequency", &freq)) { | |
176 | arch_timer_rate = freq; | |
177 | } else { | |
178 | pr_err("Kona Timer v1 unable to determine clock-frequency"); | |
59519774 | 179 | return -EINVAL; |
ad037c1f TK |
180 | } |
181 | ||
182 | /* Setup IRQ numbers */ | |
183 | timers.tmr_irq = irq_of_parse_and_map(node, 0); | |
184 | ||
185 | /* Setup IO addresses */ | |
186 | timers.tmr_regs = of_iomap(node, 0); | |
187 | ||
188 | kona_timer_disable_and_clear(timers.tmr_regs); | |
189 | ||
8011657b CD |
190 | kona_timer_clockevents_init(); |
191 | setup_irq(timers.tmr_irq, &kona_timer_irq); | |
192 | kona_timer_set_next_event((arch_timer_rate / HZ), NULL); | |
59519774 DL |
193 | |
194 | return 0; | |
8011657b CD |
195 | } |
196 | ||
177cf6e5 | 197 | CLOCKSOURCE_OF_DECLARE(brcm_kona, "brcm,kona-timer", kona_timer_init); |
aea237bf CD |
198 | /* |
199 | * bcm,kona-timer is deprecated by brcm,kona-timer | |
200 | * being kept here for driver compatibility | |
201 | */ | |
177cf6e5 | 202 | CLOCKSOURCE_OF_DECLARE(bcm_kona, "bcm,kona-timer", kona_timer_init); |