Commit | Line | Data |
---|---|---|
b85a3ef4 | 1 | /* |
9e09dc5f | 2 | * This file contains driver for the Cadence Triple Timer Counter Rev 06 |
b85a3ef4 | 3 | * |
e932900a | 4 | * Copyright (C) 2011-2013 Xilinx |
b85a3ef4 JL |
5 | * |
6 | * based on arch/mips/kernel/time.c timer driver | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
e932900a | 18 | #include <linux/clk.h> |
b85a3ef4 | 19 | #include <linux/interrupt.h> |
b85a3ef4 | 20 | #include <linux/clockchips.h> |
91dc985c JC |
21 | #include <linux/of_address.h> |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/slab.h> | |
3d77b30e | 24 | #include <linux/sched_clock.h> |
b85a3ef4 | 25 | |
e932900a MS |
26 | /* |
27 | * This driver configures the 2 16-bit count-up timers as follows: | |
28 | * | |
29 | * T1: Timer 1, clocksource for generic timekeeping | |
30 | * T2: Timer 2, clockevent source for hrtimers | |
31 | * T3: Timer 3, <unused> | |
32 | * | |
33 | * The input frequency to the timer module for emulation is 2.5MHz which is | |
34 | * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, | |
35 | * the timers are clocked at 78.125KHz (12.8 us resolution). | |
36 | ||
37 | * The input frequency to the timer module in silicon is configurable and | |
38 | * obtained from device tree. The pre-scaler of 32 is used. | |
39 | */ | |
40 | ||
b85a3ef4 JL |
41 | /* |
42 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 | |
43 | * and use same offsets for Timer 2 | |
44 | */ | |
9e09dc5f MS |
45 | #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ |
46 | #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ | |
47 | #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ | |
48 | #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ | |
49 | #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ | |
50 | #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ | |
f184c5ca | 51 | |
9e09dc5f | 52 | #define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
b85a3ef4 | 53 | |
30e1e285 SB |
54 | #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ |
55 | ||
03377e58 SB |
56 | /* |
57 | * Setup the timers to use pre-scaling, using a fixed value for now that will | |
91dc985c JC |
58 | * work across most input frequency, but it may need to be more dynamic |
59 | */ | |
60 | #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ | |
61 | #define PRESCALE 2048 /* The exponent must match this */ | |
62 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) | |
63 | #define CLK_CNTRL_PRESCALE_EN 1 | |
e932900a | 64 | #define CNT_CNTRL_RESET (1 << 4) |
b85a3ef4 JL |
65 | |
66 | /** | |
9e09dc5f | 67 | * struct ttc_timer - This definition defines local timer structure |
b85a3ef4 JL |
68 | * |
69 | * @base_addr: Base address of timer | |
e932900a MS |
70 | * @clk: Associated clock source |
71 | * @clk_rate_change_nb Notifier block for clock rate changes | |
72 | */ | |
9e09dc5f | 73 | struct ttc_timer { |
e932900a MS |
74 | void __iomem *base_addr; |
75 | struct clk *clk; | |
76 | struct notifier_block clk_rate_change_nb; | |
91dc985c JC |
77 | }; |
78 | ||
9e09dc5f MS |
79 | #define to_ttc_timer(x) \ |
80 | container_of(x, struct ttc_timer, clk_rate_change_nb) | |
e932900a | 81 | |
9e09dc5f MS |
82 | struct ttc_timer_clocksource { |
83 | struct ttc_timer ttc; | |
91dc985c | 84 | struct clocksource cs; |
b85a3ef4 JL |
85 | }; |
86 | ||
9e09dc5f MS |
87 | #define to_ttc_timer_clksrc(x) \ |
88 | container_of(x, struct ttc_timer_clocksource, cs) | |
91dc985c | 89 | |
9e09dc5f MS |
90 | struct ttc_timer_clockevent { |
91 | struct ttc_timer ttc; | |
91dc985c | 92 | struct clock_event_device ce; |
91dc985c JC |
93 | }; |
94 | ||
9e09dc5f MS |
95 | #define to_ttc_timer_clkevent(x) \ |
96 | container_of(x, struct ttc_timer_clockevent, ce) | |
b85a3ef4 | 97 | |
3d77b30e SB |
98 | static void __iomem *ttc_sched_clock_val_reg; |
99 | ||
b85a3ef4 | 100 | /** |
9e09dc5f | 101 | * ttc_set_interval - Set the timer interval value |
b85a3ef4 JL |
102 | * |
103 | * @timer: Pointer to the timer instance | |
104 | * @cycles: Timer interval ticks | |
105 | **/ | |
9e09dc5f | 106 | static void ttc_set_interval(struct ttc_timer *timer, |
b85a3ef4 JL |
107 | unsigned long cycles) |
108 | { | |
109 | u32 ctrl_reg; | |
110 | ||
111 | /* Disable the counter, set the counter value and re-enable counter */ | |
9e09dc5f MS |
112 | ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
113 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; | |
114 | __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
b85a3ef4 | 115 | |
9e09dc5f | 116 | __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
b85a3ef4 | 117 | |
03377e58 SB |
118 | /* |
119 | * Reset the counter (0x10) so that it starts from 0, one-shot | |
120 | * mode makes this needed for timing to be right. | |
121 | */ | |
91dc985c | 122 | ctrl_reg |= CNT_CNTRL_RESET; |
9e09dc5f MS |
123 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
124 | __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); | |
b85a3ef4 JL |
125 | } |
126 | ||
127 | /** | |
9e09dc5f | 128 | * ttc_clock_event_interrupt - Clock event timer interrupt handler |
b85a3ef4 JL |
129 | * |
130 | * @irq: IRQ number of the Timer | |
9e09dc5f | 131 | * @dev_id: void pointer to the ttc_timer instance |
b85a3ef4 JL |
132 | * |
133 | * returns: Always IRQ_HANDLED - success | |
134 | **/ | |
9e09dc5f | 135 | static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
b85a3ef4 | 136 | { |
9e09dc5f MS |
137 | struct ttc_timer_clockevent *ttce = dev_id; |
138 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
139 | |
140 | /* Acknowledge the interrupt and call event handler */ | |
9e09dc5f | 141 | __raw_readl(timer->base_addr + TTC_ISR_OFFSET); |
b85a3ef4 | 142 | |
9e09dc5f | 143 | ttce->ce.event_handler(&ttce->ce); |
b85a3ef4 JL |
144 | |
145 | return IRQ_HANDLED; | |
146 | } | |
147 | ||
b85a3ef4 | 148 | /** |
9e09dc5f | 149 | * __ttc_clocksource_read - Reads the timer counter register |
b85a3ef4 JL |
150 | * |
151 | * returns: Current timer counter register value | |
152 | **/ | |
9e09dc5f | 153 | static cycle_t __ttc_clocksource_read(struct clocksource *cs) |
b85a3ef4 | 154 | { |
9e09dc5f | 155 | struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
b85a3ef4 JL |
156 | |
157 | return (cycle_t)__raw_readl(timer->base_addr + | |
9e09dc5f | 158 | TTC_COUNT_VAL_OFFSET); |
b85a3ef4 JL |
159 | } |
160 | ||
3d77b30e SB |
161 | static u32 notrace ttc_sched_clock_read(void) |
162 | { | |
163 | return __raw_readl(ttc_sched_clock_val_reg); | |
164 | } | |
165 | ||
b85a3ef4 | 166 | /** |
9e09dc5f | 167 | * ttc_set_next_event - Sets the time interval for next event |
b85a3ef4 JL |
168 | * |
169 | * @cycles: Timer interval ticks | |
170 | * @evt: Address of clock event instance | |
171 | * | |
172 | * returns: Always 0 - success | |
173 | **/ | |
9e09dc5f | 174 | static int ttc_set_next_event(unsigned long cycles, |
b85a3ef4 JL |
175 | struct clock_event_device *evt) |
176 | { | |
9e09dc5f MS |
177 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
178 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 | 179 | |
9e09dc5f | 180 | ttc_set_interval(timer, cycles); |
b85a3ef4 JL |
181 | return 0; |
182 | } | |
183 | ||
184 | /** | |
9e09dc5f | 185 | * ttc_set_mode - Sets the mode of timer |
b85a3ef4 JL |
186 | * |
187 | * @mode: Mode to be set | |
188 | * @evt: Address of clock event instance | |
189 | **/ | |
9e09dc5f | 190 | static void ttc_set_mode(enum clock_event_mode mode, |
b85a3ef4 JL |
191 | struct clock_event_device *evt) |
192 | { | |
9e09dc5f MS |
193 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
194 | struct ttc_timer *timer = &ttce->ttc; | |
b85a3ef4 JL |
195 | u32 ctrl_reg; |
196 | ||
197 | switch (mode) { | |
198 | case CLOCK_EVT_MODE_PERIODIC: | |
9e09dc5f MS |
199 | ttc_set_interval(timer, |
200 | DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk), | |
e932900a | 201 | PRESCALE * HZ)); |
b85a3ef4 JL |
202 | break; |
203 | case CLOCK_EVT_MODE_ONESHOT: | |
204 | case CLOCK_EVT_MODE_UNUSED: | |
205 | case CLOCK_EVT_MODE_SHUTDOWN: | |
206 | ctrl_reg = __raw_readl(timer->base_addr + | |
9e09dc5f MS |
207 | TTC_CNT_CNTRL_OFFSET); |
208 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; | |
b85a3ef4 | 209 | __raw_writel(ctrl_reg, |
9e09dc5f | 210 | timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 JL |
211 | break; |
212 | case CLOCK_EVT_MODE_RESUME: | |
213 | ctrl_reg = __raw_readl(timer->base_addr + | |
9e09dc5f MS |
214 | TTC_CNT_CNTRL_OFFSET); |
215 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; | |
b85a3ef4 | 216 | __raw_writel(ctrl_reg, |
9e09dc5f | 217 | timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4 JL |
218 | break; |
219 | } | |
220 | } | |
221 | ||
9e09dc5f | 222 | static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
e932900a MS |
223 | unsigned long event, void *data) |
224 | { | |
225 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
226 | struct ttc_timer *ttc = to_ttc_timer(nb); |
227 | struct ttc_timer_clocksource *ttccs = container_of(ttc, | |
228 | struct ttc_timer_clocksource, ttc); | |
e932900a MS |
229 | |
230 | switch (event) { | |
231 | case POST_RATE_CHANGE: | |
232 | /* | |
233 | * Do whatever is necessary to maintain a proper time base | |
234 | * | |
235 | * I cannot find a way to adjust the currently used clocksource | |
236 | * to the new frequency. __clocksource_updatefreq_hz() sounds | |
237 | * good, but does not work. Not sure what's that missing. | |
238 | * | |
239 | * This approach works, but triggers two clocksource switches. | |
240 | * The first after unregister to clocksource jiffies. And | |
241 | * another one after the register to the newly registered timer. | |
242 | * | |
243 | * Alternatively we could 'waste' another HW timer to ping pong | |
244 | * between clock sources. That would also use one register and | |
245 | * one unregister call, but only trigger one clocksource switch | |
246 | * for the cost of another HW timer used by the OS. | |
247 | */ | |
9e09dc5f MS |
248 | clocksource_unregister(&ttccs->cs); |
249 | clocksource_register_hz(&ttccs->cs, | |
e932900a MS |
250 | ndata->new_rate / PRESCALE); |
251 | /* fall through */ | |
252 | case PRE_RATE_CHANGE: | |
253 | case ABORT_RATE_CHANGE: | |
254 | default: | |
255 | return NOTIFY_DONE; | |
256 | } | |
257 | } | |
258 | ||
9e09dc5f | 259 | static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) |
91dc985c | 260 | { |
9e09dc5f | 261 | struct ttc_timer_clocksource *ttccs; |
91dc985c | 262 | int err; |
91dc985c JC |
263 | |
264 | ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); | |
265 | if (WARN_ON(!ttccs)) | |
266 | return; | |
267 | ||
9e09dc5f | 268 | ttccs->ttc.clk = clk; |
91dc985c | 269 | |
9e09dc5f | 270 | err = clk_prepare_enable(ttccs->ttc.clk); |
c5263bb8 MS |
271 | if (WARN_ON(err)) { |
272 | kfree(ttccs); | |
91dc985c | 273 | return; |
c5263bb8 | 274 | } |
91dc985c | 275 | |
9e09dc5f MS |
276 | ttccs->ttc.clk_rate_change_nb.notifier_call = |
277 | ttc_rate_change_clocksource_cb; | |
278 | ttccs->ttc.clk_rate_change_nb.next = NULL; | |
279 | if (clk_notifier_register(ttccs->ttc.clk, | |
280 | &ttccs->ttc.clk_rate_change_nb)) | |
e932900a | 281 | pr_warn("Unable to register clock notifier.\n"); |
91dc985c | 282 | |
9e09dc5f MS |
283 | ttccs->ttc.base_addr = base; |
284 | ttccs->cs.name = "ttc_clocksource"; | |
91dc985c | 285 | ttccs->cs.rating = 200; |
9e09dc5f | 286 | ttccs->cs.read = __ttc_clocksource_read; |
91dc985c JC |
287 | ttccs->cs.mask = CLOCKSOURCE_MASK(16); |
288 | ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
289 | ||
e932900a MS |
290 | /* |
291 | * Setup the clock source counter to be an incrementing counter | |
292 | * with no interrupt and it rolls over at 0xFFFF. Pre-scale | |
293 | * it by 32 also. Let it start running now. | |
294 | */ | |
9e09dc5f | 295 | __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); |
91dc985c | 296 | __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f | 297 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
91dc985c | 298 | __raw_writel(CNT_CNTRL_RESET, |
9e09dc5f | 299 | ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c | 300 | |
e932900a | 301 | err = clocksource_register_hz(&ttccs->cs, |
9e09dc5f | 302 | clk_get_rate(ttccs->ttc.clk) / PRESCALE); |
c5263bb8 MS |
303 | if (WARN_ON(err)) { |
304 | kfree(ttccs); | |
91dc985c | 305 | return; |
c5263bb8 | 306 | } |
3d77b30e SB |
307 | |
308 | ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; | |
309 | setup_sched_clock(ttc_sched_clock_read, 16, | |
310 | clk_get_rate(ttccs->ttc.clk) / PRESCALE); | |
91dc985c JC |
311 | } |
312 | ||
9e09dc5f | 313 | static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
e932900a MS |
314 | unsigned long event, void *data) |
315 | { | |
316 | struct clk_notifier_data *ndata = data; | |
9e09dc5f MS |
317 | struct ttc_timer *ttc = to_ttc_timer(nb); |
318 | struct ttc_timer_clockevent *ttcce = container_of(ttc, | |
319 | struct ttc_timer_clockevent, ttc); | |
e932900a MS |
320 | |
321 | switch (event) { | |
322 | case POST_RATE_CHANGE: | |
323 | { | |
324 | unsigned long flags; | |
325 | ||
326 | /* | |
327 | * clockevents_update_freq should be called with IRQ disabled on | |
328 | * the CPU the timer provides events for. The timer we use is | |
329 | * common to both CPUs, not sure if we need to run on both | |
330 | * cores. | |
331 | */ | |
332 | local_irq_save(flags); | |
9e09dc5f | 333 | clockevents_update_freq(&ttcce->ce, |
e932900a MS |
334 | ndata->new_rate / PRESCALE); |
335 | local_irq_restore(flags); | |
336 | ||
337 | /* fall through */ | |
338 | } | |
339 | case PRE_RATE_CHANGE: | |
340 | case ABORT_RATE_CHANGE: | |
341 | default: | |
342 | return NOTIFY_DONE; | |
343 | } | |
344 | } | |
345 | ||
9e09dc5f | 346 | static void __init ttc_setup_clockevent(struct clk *clk, |
e932900a | 347 | void __iomem *base, u32 irq) |
91dc985c | 348 | { |
9e09dc5f | 349 | struct ttc_timer_clockevent *ttcce; |
e932900a | 350 | int err; |
91dc985c JC |
351 | |
352 | ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); | |
353 | if (WARN_ON(!ttcce)) | |
354 | return; | |
355 | ||
9e09dc5f | 356 | ttcce->ttc.clk = clk; |
91dc985c | 357 | |
9e09dc5f | 358 | err = clk_prepare_enable(ttcce->ttc.clk); |
c5263bb8 MS |
359 | if (WARN_ON(err)) { |
360 | kfree(ttcce); | |
91dc985c | 361 | return; |
c5263bb8 | 362 | } |
91dc985c | 363 | |
9e09dc5f MS |
364 | ttcce->ttc.clk_rate_change_nb.notifier_call = |
365 | ttc_rate_change_clockevent_cb; | |
366 | ttcce->ttc.clk_rate_change_nb.next = NULL; | |
367 | if (clk_notifier_register(ttcce->ttc.clk, | |
368 | &ttcce->ttc.clk_rate_change_nb)) | |
e932900a | 369 | pr_warn("Unable to register clock notifier.\n"); |
91dc985c | 370 | |
9e09dc5f MS |
371 | ttcce->ttc.base_addr = base; |
372 | ttcce->ce.name = "ttc_clockevent"; | |
91dc985c | 373 | ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
9e09dc5f MS |
374 | ttcce->ce.set_next_event = ttc_set_next_event; |
375 | ttcce->ce.set_mode = ttc_set_mode; | |
91dc985c JC |
376 | ttcce->ce.rating = 200; |
377 | ttcce->ce.irq = irq; | |
87e4ee75 | 378 | ttcce->ce.cpumask = cpu_possible_mask; |
91dc985c | 379 | |
e932900a MS |
380 | /* |
381 | * Setup the clock event timer to be an interval timer which | |
382 | * is prescaled by 32 using the interval interrupt. Leave it | |
383 | * disabled for now. | |
384 | */ | |
9e09dc5f | 385 | __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c | 386 | __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f MS |
387 | ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
388 | __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); | |
91dc985c | 389 | |
9e09dc5f | 390 | err = request_irq(irq, ttc_clock_event_interrupt, |
e932900a MS |
391 | IRQF_DISABLED | IRQF_TIMER, |
392 | ttcce->ce.name, ttcce); | |
c5263bb8 MS |
393 | if (WARN_ON(err)) { |
394 | kfree(ttcce); | |
91dc985c | 395 | return; |
c5263bb8 | 396 | } |
91dc985c JC |
397 | |
398 | clockevents_config_and_register(&ttcce->ce, | |
9e09dc5f | 399 | clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe); |
91dc985c JC |
400 | } |
401 | ||
b85a3ef4 | 402 | /** |
9e09dc5f | 403 | * ttc_timer_init - Initialize the timer |
b85a3ef4 JL |
404 | * |
405 | * Initializes the timer hardware and register the clock source and clock event | |
406 | * timers with Linux kernal timer framework | |
e932900a | 407 | */ |
9e09dc5f | 408 | static void __init ttc_timer_init(struct device_node *timer) |
e932900a MS |
409 | { |
410 | unsigned int irq; | |
411 | void __iomem *timer_baseaddr; | |
30e1e285 | 412 | struct clk *clk_cs, *clk_ce; |
c5263bb8 | 413 | static int initialized; |
30e1e285 | 414 | int clksel; |
c5263bb8 MS |
415 | |
416 | if (initialized) | |
417 | return; | |
418 | ||
419 | initialized = 1; | |
e932900a MS |
420 | |
421 | /* | |
422 | * Get the 1st Triple Timer Counter (TTC) block from the device tree | |
423 | * and use it. Note that the event timer uses the interrupt and it's the | |
424 | * 2nd TTC hence the irq_of_parse_and_map(,1) | |
425 | */ | |
426 | timer_baseaddr = of_iomap(timer, 0); | |
427 | if (!timer_baseaddr) { | |
428 | pr_err("ERROR: invalid timer base address\n"); | |
429 | BUG(); | |
430 | } | |
431 | ||
432 | irq = irq_of_parse_and_map(timer, 1); | |
433 | if (irq <= 0) { | |
434 | pr_err("ERROR: invalid interrupt number\n"); | |
435 | BUG(); | |
436 | } | |
437 | ||
30e1e285 SB |
438 | clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); |
439 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); | |
440 | clk_cs = of_clk_get(timer, clksel); | |
441 | if (IS_ERR(clk_cs)) { | |
442 | pr_err("ERROR: timer input clock not found\n"); | |
443 | BUG(); | |
444 | } | |
445 | ||
446 | clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); | |
447 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); | |
448 | clk_ce = of_clk_get(timer, clksel); | |
449 | if (IS_ERR(clk_ce)) { | |
e932900a MS |
450 | pr_err("ERROR: timer input clock not found\n"); |
451 | BUG(); | |
452 | } | |
453 | ||
30e1e285 SB |
454 | ttc_setup_clocksource(clk_cs, timer_baseaddr); |
455 | ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); | |
e932900a MS |
456 | |
457 | pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); | |
458 | } | |
459 | ||
9e09dc5f | 460 | CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |