[deliverable/linux.git] / drivers / clocksource / cadence_ttc_timer.c

/*
 * This file contains driver for the Cadence Triple Timer Counter Rev 06
 *
 *  Copyright (C) 2011-2013 Xilinx
 *
 * based on arch/mips/kernel/time.c timer driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk-provider.h>

/*
 * This driver configures the 2 16-bit count-up timers as follows:
 *
 * T1: Timer 1, clocksource for generic timekeeping
 * T2: Timer 2, clockevent source for hrtimers
 * T3: Timer 3, <unused>
 *
 * The input frequency to the timer module for emulation is 2.5MHz which is
 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
 * the timers are clocked at 78.125KHz (12.8 us resolution).

 * The input frequency to the timer module in silicon is configurable and
 * obtained from device tree. The pre-scaler of 32 is used.
 */

/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
#define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
#define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
#define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
#define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */

#define TTC_CNT_CNTRL_DISABLE_MASK	0x1

#define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */

/*
 * Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
#define CNT_CNTRL_RESET		(1 << 4)

/**
 * struct ttc_timer - This definition defines local timer structure
 *
 * @base_addr:	Base address of timer
 * @clk:	Associated clock source
 * @clk_rate_change_nb	Notifier block for clock rate changes
 */
struct ttc_timer {
	void __iomem *base_addr;
	struct clk *clk;
	struct notifier_block clk_rate_change_nb;
};

#define to_ttc_timer(x) \
		container_of(x, struct ttc_timer, clk_rate_change_nb)

struct ttc_timer_clocksource {
	struct ttc_timer	ttc;
	struct clocksource	cs;
};

#define to_ttc_timer_clksrc(x) \
		container_of(x, struct ttc_timer_clocksource, cs)

struct ttc_timer_clockevent {
	struct ttc_timer		ttc;
	struct clock_event_device	ce;
};

#define to_ttc_timer_clkevent(x) \
		container_of(x, struct ttc_timer_clockevent, ce)

/**
 * ttc_set_interval - Set the timer interval value
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
static void ttc_set_interval(struct ttc_timer *timer,
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
	ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);

	__raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);

	/*
	 * Reset the counter (0x10) so that it starts from 0, one-shot
	 * mode makes this needed for timing to be right.
	 */
	ctrl_reg |= CNT_CNTRL_RESET;
	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
}

/**
 * ttc_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the ttc_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
{
	struct ttc_timer_clockevent *ttce = dev_id;
	struct ttc_timer *timer = &ttce->ttc;

	/* Acknowledge the interrupt and call event handler */
	__raw_readl(timer->base_addr + TTC_ISR_OFFSET);

	ttce->ce.event_handler(&ttce->ce);

	return IRQ_HANDLED;
}

/**
 * __ttc_clocksource_read - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
static cycle_t __ttc_clocksource_read(struct clocksource *cs)
{
	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;

	return (cycle_t)__raw_readl(timer->base_addr +
				TTC_COUNT_VAL_OFFSET);
}

/**
 * ttc_set_next_event - Sets the time interval for next event
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
static int ttc_set_next_event(unsigned long cycles,
					struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;

	ttc_set_interval(timer, cycles);
	return 0;
}

/**
 * ttc_set_mode - Sets the mode of timer
 *
 * @mode:	Mode to be set
 * @evt:	Address of clock event instance
 **/
static void ttc_set_mode(enum clock_event_mode mode,
					struct clock_event_device *evt)
{
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
	u32 ctrl_reg;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		ttc_set_interval(timer,
				DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk),
					PRESCALE * HZ));
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl_reg = __raw_readl(timer->base_addr +
					TTC_CNT_CNTRL_OFFSET);
		ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + TTC_CNT_CNTRL_OFFSET);
		break;
	case CLOCK_EVT_MODE_RESUME:
		ctrl_reg = __raw_readl(timer->base_addr +
					TTC_CNT_CNTRL_OFFSET);
		ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + TTC_CNT_CNTRL_OFFSET);
		break;
	}
}

static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clocksource *ttccs = container_of(ttc,
			struct ttc_timer_clocksource, ttc);

	switch (event) {
	case POST_RATE_CHANGE:
		/*
		 * Do whatever is necessary to maintain a proper time base
		 *
		 * I cannot find a way to adjust the currently used clocksource
		 * to the new frequency. __clocksource_updatefreq_hz() sounds
		 * good, but does not work. Not sure what's that missing.
		 *
		 * This approach works, but triggers two clocksource switches.
		 * The first after unregister to clocksource jiffies. And
		 * another one after the register to the newly registered timer.
		 *
		 * Alternatively we could 'waste' another HW timer to ping pong
		 * between clock sources. That would also use one register and
		 * one unregister call, but only trigger one clocksource switch
		 * for the cost of another HW timer used by the OS.
		 */
		clocksource_unregister(&ttccs->cs);
		clocksource_register_hz(&ttccs->cs,
				ndata->new_rate / PRESCALE);
		/* fall through */
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
{
	struct ttc_timer_clocksource *ttccs;
	int err;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (WARN_ON(!ttccs))
		return;

	ttccs->ttc.clk = clk;

	err = clk_prepare_enable(ttccs->ttc.clk);
	if (WARN_ON(err)) {
		kfree(ttccs);
		return;
	}

	ttccs->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clocksource_cb;
	ttccs->ttc.clk_rate_change_nb.next = NULL;
	if (clk_notifier_register(ttccs->ttc.clk,
				&ttccs->ttc.clk_rate_change_nb))
		pr_warn("Unable to register clock notifier.\n");

	ttccs->ttc.base_addr = base;
	ttccs->cs.name = "ttc_clocksource";
	ttccs->cs.rating = 200;
	ttccs->cs.read = __ttc_clocksource_read;
	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	/*
	 * Setup the clock source counter to be an incrementing counter
	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
	 * it by 32 also. Let it start running now.
	 */
	__raw_writel(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	__raw_writel(CNT_CNTRL_RESET,
		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);

	err = clocksource_register_hz(&ttccs->cs,
			clk_get_rate(ttccs->ttc.clk) / PRESCALE);
	if (WARN_ON(err)) {
		kfree(ttccs);
		return;
	}
}

static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clockevent *ttcce = container_of(ttc,
			struct ttc_timer_clockevent, ttc);

	switch (event) {
	case POST_RATE_CHANGE:
	{
		unsigned long flags;

		/*
		 * clockevents_update_freq should be called with IRQ disabled on
		 * the CPU the timer provides events for. The timer we use is
		 * common to both CPUs, not sure if we need to run on both
		 * cores.
		 */
		local_irq_save(flags);
		clockevents_update_freq(&ttcce->ce,
				ndata->new_rate / PRESCALE);
		local_irq_restore(flags);

		/* fall through */
	}
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

static void __init ttc_setup_clockevent(struct clk *clk,
						void __iomem *base, u32 irq)
{
	struct ttc_timer_clockevent *ttcce;
	int err;

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (WARN_ON(!ttcce))
		return;

	ttcce->ttc.clk = clk;

	err = clk_prepare_enable(ttcce->ttc.clk);
	if (WARN_ON(err)) {
		kfree(ttcce);
		return;
	}

	ttcce->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clockevent_cb;
	ttcce->ttc.clk_rate_change_nb.next = NULL;
	if (clk_notifier_register(ttcce->ttc.clk,
				&ttcce->ttc.clk_rate_change_nb))
		pr_warn("Unable to register clock notifier.\n");

	ttcce->ttc.base_addr = base;
	ttcce->ce.name = "ttc_clockevent";
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ttcce->ce.set_next_event = ttc_set_next_event;
	ttcce->ce.set_mode = ttc_set_mode;
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;
	ttcce->ce.cpumask = cpu_possible_mask;

	/*
	 * Setup the clock event timer to be an interval timer which
	 * is prescaled by 32 using the interval interrupt. Leave it
	 * disabled for now.
	 */
	__raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	__raw_writel(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);

	err = request_irq(irq, ttc_clock_event_interrupt,
			  IRQF_DISABLED | IRQF_TIMER,
			  ttcce->ce.name, ttcce);
	if (WARN_ON(err)) {
		kfree(ttcce);
		return;
	}

	clockevents_config_and_register(&ttcce->ce,
			clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe);
}

/**
 * ttc_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 */
static void __init ttc_timer_init(struct device_node *timer)
{
	unsigned int irq;
	void __iomem *timer_baseaddr;
	struct clk *clk_cs, *clk_ce;
	static int initialized;
	int clksel;

	if (initialized)
		return;

	initialized = 1;

	/*
	 * Get the 1st Triple Timer Counter (TTC) block from the device tree
	 * and use it. Note that the event timer uses the interrupt and it's the
	 * 2nd TTC hence the irq_of_parse_and_map(,1)
	 */
	timer_baseaddr = of_iomap(timer, 0);
	if (!timer_baseaddr) {
		pr_err("ERROR: invalid timer base address\n");
		BUG();
	}

	irq = irq_of_parse_and_map(timer, 1);
	if (irq <= 0) {
		pr_err("ERROR: invalid interrupt number\n");
		BUG();
	}

	clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_cs = of_clk_get(timer, clksel);
	if (IS_ERR(clk_cs)) {
		pr_err("ERROR: timer input clock not found\n");
		BUG();
	}

	clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_ce = of_clk_get(timer, clksel);
	if (IS_ERR(clk_ce)) {
		pr_err("ERROR: timer input clock not found\n");
		BUG();
	}

	ttc_setup_clocksource(clk_cs, timer_baseaddr);
	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);

	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
}

CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
Commit	Line	Data
b85a3ef4	1	/*
9e09dc5f	2	* This file contains driver for the Cadence Triple Timer Counter Rev 06
b85a3ef4	3	*
e932900a	4	* Copyright (C) 2011-2013 Xilinx
b85a3ef4 JL	5	*
	6	* based on arch/mips/kernel/time.c timer driver
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
e932900a	18	#include <linux/clk.h>
b85a3ef4	19	#include <linux/interrupt.h>
b85a3ef4	20	#include <linux/clockchips.h>
91dc985c JC	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
	23	#include <linux/slab.h>
	24	#include <linux/clk-provider.h>
b85a3ef4	25
e932900a MS	26	/*
	27	* This driver configures the 2 16-bit count-up timers as follows:
	28	*
	29	* T1: Timer 1, clocksource for generic timekeeping
	30	* T2: Timer 2, clockevent source for hrtimers
	31	* T3: Timer 3, <unused>
	32	*
	33	* The input frequency to the timer module for emulation is 2.5MHz which is
	34	* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
	35	* the timers are clocked at 78.125KHz (12.8 us resolution).
	36
	37	* The input frequency to the timer module in silicon is configurable and
	38	* obtained from device tree. The pre-scaler of 32 is used.
	39	*/
	40
b85a3ef4 JL	41	/*
	42	* Timer Register Offset Definitions of Timer 1, Increment base address by 4
	43	* and use same offsets for Timer 2
	44	*/
9e09dc5f MS	45	#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
	46	#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
	47	#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
	48	#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
	49	#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
	50	#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
f184c5ca	51
9e09dc5f	52	#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
b85a3ef4	53
30e1e285 SB	54	#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
30e1e285 SB	55
03377e58 SB	56	/*
03377e58 SB	57	* Setup the timers to use pre-scaling, using a fixed value for now that will
91dc985c JC	58	* work across most input frequency, but it may need to be more dynamic
	59	*/
	60	#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
	61	#define PRESCALE 2048 /* The exponent must match this */
	62	#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
	63	#define CLK_CNTRL_PRESCALE_EN 1
e932900a	64	#define CNT_CNTRL_RESET (1 << 4)
b85a3ef4 JL	65
b85a3ef4 JL	66	/**
9e09dc5f	67	* struct ttc_timer - This definition defines local timer structure
b85a3ef4 JL	68	*
b85a3ef4 JL	69	* @base_addr: Base address of timer
e932900a MS	70	* @clk: Associated clock source
	71	* @clk_rate_change_nb Notifier block for clock rate changes
	72	*/
9e09dc5f	73	struct ttc_timer {
e932900a MS	74	void __iomem *base_addr;
	75	struct clk *clk;
	76	struct notifier_block clk_rate_change_nb;
91dc985c JC	77	};
91dc985c JC	78
9e09dc5f MS	79	#define to_ttc_timer(x) \
9e09dc5f MS	80	container_of(x, struct ttc_timer, clk_rate_change_nb)
e932900a	81
9e09dc5f MS	82	struct ttc_timer_clocksource {
9e09dc5f MS	83	struct ttc_timer ttc;
91dc985c	84	struct clocksource cs;
b85a3ef4 JL	85	};
b85a3ef4 JL	86
9e09dc5f MS	87	#define to_ttc_timer_clksrc(x) \
9e09dc5f MS	88	container_of(x, struct ttc_timer_clocksource, cs)
91dc985c	89
9e09dc5f MS	90	struct ttc_timer_clockevent {
9e09dc5f MS	91	struct ttc_timer ttc;
91dc985c	92	struct clock_event_device ce;
91dc985c JC	93	};
91dc985c JC	94
9e09dc5f MS	95	#define to_ttc_timer_clkevent(x) \
9e09dc5f MS	96	container_of(x, struct ttc_timer_clockevent, ce)
b85a3ef4 JL	97
b85a3ef4 JL	98	/**
9e09dc5f	99	* ttc_set_interval - Set the timer interval value
b85a3ef4 JL	100	*
	101	* @timer: Pointer to the timer instance
	102	* @cycles: Timer interval ticks
	103	**/
9e09dc5f	104	static void ttc_set_interval(struct ttc_timer *timer,
b85a3ef4 JL	105	unsigned long cycles)
	106	{
	107	u32 ctrl_reg;
	108
	109	/* Disable the counter, set the counter value and re-enable counter */
9e09dc5f MS	110	ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	111	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
	112	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4	113
9e09dc5f	114	__raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
b85a3ef4	115
03377e58 SB	116	/*
	117	* Reset the counter (0x10) so that it starts from 0, one-shot
	118	* mode makes this needed for timing to be right.
	119	*/
91dc985c	120	ctrl_reg \|= CNT_CNTRL_RESET;
9e09dc5f MS	121	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
9e09dc5f MS	122	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	123	}
	124
	125	/**
9e09dc5f	126	* ttc_clock_event_interrupt - Clock event timer interrupt handler
b85a3ef4 JL	127	*
b85a3ef4 JL	128	* @irq: IRQ number of the Timer
9e09dc5f	129	* @dev_id: void pointer to the ttc_timer instance
b85a3ef4 JL	130	*
	131	* returns: Always IRQ_HANDLED - success
	132	**/
9e09dc5f	133	static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
b85a3ef4	134	{
9e09dc5f MS	135	struct ttc_timer_clockevent *ttce = dev_id;
9e09dc5f MS	136	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	137
b85a3ef4 JL	138	/* Acknowledge the interrupt and call event handler */
9e09dc5f	139	__raw_readl(timer->base_addr + TTC_ISR_OFFSET);
b85a3ef4	140
9e09dc5f	141	ttce->ce.event_handler(&ttce->ce);
b85a3ef4 JL	142
	143	return IRQ_HANDLED;
	144	}
	145
b85a3ef4	146	/**
9e09dc5f	147	* __ttc_clocksource_read - Reads the timer counter register
b85a3ef4 JL	148	*
	149	* returns: Current timer counter register value
	150	**/
9e09dc5f	151	static cycle_t __ttc_clocksource_read(struct clocksource *cs)
b85a3ef4	152	{
9e09dc5f	153	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
b85a3ef4 JL	154
b85a3ef4 JL	155	return (cycle_t)__raw_readl(timer->base_addr +
9e09dc5f	156	TTC_COUNT_VAL_OFFSET);
b85a3ef4 JL	157	}
b85a3ef4 JL	158
b85a3ef4	159	/**
9e09dc5f	160	* ttc_set_next_event - Sets the time interval for next event
b85a3ef4 JL	161	*
	162	* @cycles: Timer interval ticks
	163	* @evt: Address of clock event instance
	164	*
	165	* returns: Always 0 - success
	166	**/
9e09dc5f	167	static int ttc_set_next_event(unsigned long cycles,
b85a3ef4 JL	168	struct clock_event_device *evt)
b85a3ef4 JL	169	{
9e09dc5f MS	170	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	171	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4	172
9e09dc5f	173	ttc_set_interval(timer, cycles);
b85a3ef4 JL	174	return 0;
	175	}
	176
	177	/**
9e09dc5f	178	* ttc_set_mode - Sets the mode of timer
b85a3ef4 JL	179	*
	180	* @mode: Mode to be set
	181	* @evt: Address of clock event instance
	182	**/
9e09dc5f	183	static void ttc_set_mode(enum clock_event_mode mode,
b85a3ef4 JL	184	struct clock_event_device *evt)
b85a3ef4 JL	185	{
9e09dc5f MS	186	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
9e09dc5f MS	187	struct ttc_timer *timer = &ttce->ttc;
b85a3ef4 JL	188	u32 ctrl_reg;
	189
	190	switch (mode) {
	191	case CLOCK_EVT_MODE_PERIODIC:
9e09dc5f MS	192	ttc_set_interval(timer,
9e09dc5f MS	193	DIV_ROUND_CLOSEST(clk_get_rate(ttce->ttc.clk),
e932900a	194	PRESCALE * HZ));
b85a3ef4 JL	195	break;
	196	case CLOCK_EVT_MODE_ONESHOT:
	197	case CLOCK_EVT_MODE_UNUSED:
	198	case CLOCK_EVT_MODE_SHUTDOWN:
	199	ctrl_reg = __raw_readl(timer->base_addr +
9e09dc5f MS	200	TTC_CNT_CNTRL_OFFSET);
9e09dc5f MS	201	ctrl_reg \|= TTC_CNT_CNTRL_DISABLE_MASK;
b85a3ef4	202	__raw_writel(ctrl_reg,
9e09dc5f	203	timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	204	break;
	205	case CLOCK_EVT_MODE_RESUME:
	206	ctrl_reg = __raw_readl(timer->base_addr +
9e09dc5f MS	207	TTC_CNT_CNTRL_OFFSET);
9e09dc5f MS	208	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
b85a3ef4	209	__raw_writel(ctrl_reg,
9e09dc5f	210	timer->base_addr + TTC_CNT_CNTRL_OFFSET);
b85a3ef4 JL	211	break;
	212	}
	213	}
	214
9e09dc5f	215	static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
e932900a MS	216	unsigned long event, void *data)
	217	{
	218	struct clk_notifier_data *ndata = data;
9e09dc5f MS	219	struct ttc_timer *ttc = to_ttc_timer(nb);
	220	struct ttc_timer_clocksource *ttccs = container_of(ttc,
	221	struct ttc_timer_clocksource, ttc);
e932900a MS	222
	223	switch (event) {
	224	case POST_RATE_CHANGE:
	225	/*
	226	* Do whatever is necessary to maintain a proper time base
	227	*
	228	* I cannot find a way to adjust the currently used clocksource
	229	* to the new frequency. __clocksource_updatefreq_hz() sounds
	230	* good, but does not work. Not sure what's that missing.
	231	*
	232	* This approach works, but triggers two clocksource switches.
	233	* The first after unregister to clocksource jiffies. And
	234	* another one after the register to the newly registered timer.
	235	*
	236	* Alternatively we could 'waste' another HW timer to ping pong
	237	* between clock sources. That would also use one register and
	238	* one unregister call, but only trigger one clocksource switch
	239	* for the cost of another HW timer used by the OS.
	240	*/
9e09dc5f MS	241	clocksource_unregister(&ttccs->cs);
9e09dc5f MS	242	clocksource_register_hz(&ttccs->cs,
e932900a MS	243	ndata->new_rate / PRESCALE);
	244	/* fall through */
	245	case PRE_RATE_CHANGE:
	246	case ABORT_RATE_CHANGE:
	247	default:
	248	return NOTIFY_DONE;
	249	}
	250	}
	251
9e09dc5f	252	static void __init ttc_setup_clocksource(struct clk clk, void __iomem base)
91dc985c	253	{
9e09dc5f	254	struct ttc_timer_clocksource *ttccs;
91dc985c	255	int err;
91dc985c JC	256
	257	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	258	if (WARN_ON(!ttccs))
	259	return;
	260
9e09dc5f	261	ttccs->ttc.clk = clk;
91dc985c	262
9e09dc5f	263	err = clk_prepare_enable(ttccs->ttc.clk);
c5263bb8 MS	264	if (WARN_ON(err)) {
c5263bb8 MS	265	kfree(ttccs);
91dc985c	266	return;
c5263bb8	267	}
91dc985c	268
9e09dc5f MS	269	ttccs->ttc.clk_rate_change_nb.notifier_call =
	270	ttc_rate_change_clocksource_cb;
	271	ttccs->ttc.clk_rate_change_nb.next = NULL;
	272	if (clk_notifier_register(ttccs->ttc.clk,
	273	&ttccs->ttc.clk_rate_change_nb))
e932900a	274	pr_warn("Unable to register clock notifier.\n");
91dc985c	275
9e09dc5f MS	276	ttccs->ttc.base_addr = base;
9e09dc5f MS	277	ttccs->cs.name = "ttc_clocksource";
91dc985c	278	ttccs->cs.rating = 200;
9e09dc5f	279	ttccs->cs.read = __ttc_clocksource_read;
91dc985c JC	280	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	281	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	282
e932900a MS	283	/*
	284	* Setup the clock source counter to be an incrementing counter
	285	* with no interrupt and it rolls over at 0xFFFF. Pre-scale
	286	* it by 32 also. Let it start running now.
	287	*/
9e09dc5f	288	__raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
91dc985c	289	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f	290	ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
91dc985c	291	__raw_writel(CNT_CNTRL_RESET,
9e09dc5f	292	ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
91dc985c	293
e932900a	294	err = clocksource_register_hz(&ttccs->cs,
9e09dc5f	295	clk_get_rate(ttccs->ttc.clk) / PRESCALE);
c5263bb8 MS	296	if (WARN_ON(err)) {
c5263bb8 MS	297	kfree(ttccs);
91dc985c	298	return;
c5263bb8	299	}
91dc985c JC	300	}
91dc985c JC	301
9e09dc5f	302	static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
e932900a MS	303	unsigned long event, void *data)
	304	{
	305	struct clk_notifier_data *ndata = data;
9e09dc5f MS	306	struct ttc_timer *ttc = to_ttc_timer(nb);
	307	struct ttc_timer_clockevent *ttcce = container_of(ttc,
	308	struct ttc_timer_clockevent, ttc);
e932900a MS	309
	310	switch (event) {
	311	case POST_RATE_CHANGE:
	312	{
	313	unsigned long flags;
	314
	315	/*
	316	* clockevents_update_freq should be called with IRQ disabled on
	317	* the CPU the timer provides events for. The timer we use is
	318	* common to both CPUs, not sure if we need to run on both
	319	* cores.
	320	*/
	321	local_irq_save(flags);
9e09dc5f	322	clockevents_update_freq(&ttcce->ce,
e932900a MS	323	ndata->new_rate / PRESCALE);
	324	local_irq_restore(flags);
	325
	326	/* fall through */
	327	}
	328	case PRE_RATE_CHANGE:
	329	case ABORT_RATE_CHANGE:
	330	default:
	331	return NOTIFY_DONE;
	332	}
	333	}
	334
9e09dc5f	335	static void __init ttc_setup_clockevent(struct clk *clk,
e932900a	336	void __iomem *base, u32 irq)
91dc985c	337	{
9e09dc5f	338	struct ttc_timer_clockevent *ttcce;
e932900a	339	int err;
91dc985c JC	340
	341	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	342	if (WARN_ON(!ttcce))
	343	return;
	344
9e09dc5f	345	ttcce->ttc.clk = clk;
91dc985c	346
9e09dc5f	347	err = clk_prepare_enable(ttcce->ttc.clk);
c5263bb8 MS	348	if (WARN_ON(err)) {
c5263bb8 MS	349	kfree(ttcce);
91dc985c	350	return;
c5263bb8	351	}
91dc985c	352
9e09dc5f MS	353	ttcce->ttc.clk_rate_change_nb.notifier_call =
	354	ttc_rate_change_clockevent_cb;
	355	ttcce->ttc.clk_rate_change_nb.next = NULL;
	356	if (clk_notifier_register(ttcce->ttc.clk,
	357	&ttcce->ttc.clk_rate_change_nb))
e932900a	358	pr_warn("Unable to register clock notifier.\n");
91dc985c	359
9e09dc5f MS	360	ttcce->ttc.base_addr = base;
9e09dc5f MS	361	ttcce->ce.name = "ttc_clockevent";
91dc985c	362	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
9e09dc5f MS	363	ttcce->ce.set_next_event = ttc_set_next_event;
9e09dc5f MS	364	ttcce->ce.set_mode = ttc_set_mode;
91dc985c JC	365	ttcce->ce.rating = 200;
91dc985c JC	366	ttcce->ce.irq = irq;
87e4ee75	367	ttcce->ce.cpumask = cpu_possible_mask;
91dc985c	368
e932900a MS	369	/*
	370	* Setup the clock event timer to be an interval timer which
	371	* is prescaled by 32 using the interval interrupt. Leave it
	372	* disabled for now.
	373	*/
9e09dc5f	374	__raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
91dc985c	375	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
9e09dc5f MS	376	ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
9e09dc5f MS	377	__raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
91dc985c	378
9e09dc5f	379	err = request_irq(irq, ttc_clock_event_interrupt,
e932900a MS	380	IRQF_DISABLED \| IRQF_TIMER,
e932900a MS	381	ttcce->ce.name, ttcce);
c5263bb8 MS	382	if (WARN_ON(err)) {
c5263bb8 MS	383	kfree(ttcce);
91dc985c	384	return;
c5263bb8	385	}
91dc985c JC	386
91dc985c JC	387	clockevents_config_and_register(&ttcce->ce,
9e09dc5f	388	clk_get_rate(ttcce->ttc.clk) / PRESCALE, 1, 0xfffe);
91dc985c JC	389	}
91dc985c JC	390
b85a3ef4	391	/**
9e09dc5f	392	* ttc_timer_init - Initialize the timer
b85a3ef4 JL	393	*
	394	* Initializes the timer hardware and register the clock source and clock event
	395	* timers with Linux kernal timer framework
e932900a	396	*/
9e09dc5f	397	static void __init ttc_timer_init(struct device_node *timer)
e932900a MS	398	{
	399	unsigned int irq;
	400	void __iomem *timer_baseaddr;
30e1e285	401	struct clk clk_cs, clk_ce;
c5263bb8	402	static int initialized;
30e1e285	403	int clksel;
c5263bb8 MS	404
	405	if (initialized)
	406	return;
	407
	408	initialized = 1;
e932900a MS	409
	410	/*
	411	* Get the 1st Triple Timer Counter (TTC) block from the device tree
	412	* and use it. Note that the event timer uses the interrupt and it's the
	413	* 2nd TTC hence the irq_of_parse_and_map(,1)
	414	*/
	415	timer_baseaddr = of_iomap(timer, 0);
	416	if (!timer_baseaddr) {
	417	pr_err("ERROR: invalid timer base address\n");
	418	BUG();
	419	}
	420
	421	irq = irq_of_parse_and_map(timer, 1);
	422	if (irq <= 0) {
	423	pr_err("ERROR: invalid interrupt number\n");
	424	BUG();
	425	}
	426
30e1e285 SB	427	clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
	428	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	429	clk_cs = of_clk_get(timer, clksel);
	430	if (IS_ERR(clk_cs)) {
	431	pr_err("ERROR: timer input clock not found\n");
	432	BUG();
	433	}
	434
	435	clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
	436	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	437	clk_ce = of_clk_get(timer, clksel);
	438	if (IS_ERR(clk_ce)) {
e932900a MS	439	pr_err("ERROR: timer input clock not found\n");
	440	BUG();
	441	}
	442
30e1e285 SB	443	ttc_setup_clocksource(clk_cs, timer_baseaddr);
30e1e285 SB	444	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
e932900a MS	445
	446	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
	447	}
	448
9e09dc5f	449	CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);