[deliverable/linux.git] / drivers / clocksource / h8300_timer16.c

/*
 *  H8/300 16bit Timer driver
 *
 *  Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
 */

#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TSTR	0
#define TISRC	6

#define TCR	0
#define TCNT	2

struct timer16_priv {
	struct clocksource cs;
	unsigned long total_cycles;
	void __iomem *mapbase;
	void __iomem *mapcommon;
	unsigned short cs_enabled;
	unsigned char enb;
	unsigned char ovf;
	unsigned char ovie;
	struct clk *clk;
};

static unsigned long timer16_get_counter(struct timer16_priv *p)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = readb(p->mapcommon + TISRC) & p->ovf;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = readw(p->mapbase + TCNT);
		v2 = readw(p->mapbase + TCNT);
		v3 = readw(p->mapbase + TCNT);
		o1 = readb(p->mapcommon + TISRC) & p->ovf;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	v2 |= 0x10000;
	return v2;
}


static irqreturn_t timer16_interrupt(int irq, void *dev_id)
{
	struct timer16_priv *p = (struct timer16_priv *)dev_id;

	writeb(readb(p->mapcommon + TISRC) & ~p->ovf,
		  p->mapcommon + TISRC);
	p->total_cycles += 0x10000;

	return IRQ_HANDLED;
}

static inline struct timer16_priv *cs_to_priv(struct clocksource *cs)
{
	return container_of(cs, struct timer16_priv, cs);
}

static cycle_t timer16_clocksource_read(struct clocksource *cs)
{
	struct timer16_priv *p = cs_to_priv(cs);
	unsigned long raw, value;

	value = p->total_cycles;
	raw = timer16_get_counter(p);

	return value + raw;
}

static int timer16_enable(struct clocksource *cs)
{
	struct timer16_priv *p = cs_to_priv(cs);

	WARN_ON(p->cs_enabled);

	p->total_cycles = 0;
	writew(0x0000, p->mapbase + TCNT);
	writeb(0x83, p->mapbase + TCR);
	writeb(readb(p->mapcommon + TSTR) | p->enb,
		  p->mapcommon + TSTR);
	writeb(readb(p->mapcommon + TISRC) | p->ovie,
		  p->mapcommon + TSTR);

	p->cs_enabled = true;
	return 0;
}

static void timer16_disable(struct clocksource *cs)
{
	struct timer16_priv *p = cs_to_priv(cs);

	WARN_ON(!p->cs_enabled);

	writeb(readb(p->mapcommon + TSTR) & ~p->enb,
		  p->mapcommon + TSTR);

	p->cs_enabled = false;
}

static struct timer16_priv timer16_priv = {
	.cs = {
		.name = "h8300_16timer",
		.rating = 200,
		.read = timer16_clocksource_read,
		.enable = timer16_enable,
		.disable = timer16_disable,
		.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
		.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	},
};

#define REG_CH   0
#define REG_COMM 1

static void __init h8300_16timer_init(struct device_node *node)
{
	void __iomem *base[2];
	int ret, irq;
	unsigned int ch;
	struct clk *clk;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("failed to get clock for clocksource\n");
		return;
	}

	base[REG_CH] = of_iomap(node, 0);
	if (!base[REG_CH]) {
		pr_err("failed to map registers for clocksource\n");
		goto free_clk;
	}

	base[REG_COMM] = of_iomap(node, 1);
	if (!base[REG_COMM]) {
		pr_err("failed to map registers for clocksource\n");
		goto unmap_ch;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (!irq) {
		pr_err("failed to get irq for clockevent\n");
		goto unmap_comm;
	}

	of_property_read_u32(node, "renesas,channel", &ch);

	timer16_priv.mapbase = base[REG_CH];
	timer16_priv.mapcommon = base[REG_COMM];
	timer16_priv.enb = 1 << ch;
	timer16_priv.ovf = 1 << ch;
	timer16_priv.ovie = 1 << (4 + ch);

	ret = request_irq(irq, timer16_interrupt,
			  IRQF_TIMER, timer16_priv.cs.name, &timer16_priv);
	if (ret < 0) {
		pr_err("failed to request irq %d of clocksource\n", irq);
		goto unmap_comm;
	}

	clocksource_register_hz(&timer16_priv.cs,
				clk_get_rate(timer16_priv.clk) / 8);
	return;

unmap_comm:
	iounmap(base[REG_COMM]);
unmap_ch:
	iounmap(base[REG_CH]);
free_clk:
	clk_put(clk);
}

CLOCKSOURCE_OF_DECLARE(h8300_16bit, "renesas,16bit-timer", h8300_16timer_init);
Commit	Line	Data
618b902d YS	1	/*
	2	* H8/300 16bit Timer driver
	3	*
	4	* Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
	5	*/
	6
618b902d YS	7	#include <linux/interrupt.h>
618b902d YS	8	#include <linux/init.h>
618b902d	9	#include <linux/clocksource.h>
618b902d YS	10	#include <linux/clk.h>
	11	#include <linux/io.h>
	12	#include <linux/of.h>
4633f4ca YS	13	#include <linux/of_address.h>
4633f4ca YS	14	#include <linux/of_irq.h>
618b902d	15
618b902d	16	#define TSTR 0
618b902d YS	17	#define TISRC 6
	18
	19	#define TCR 0
618b902d	20	#define TCNT 2
618b902d YS	21
618b902d YS	22	struct timer16_priv {
618b902d	23	struct clocksource cs;
618b902d	24	unsigned long total_cycles;
75160515 DL	25	void __iomem *mapbase;
75160515 DL	26	void __iomem *mapcommon;
618b902d YS	27	unsigned short cs_enabled;
618b902d YS	28	unsigned char enb;
618b902d	29	unsigned char ovf;
2a0ff877	30	unsigned char ovie;
618b902d YS	31	struct clk *clk;
	32	};
	33
	34	static unsigned long timer16_get_counter(struct timer16_priv *p)
	35	{
	36	unsigned long v1, v2, v3;
	37	int o1, o2;
	38
75160515	39	o1 = readb(p->mapcommon + TISRC) & p->ovf;
618b902d YS	40
	41	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	42	do {
	43	o2 = o1;
75160515 DL	44	v1 = readw(p->mapbase + TCNT);
	45	v2 = readw(p->mapbase + TCNT);
	46	v3 = readw(p->mapbase + TCNT);
	47	o1 = readb(p->mapcommon + TISRC) & p->ovf;
618b902d YS	48	} while (unlikely((o1 != o2) \|\| (v1 > v2 && v1 < v3)
	49	\|\| (v2 > v3 && v2 < v1) \|\| (v3 > v1 && v3 < v2)));
	50
	51	v2 \|= 0x10000;
	52	return v2;
	53	}
	54
	55
	56	static irqreturn_t timer16_interrupt(int irq, void *dev_id)
	57	{
	58	struct timer16_priv p = (struct timer16_priv )dev_id;
	59
2a0ff877 YS	60	writeb(readb(p->mapcommon + TISRC) & ~p->ovf,
2a0ff877 YS	61	p->mapcommon + TISRC);
618b902d YS	62	p->total_cycles += 0x10000;
	63
	64	return IRQ_HANDLED;
	65	}
	66
	67	static inline struct timer16_priv cs_to_priv(struct clocksource cs)
	68	{
	69	return container_of(cs, struct timer16_priv, cs);
	70	}
	71
	72	static cycle_t timer16_clocksource_read(struct clocksource *cs)
	73	{
	74	struct timer16_priv *p = cs_to_priv(cs);
05de7ed6	75	unsigned long raw, value;
618b902d	76
618b902d YS	77	value = p->total_cycles;
618b902d YS	78	raw = timer16_get_counter(p);
618b902d YS	79
	80	return value + raw;
	81	}
	82
	83	static int timer16_enable(struct clocksource *cs)
	84	{
	85	struct timer16_priv *p = cs_to_priv(cs);
	86
	87	WARN_ON(p->cs_enabled);
	88
	89	p->total_cycles = 0;
75160515 DL	90	writew(0x0000, p->mapbase + TCNT);
	91	writeb(0x83, p->mapbase + TCR);
	92	writeb(readb(p->mapcommon + TSTR) \| p->enb,
618b902d	93	p->mapcommon + TSTR);
2a0ff877 YS	94	writeb(readb(p->mapcommon + TISRC) \| p->ovie,
2a0ff877 YS	95	p->mapcommon + TSTR);
618b902d YS	96
	97	p->cs_enabled = true;
	98	return 0;
	99	}
	100
	101	static void timer16_disable(struct clocksource *cs)
	102	{
	103	struct timer16_priv *p = cs_to_priv(cs);
	104
	105	WARN_ON(!p->cs_enabled);
	106
75160515	107	writeb(readb(p->mapcommon + TSTR) & ~p->enb,
618b902d YS	108	p->mapcommon + TSTR);
	109
	110	p->cs_enabled = false;
	111	}
	112
4633f4ca YS	113	static struct timer16_priv timer16_priv = {
	114	.cs = {
	115	.name = "h8300_16timer",
	116	.rating = 200,
	117	.read = timer16_clocksource_read,
	118	.enable = timer16_enable,
	119	.disable = timer16_disable,
	120	.mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
	121	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	122	},
	123	};
	124
618b902d YS	125	#define REG_CH 0
	126	#define REG_COMM 1
	127
4633f4ca	128	static void __init h8300_16timer_init(struct device_node *node)
618b902d	129	{
4633f4ca	130	void __iomem *base[2];
618b902d YS	131	int ret, irq;
618b902d YS	132	unsigned int ch;
4633f4ca	133	struct clk *clk;
618b902d	134
4633f4ca YS	135	clk = of_clk_get(node, 0);
	136	if (IS_ERR(clk)) {
	137	pr_err("failed to get clock for clocksource\n");
	138	return;
618b902d YS	139	}
618b902d YS	140
4633f4ca YS	141	base[REG_CH] = of_iomap(node, 0);
	142	if (!base[REG_CH]) {
	143	pr_err("failed to map registers for clocksource\n");
	144	goto free_clk;
618b902d	145	}
618b902d	146
4633f4ca YS	147	base[REG_COMM] = of_iomap(node, 1);
	148	if (!base[REG_COMM]) {
	149	pr_err("failed to map registers for clocksource\n");
	150	goto unmap_ch;
618b902d YS	151	}
618b902d YS	152
4633f4ca	153	irq = irq_of_parse_and_map(node, 0);
5019c902	154	if (!irq) {
4633f4ca YS	155	pr_err("failed to get irq for clockevent\n");
4633f4ca YS	156	goto unmap_comm;
618b902d YS	157	}
618b902d YS	158
4633f4ca	159	of_property_read_u32(node, "renesas,channel", &ch);
618b902d	160
75160515 DL	161	timer16_priv.mapbase = base[REG_CH];
75160515 DL	162	timer16_priv.mapcommon = base[REG_COMM];
4633f4ca	163	timer16_priv.enb = 1 << ch;
2a0ff877 YS	164	timer16_priv.ovf = 1 << ch;
2a0ff877 YS	165	timer16_priv.ovie = 1 << (4 + ch);
618b902d	166
4633f4ca YS	167	ret = request_irq(irq, timer16_interrupt,
	168	IRQF_TIMER, timer16_priv.cs.name, &timer16_priv);
	169	if (ret < 0) {
	170	pr_err("failed to request irq %d of clocksource\n", irq);
	171	goto unmap_comm;
618b902d	172	}
618b902d	173
4633f4ca YS	174	clocksource_register_hz(&timer16_priv.cs,
	175	clk_get_rate(timer16_priv.clk) / 8);
	176	return;
618b902d	177
4633f4ca YS	178	unmap_comm:
	179	iounmap(base[REG_COMM]);
	180	unmap_ch:
	181	iounmap(base[REG_CH]);
	182	free_clk:
	183	clk_put(clk);
618b902d YS	184	}
618b902d YS	185
4633f4ca	186	CLOCKSOURCE_OF_DECLARE(h8300_16bit, "renesas,16bit-timer", h8300_16timer_init);