[deliverable/linux.git] / drivers / clocksource / h8300_timer8.c

/*
 *  linux/arch/h8300/kernel/cpu/timer/timer8.c
 *
 *  Yoshinori Sato <ysato@users.sourcefoge.jp>
 *
 *  8bit Timer driver
 *
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define _8TCR	0
#define _8TCSR	2
#define TCORA	4
#define TCORB	6
#define _8TCNT	8

#define FLAG_STARTED (1 << 3)

#define SCALE 64

struct timer8_priv {
	struct clock_event_device ced;
	unsigned long mapbase;
	unsigned long flags;
	unsigned int rate;
	unsigned int tcora;
	struct clk *pclk;
};

static unsigned long timer8_get_counter(struct timer8_priv *p)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = ctrl_inw(p->mapbase + _8TCNT);
		v2 = ctrl_inw(p->mapbase + _8TCNT);
		v3 = ctrl_inw(p->mapbase + _8TCNT);
		o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	v2 |= o1 << 10;
	return v2;
}

static irqreturn_t timer8_interrupt(int irq, void *dev_id)
{
	struct timer8_priv *p = dev_id;

	ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x40,
		  p->mapbase + _8TCSR);

	ctrl_outw(p->tcora, p->mapbase + TCORA);

	if (clockevent_state_oneshot(&p->ced))
		ctrl_outw(0x0000, p->mapbase + _8TCR);

	p->ced.event_handler(&p->ced);

	return IRQ_HANDLED;
}

static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
{
	unsigned long now;

	if (delta >= 0x10000)
		pr_warn("delta out of range\n");
	now = timer8_get_counter(p);
	p->tcora = delta;
	ctrl_outb(ctrl_inb(p->mapbase + _8TCR) | 0x40, p->mapbase + _8TCR);
	if (delta > now)
		ctrl_outw(delta, p->mapbase + TCORA);
	else
		ctrl_outw(now + 1, p->mapbase + TCORA);
}

static int timer8_enable(struct timer8_priv *p)
{
	p->rate = clk_get_rate(p->pclk) / SCALE;
	ctrl_outw(0xffff, p->mapbase + TCORA);
	ctrl_outw(0x0000, p->mapbase + _8TCNT);
	ctrl_outw(0x0c02, p->mapbase + _8TCR);

	return 0;
}

static int timer8_start(struct timer8_priv *p)
{
	int ret = 0;

	if (!(p->flags & FLAG_STARTED))
		ret = timer8_enable(p);

	if (ret)
		goto out;
	p->flags |= FLAG_STARTED;

 out:
	return ret;
}

static void timer8_stop(struct timer8_priv *p)
{
	ctrl_outw(0x0000, p->mapbase + _8TCR);
}

static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
{
	return container_of(ced, struct timer8_priv, ced);
}

static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
{
	struct clock_event_device *ced = &p->ced;

	timer8_start(p);

	ced->shift = 32;
	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);

	timer8_set_next(p, delta);
}

static int timer8_clock_event_shutdown(struct clock_event_device *ced)
{
	timer8_stop(ced_to_priv(ced));
	return 0;
}

static int timer8_clock_event_periodic(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for periodic clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);

	return 0;
}

static int timer8_clock_event_oneshot(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for oneshot clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, 0x10000);

	return 0;
}

static int timer8_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	BUG_ON(!clockevent_state_oneshot(ced));
	timer8_set_next(p, delta - 1);

	return 0;
}

static struct timer8_priv timer8_priv = {
	.ced = {
		.name = "h8300_8timer",
		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
		.rating = 200,
		.set_next_event = timer8_clock_event_next,
		.set_state_shutdown = timer8_clock_event_shutdown,
		.set_state_periodic = timer8_clock_event_periodic,
		.set_state_oneshot = timer8_clock_event_oneshot,
	},
};

static void __init h8300_8timer_init(struct device_node *node)
{
	void __iomem *base;
	int irq;
	int ret = 0;
	int rate;
	struct clk *clk;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("failed to get clock for clockevent\n");
		return;
	}

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("failed to map registers for clockevent\n");
		goto free_clk;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (!irq) {
		pr_err("failed to get irq for clockevent\n");
		goto unmap_reg;
	}

	timer8_priv.mapbase = (unsigned long)base;
	timer8_priv.pclk = clk;

	ret = request_irq(irq, timer8_interrupt,
			  IRQF_TIMER, timer8_priv.ced.name, &timer8_priv);
	if (ret < 0) {
		pr_err("failed to request irq %d for clockevent\n", irq);
		goto unmap_reg;
	}
	rate = clk_get_rate(clk) / SCALE;
	clockevents_config_and_register(&timer8_priv.ced, rate, 1, 0x0000ffff);
	return;

unmap_reg:
	iounmap(base);
free_clk:
	clk_put(clk);
}

CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
Commit	Line	Data
618b902d YS	1	/*
	2	* linux/arch/h8300/kernel/cpu/timer/timer8.c
	3	*
	4	* Yoshinori Sato <ysato@users.sourcefoge.jp>
	5	*
	6	* 8bit Timer driver
	7	*
	8	*/
	9
	10	#include <linux/errno.h>
618b902d YS	11	#include <linux/kernel.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/init.h>
618b902d	14	#include <linux/clockchips.h>
618b902d YS	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/of.h>
4633f4ca YS	18	#include <linux/of_address.h>
4633f4ca YS	19	#include <linux/of_irq.h>
618b902d	20
618b902d YS	21	#define _8TCR 0
	22	#define _8TCSR 2
	23	#define TCORA 4
	24	#define TCORB 6
	25	#define _8TCNT 8
	26
618b902d YS	27	#define FLAG_STARTED (1 << 3)
618b902d YS	28
4633f4ca YS	29	#define SCALE 64
4633f4ca YS	30
618b902d	31	struct timer8_priv {
618b902d	32	struct clock_event_device ced;
618b902d	33	unsigned long mapbase;
618b902d YS	34	unsigned long flags;
	35	unsigned int rate;
	36	unsigned int tcora;
	37	struct clk *pclk;
	38	};
	39
	40	static unsigned long timer8_get_counter(struct timer8_priv *p)
	41	{
	42	unsigned long v1, v2, v3;
	43	int o1, o2;
	44
	45	o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;
	46
	47	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	48	do {
	49	o2 = o1;
	50	v1 = ctrl_inw(p->mapbase + _8TCNT);
	51	v2 = ctrl_inw(p->mapbase + _8TCNT);
	52	v3 = ctrl_inw(p->mapbase + _8TCNT);
	53	o1 = ctrl_inb(p->mapbase + _8TCSR) & 0x20;
	54	} while (unlikely((o1 != o2) \|\| (v1 > v2 && v1 < v3)
	55	\|\| (v2 > v3 && v2 < v1) \|\| (v3 > v1 && v3 < v2)));
	56
	57	v2 \|= o1 << 10;
	58	return v2;
	59	}
	60
	61	static irqreturn_t timer8_interrupt(int irq, void *dev_id)
	62	{
	63	struct timer8_priv *p = dev_id;
	64
	65	ctrl_outb(ctrl_inb(p->mapbase + _8TCSR) & ~0x40,
	66	p->mapbase + _8TCSR);
7053fdac	67
618b902d	68	ctrl_outw(p->tcora, p->mapbase + TCORA);
7053fdac DL	69
	70	if (clockevent_state_oneshot(&p->ced))
	71	ctrl_outw(0x0000, p->mapbase + _8TCR);
	72
	73	p->ced.event_handler(&p->ced);
618b902d YS	74
	75	return IRQ_HANDLED;
	76	}
	77
	78	static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
	79	{
618b902d YS	80	unsigned long now;
618b902d YS	81
618b902d	82	if (delta >= 0x10000)
8c09b7d6	83	pr_warn("delta out of range\n");
618b902d YS	84	now = timer8_get_counter(p);
	85	p->tcora = delta;
	86	ctrl_outb(ctrl_inb(p->mapbase + _8TCR) \| 0x40, p->mapbase + _8TCR);
	87	if (delta > now)
	88	ctrl_outw(delta, p->mapbase + TCORA);
	89	else
	90	ctrl_outw(now + 1, p->mapbase + TCORA);
618b902d YS	91	}
	92
	93	static int timer8_enable(struct timer8_priv *p)
	94	{
4633f4ca	95	p->rate = clk_get_rate(p->pclk) / SCALE;
618b902d YS	96	ctrl_outw(0xffff, p->mapbase + TCORA);
	97	ctrl_outw(0x0000, p->mapbase + _8TCNT);
	98	ctrl_outw(0x0c02, p->mapbase + _8TCR);
	99
	100	return 0;
	101	}
	102
	103	static int timer8_start(struct timer8_priv *p)
	104	{
	105	int ret = 0;
618b902d YS	106
	107	if (!(p->flags & FLAG_STARTED))
	108	ret = timer8_enable(p);
	109
	110	if (ret)
	111	goto out;
	112	p->flags \|= FLAG_STARTED;
	113
	114	out:
618b902d YS	115	return ret;
	116	}
	117
	118	static void timer8_stop(struct timer8_priv *p)
	119	{
618b902d	120	ctrl_outw(0x0000, p->mapbase + _8TCR);
618b902d YS	121	}
	122
	123	static inline struct timer8_priv ced_to_priv(struct clock_event_device ced)
	124	{
	125	return container_of(ced, struct timer8_priv, ced);
	126	}
	127
1f058d52	128	static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
618b902d YS	129	{
	130	struct clock_event_device *ced = &p->ced;
	131
	132	timer8_start(p);
	133
	134	ced->shift = 32;
	135	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	136	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	137	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);
	138
1f058d52	139	timer8_set_next(p, delta);
618b902d YS	140	}
618b902d YS	141
fc2b2f5d VK	142	static int timer8_clock_event_shutdown(struct clock_event_device *ced)
	143	{
	144	timer8_stop(ced_to_priv(ced));
	145	return 0;
	146	}
	147
	148	static int timer8_clock_event_periodic(struct clock_event_device *ced)
618b902d YS	149	{
	150	struct timer8_priv *p = ced_to_priv(ced);
	151
4633f4ca	152	pr_info("%s: used for periodic clock events\n", ced->name);
fc2b2f5d	153	timer8_stop(p);
1f058d52	154	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
fc2b2f5d VK	155
	156	return 0;
	157	}
	158
	159	static int timer8_clock_event_oneshot(struct clock_event_device *ced)
	160	{
	161	struct timer8_priv *p = ced_to_priv(ced);
	162
4633f4ca	163	pr_info("%s: used for oneshot clock events\n", ced->name);
fc2b2f5d	164	timer8_stop(p);
1f058d52	165	timer8_clock_event_start(p, 0x10000);
fc2b2f5d VK	166
fc2b2f5d VK	167	return 0;
618b902d YS	168	}
	169
	170	static int timer8_clock_event_next(unsigned long delta,
	171	struct clock_event_device *ced)
	172	{
	173	struct timer8_priv *p = ced_to_priv(ced);
	174
fc2b2f5d	175	BUG_ON(!clockevent_state_oneshot(ced));
618b902d YS	176	timer8_set_next(p, delta - 1);
	177
	178	return 0;
	179	}
	180
4633f4ca YS	181	static struct timer8_priv timer8_priv = {
	182	.ced = {
	183	.name = "h8300_8timer",
	184	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	185	.rating = 200,
	186	.set_next_event = timer8_clock_event_next,
	187	.set_state_shutdown = timer8_clock_event_shutdown,
	188	.set_state_periodic = timer8_clock_event_periodic,
	189	.set_state_oneshot = timer8_clock_event_oneshot,
	190	},
	191	};
	192
	193	static void __init h8300_8timer_init(struct device_node *node)
618b902d	194	{
4633f4ca	195	void __iomem *base;
618b902d	196	int irq;
4633f4ca YS	197	int ret = 0;
	198	int rate;
	199	struct clk *clk;
618b902d	200
4633f4ca YS	201	clk = of_clk_get(node, 0);
	202	if (IS_ERR(clk)) {
	203	pr_err("failed to get clock for clockevent\n");
	204	return;
	205	}
618b902d	206
4633f4ca YS	207	base = of_iomap(node, 0);
	208	if (!base) {
	209	pr_err("failed to map registers for clockevent\n");
	210	goto free_clk;
618b902d YS	211	}
618b902d YS	212
4633f4ca	213	irq = irq_of_parse_and_map(node, 0);
54a0cd5a	214	if (!irq) {
4633f4ca YS	215	pr_err("failed to get irq for clockevent\n");
4633f4ca YS	216	goto unmap_reg;
618b902d YS	217	}
618b902d YS	218
4633f4ca YS	219	timer8_priv.mapbase = (unsigned long)base;
4633f4ca YS	220	timer8_priv.pclk = clk;
618b902d	221
4633f4ca YS	222	ret = request_irq(irq, timer8_interrupt,
4633f4ca YS	223	IRQF_TIMER, timer8_priv.ced.name, &timer8_priv);
618b902d	224	if (ret < 0) {
4633f4ca YS	225	pr_err("failed to request irq %d for clockevent\n", irq);
4633f4ca YS	226	goto unmap_reg;
618b902d	227	}
4633f4ca YS	228	rate = clk_get_rate(clk) / SCALE;
	229	clockevents_config_and_register(&timer8_priv.ced, rate, 1, 0x0000ffff);
	230	return;
	231
	232	unmap_reg:
	233	iounmap(base);
	234	free_clk:
	235	clk_put(clk);
618b902d YS	236	}
618b902d YS	237
4633f4ca	238	CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);