[deliverable/linux.git] / drivers / clocksource / h8300_timer8.c

/*
 *  linux/arch/h8300/kernel/cpu/timer/timer8.c
 *
 *  Yoshinori Sato <ysato@users.sourcefoge.jp>
 *
 *  8bit Timer driver
 *
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define _8TCR	0
#define _8TCSR	2
#define TCORA	4
#define TCORB	6
#define _8TCNT	8

#define FLAG_STARTED (1 << 3)

#define SCALE 64

struct timer8_priv {
	struct clock_event_device ced;
	void __iomem *mapbase;
	unsigned long flags;
	unsigned int rate;
};

static irqreturn_t timer8_interrupt(int irq, void *dev_id)
{
	struct timer8_priv *p = dev_id;

	if (clockevent_state_oneshot(&p->ced))
		writew(0x0000, p->mapbase + _8TCR);

	p->ced.event_handler(&p->ced);

	writeb(readb(p->mapbase + _8TCSR) & ~0x40,
		  p->mapbase + _8TCSR);

	return IRQ_HANDLED;
}

static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
{
	if (delta >= 0x10000)
		pr_warn("delta out of range\n");
	writeb(readb(p->mapbase + _8TCR) & ~0x40, p->mapbase + _8TCR);
	writew(0, p->mapbase + _8TCNT);
	writew(delta, p->mapbase + TCORA);
	writeb(readb(p->mapbase + _8TCR) | 0x40, p->mapbase + _8TCR);
}

static int timer8_enable(struct timer8_priv *p)
{
	writew(0xffff, p->mapbase + TCORA);
	writew(0x0000, p->mapbase + _8TCNT);
	writew(0x0c02, p->mapbase + _8TCR);

	return 0;
}

static int timer8_start(struct timer8_priv *p)
{
	int ret;

	if ((p->flags & FLAG_STARTED))
		return 0;

	ret = timer8_enable(p);
	if (!ret)
		p->flags |= FLAG_STARTED;

	return ret;
}

static void timer8_stop(struct timer8_priv *p)
{
	writew(0x0000, p->mapbase + _8TCR);
}

static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
{
	return container_of(ced, struct timer8_priv, ced);
}

static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
{
	struct clock_event_device *ced = &p->ced;

	timer8_start(p);

	ced->shift = 32;
	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);

	timer8_set_next(p, delta);
}

static int timer8_clock_event_shutdown(struct clock_event_device *ced)
{
	timer8_stop(ced_to_priv(ced));
	return 0;
}

static int timer8_clock_event_periodic(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for periodic clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);

	return 0;
}

static int timer8_clock_event_oneshot(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for oneshot clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, 0x10000);

	return 0;
}

static int timer8_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	BUG_ON(!clockevent_state_oneshot(ced));
	timer8_set_next(p, delta - 1);

	return 0;
}

static struct timer8_priv timer8_priv = {
	.ced = {
		.name = "h8300_8timer",
		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
		.rating = 200,
		.set_next_event = timer8_clock_event_next,
		.set_state_shutdown = timer8_clock_event_shutdown,
		.set_state_periodic = timer8_clock_event_periodic,
		.set_state_oneshot = timer8_clock_event_oneshot,
	},
};

static void __init h8300_8timer_init(struct device_node *node)
{
	void __iomem *base;
	int irq;
	struct clk *clk;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("failed to get clock for clockevent\n");
		return;
	}

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("failed to map registers for clockevent\n");
		goto free_clk;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (!irq) {
		pr_err("failed to get irq for clockevent\n");
		goto unmap_reg;
	}

	timer8_priv.mapbase = base;

	timer8_priv.rate = clk_get_rate(clk) / SCALE;
	if (!timer8_priv.rate) {
		pr_err("Failed to get rate for the clocksource\n");
		goto unmap_reg;
	}

	if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
			timer8_priv.ced.name, &timer8_priv) < 0) {
		pr_err("failed to request irq %d for clockevent\n", irq);
		goto unmap_reg;
	}

	clockevents_config_and_register(&timer8_priv.ced,
					timer8_priv.rate, 1, 0x0000ffff);

	return;
unmap_reg:
	iounmap(base);
free_clk:
	clk_put(clk);
}

CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
Commit	Line	Data
618b902d YS	1	/*
	2	* linux/arch/h8300/kernel/cpu/timer/timer8.c
	3	*
	4	* Yoshinori Sato <ysato@users.sourcefoge.jp>
	5	*
	6	* 8bit Timer driver
	7	*
	8	*/
	9
	10	#include <linux/errno.h>
618b902d YS	11	#include <linux/kernel.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/init.h>
618b902d	14	#include <linux/clockchips.h>
618b902d YS	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/of.h>
4633f4ca YS	18	#include <linux/of_address.h>
4633f4ca YS	19	#include <linux/of_irq.h>
618b902d	20
618b902d YS	21	#define _8TCR 0
	22	#define _8TCSR 2
	23	#define TCORA 4
	24	#define TCORB 6
	25	#define _8TCNT 8
	26
618b902d YS	27	#define FLAG_STARTED (1 << 3)
618b902d YS	28
4633f4ca YS	29	#define SCALE 64
4633f4ca YS	30
618b902d	31	struct timer8_priv {
618b902d	32	struct clock_event_device ced;
75160515	33	void __iomem *mapbase;
618b902d YS	34	unsigned long flags;
618b902d YS	35	unsigned int rate;
618b902d YS	36	};
618b902d YS	37
618b902d YS	38	static irqreturn_t timer8_interrupt(int irq, void *dev_id)
	39	{
	40	struct timer8_priv *p = dev_id;
	41
7053fdac	42	if (clockevent_state_oneshot(&p->ced))
75160515	43	writew(0x0000, p->mapbase + _8TCR);
7053fdac DL	44
7053fdac DL	45	p->ced.event_handler(&p->ced);
618b902d	46
f37632d1 YS	47	writeb(readb(p->mapbase + _8TCSR) & ~0x40,
	48	p->mapbase + _8TCSR);
	49
618b902d YS	50	return IRQ_HANDLED;
	51	}
	52
	53	static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
	54	{
618b902d	55	if (delta >= 0x10000)
8c09b7d6	56	pr_warn("delta out of range\n");
f37632d1 YS	57	writeb(readb(p->mapbase + _8TCR) & ~0x40, p->mapbase + _8TCR);
	58	writew(0, p->mapbase + _8TCNT);
	59	writew(delta, p->mapbase + TCORA);
75160515	60	writeb(readb(p->mapbase + _8TCR) \| 0x40, p->mapbase + _8TCR);
618b902d YS	61	}
	62
	63	static int timer8_enable(struct timer8_priv *p)
	64	{
75160515 DL	65	writew(0xffff, p->mapbase + TCORA);
	66	writew(0x0000, p->mapbase + _8TCNT);
	67	writew(0x0c02, p->mapbase + _8TCR);
618b902d YS	68
	69	return 0;
	70	}
	71
	72	static int timer8_start(struct timer8_priv *p)
	73	{
cce483e0	74	int ret;
618b902d	75
cce483e0 DL	76	if ((p->flags & FLAG_STARTED))
cce483e0 DL	77	return 0;
618b902d	78
cce483e0 DL	79	ret = timer8_enable(p);
	80	if (!ret)
	81	p->flags \|= FLAG_STARTED;
618b902d	82
618b902d YS	83	return ret;
	84	}
	85
	86	static void timer8_stop(struct timer8_priv *p)
	87	{
75160515	88	writew(0x0000, p->mapbase + _8TCR);
618b902d YS	89	}
	90
	91	static inline struct timer8_priv ced_to_priv(struct clock_event_device ced)
	92	{
	93	return container_of(ced, struct timer8_priv, ced);
	94	}
	95
1f058d52	96	static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
618b902d YS	97	{
	98	struct clock_event_device *ced = &p->ced;
	99
	100	timer8_start(p);
	101
	102	ced->shift = 32;
	103	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	104	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	105	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);
	106
1f058d52	107	timer8_set_next(p, delta);
618b902d YS	108	}
618b902d YS	109
fc2b2f5d VK	110	static int timer8_clock_event_shutdown(struct clock_event_device *ced)
	111	{
	112	timer8_stop(ced_to_priv(ced));
	113	return 0;
	114	}
	115
	116	static int timer8_clock_event_periodic(struct clock_event_device *ced)
618b902d YS	117	{
	118	struct timer8_priv *p = ced_to_priv(ced);
	119
4633f4ca	120	pr_info("%s: used for periodic clock events\n", ced->name);
fc2b2f5d	121	timer8_stop(p);
1f058d52	122	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
fc2b2f5d VK	123
	124	return 0;
	125	}
	126
	127	static int timer8_clock_event_oneshot(struct clock_event_device *ced)
	128	{
	129	struct timer8_priv *p = ced_to_priv(ced);
	130
4633f4ca	131	pr_info("%s: used for oneshot clock events\n", ced->name);
fc2b2f5d	132	timer8_stop(p);
1f058d52	133	timer8_clock_event_start(p, 0x10000);
fc2b2f5d VK	134
fc2b2f5d VK	135	return 0;
618b902d YS	136	}
	137
	138	static int timer8_clock_event_next(unsigned long delta,
	139	struct clock_event_device *ced)
	140	{
	141	struct timer8_priv *p = ced_to_priv(ced);
	142
fc2b2f5d	143	BUG_ON(!clockevent_state_oneshot(ced));
618b902d YS	144	timer8_set_next(p, delta - 1);
	145
	146	return 0;
	147	}
	148
4633f4ca YS	149	static struct timer8_priv timer8_priv = {
	150	.ced = {
	151	.name = "h8300_8timer",
	152	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	153	.rating = 200,
	154	.set_next_event = timer8_clock_event_next,
	155	.set_state_shutdown = timer8_clock_event_shutdown,
	156	.set_state_periodic = timer8_clock_event_periodic,
	157	.set_state_oneshot = timer8_clock_event_oneshot,
	158	},
	159	};
	160
	161	static void __init h8300_8timer_init(struct device_node *node)
618b902d	162	{
4633f4ca	163	void __iomem *base;
618b902d	164	int irq;
4633f4ca	165	struct clk *clk;
618b902d	166
4633f4ca YS	167	clk = of_clk_get(node, 0);
	168	if (IS_ERR(clk)) {
	169	pr_err("failed to get clock for clockevent\n");
	170	return;
	171	}
618b902d	172
4633f4ca YS	173	base = of_iomap(node, 0);
	174	if (!base) {
	175	pr_err("failed to map registers for clockevent\n");
	176	goto free_clk;
618b902d YS	177	}
618b902d YS	178
4633f4ca	179	irq = irq_of_parse_and_map(node, 0);
54a0cd5a	180	if (!irq) {
4633f4ca YS	181	pr_err("failed to get irq for clockevent\n");
4633f4ca YS	182	goto unmap_reg;
618b902d YS	183	}
618b902d YS	184
75160515	185	timer8_priv.mapbase = base;
cce483e0	186
6f2b611d YS	187	timer8_priv.rate = clk_get_rate(clk) / SCALE;
6f2b611d YS	188	if (!timer8_priv.rate) {
cce483e0 DL	189	pr_err("Failed to get rate for the clocksource\n");
	190	goto unmap_reg;
	191	}
618b902d	192
6f2b611d YS	193	if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
6f2b611d YS	194	timer8_priv.ced.name, &timer8_priv) < 0) {
4633f4ca YS	195	pr_err("failed to request irq %d for clockevent\n", irq);
4633f4ca YS	196	goto unmap_reg;
618b902d	197	}
cce483e0	198
6f2b611d YS	199	clockevents_config_and_register(&timer8_priv.ced,
6f2b611d YS	200	timer8_priv.rate, 1, 0x0000ffff);
4633f4ca	201
cce483e0	202	return;
4633f4ca YS	203	unmap_reg:
	204	iounmap(base);
	205	free_clk:
	206	clk_put(clk);
618b902d YS	207	}
618b902d YS	208
4633f4ca	209	CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);