[deliverable/linux.git] / drivers / clocksource / mips-gic-timer.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irqchip/mips-gic.h>
#include <linux/notifier.h>
#include <linux/of_irq.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/time.h>

static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
static int gic_timer_irq;
static unsigned int gic_frequency;

static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
{
	u64 cnt;
	int res;

	cnt = gic_read_count();
	cnt += (u64)delta;
	gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
	return res;
}

static void gic_set_clock_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	/* Nothing to do ...  */
}

static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *cd = dev_id;

	gic_write_compare(gic_read_compare());
	cd->event_handler(cd);
	return IRQ_HANDLED;
}

struct irqaction gic_compare_irqaction = {
	.handler = gic_compare_interrupt,
	.percpu_dev_id = &gic_clockevent_device,
	.flags = IRQF_PERCPU | IRQF_TIMER,
	.name = "timer",
};

static void gic_clockevent_cpu_init(struct clock_event_device *cd)
{
	unsigned int cpu = smp_processor_id();

	cd->name		= "MIPS GIC";
	cd->features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_C3STOP;

	cd->rating		= 350;
	cd->irq			= gic_timer_irq;
	cd->cpumask		= cpumask_of(cpu);
	cd->set_next_event	= gic_next_event;
	cd->set_mode		= gic_set_clock_mode;

	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);

	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
}

static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
{
	disable_percpu_irq(gic_timer_irq);
}

static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
				void *data)
{
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
		break;
	case CPU_DYING:
		gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block gic_cpu_nb = {
	.notifier_call = gic_cpu_notifier,
};

static int gic_clockevent_init(void)
{
	if (!cpu_has_counter || !gic_frequency)
		return -ENXIO;

	setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);

	register_cpu_notifier(&gic_cpu_nb);

	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));

	return 0;
}

static cycle_t gic_hpt_read(struct clocksource *cs)
{
	return gic_read_count();
}

static struct clocksource gic_clocksource = {
	.name	= "GIC",
	.read	= gic_hpt_read,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init __gic_clocksource_init(void)
{
	/* Set clocksource mask. */
	gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());

	/* Calculate a somewhat reasonable rating value. */
	gic_clocksource.rating = 200 + gic_frequency / 10000000;

	clocksource_register_hz(&gic_clocksource, gic_frequency);

	gic_clockevent_init();
}

void __init gic_clocksource_init(unsigned int frequency)
{
	gic_frequency = frequency;
	gic_timer_irq = MIPS_GIC_IRQ_BASE +
		GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);

	__gic_clocksource_init();
}

static void __init gic_clocksource_of_init(struct device_node *node)
{
	if (WARN_ON(!gic_present || !node->parent ||
		    !of_device_is_compatible(node->parent, "mti,gic")))
		return;

	if (of_property_read_u32(node, "clock-frequency", &gic_frequency)) {
		pr_err("GIC frequency not specified.\n");
		return;
	}
	gic_timer_irq = irq_of_parse_and_map(node, 0);
	if (!gic_timer_irq) {
		pr_err("GIC timer IRQ not specified.\n");
		return;
	}

	__gic_clocksource_init();
}
CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
		       gic_clocksource_of_init);
Commit	Line	Data
778eeb1b SH	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
	7	*/
a331ce63	8	#include <linux/clockchips.h>
e4752dbb	9	#include <linux/cpu.h>
778eeb1b	10	#include <linux/init.h>
a331ce63	11	#include <linux/interrupt.h>
4060bbe9	12	#include <linux/irqchip/mips-gic.h>
e4752dbb	13	#include <linux/notifier.h>
e12aa828	14	#include <linux/of_irq.h>
a331ce63 AB	15	#include <linux/percpu.h>
a331ce63 AB	16	#include <linux/smp.h>
dfa762e1	17	#include <linux/time.h>
778eeb1b	18
5fee56e0	19	static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
e4752dbb	20	static int gic_timer_irq;
b0854514	21	static unsigned int gic_frequency;
a331ce63 AB	22
	23	static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
	24	{
	25	u64 cnt;
	26	int res;
	27
	28	cnt = gic_read_count();
	29	cnt += (u64)delta;
	30	gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
	31	res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
	32	return res;
	33	}
	34
5fee56e0	35	static void gic_set_clock_mode(enum clock_event_mode mode,
a331ce63 AB	36	struct clock_event_device *evt)
	37	{
	38	/* Nothing to do ... */
	39	}
	40
5fee56e0	41	static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
a331ce63	42	{
f7ea3060	43	struct clock_event_device *cd = dev_id;
a331ce63 AB	44
a331ce63 AB	45	gic_write_compare(gic_read_compare());
a331ce63 AB	46	cd->event_handler(cd);
	47	return IRQ_HANDLED;
	48	}
	49
	50	struct irqaction gic_compare_irqaction = {
	51	.handler = gic_compare_interrupt,
f7ea3060	52	.percpu_dev_id = &gic_clockevent_device,
a331ce63 AB	53	.flags = IRQF_PERCPU \| IRQF_TIMER,
	54	.name = "timer",
	55	};
	56
e4752dbb	57	static void gic_clockevent_cpu_init(struct clock_event_device *cd)
a331ce63 AB	58	{
a331ce63 AB	59	unsigned int cpu = smp_processor_id();
a331ce63 AB	60
	61	cd->name = "MIPS GIC";
	62	cd->features = CLOCK_EVT_FEAT_ONESHOT \|
	63	CLOCK_EVT_FEAT_C3STOP;
	64
a45da565	65	cd->rating = 350;
e4752dbb	66	cd->irq = gic_timer_irq;
a331ce63 AB	67	cd->cpumask = cpumask_of(cpu);
	68	cd->set_next_event = gic_next_event;
	69	cd->set_mode = gic_set_clock_mode;
a331ce63	70
b695d8e6	71	clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
a331ce63	72
e4752dbb AB	73	enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
	74	}
	75
	76	static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
	77	{
	78	disable_percpu_irq(gic_timer_irq);
	79	}
	80
	81	static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
	82	void *data)
	83	{
	84	switch (action & ~CPU_TASKS_FROZEN) {
	85	case CPU_STARTING:
	86	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
	87	break;
	88	case CPU_DYING:
	89	gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
	90	break;
a331ce63 AB	91	}
a331ce63 AB	92
e4752dbb AB	93	return NOTIFY_OK;
	94	}
	95
	96	static struct notifier_block gic_cpu_nb = {
	97	.notifier_call = gic_cpu_notifier,
	98	};
	99
	100	static int gic_clockevent_init(void)
	101	{
	102	if (!cpu_has_counter \|\| !gic_frequency)
	103	return -ENXIO;
	104
e4752dbb AB	105	setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
	106
	107	register_cpu_notifier(&gic_cpu_nb);
	108
	109	gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
a331ce63 AB	110
	111	return 0;
	112	}
	113
778eeb1b SH	114	static cycle_t gic_hpt_read(struct clocksource *cs)
778eeb1b SH	115	{
dfa762e1	116	return gic_read_count();
778eeb1b SH	117	}
	118
	119	static struct clocksource gic_clocksource = {
	120	.name = "GIC",
	121	.read = gic_hpt_read,
	122	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	123	};
	124
e12aa828	125	static void __init __gic_clocksource_init(void)
778eeb1b	126	{
778eeb1b	127	/* Set clocksource mask. */
387904ff	128	gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
778eeb1b SH	129
778eeb1b SH	130	/* Calculate a somewhat reasonable rating value. */
e12aa828	131	gic_clocksource.rating = 200 + gic_frequency / 10000000;
778eeb1b	132
e12aa828	133	clocksource_register_hz(&gic_clocksource, gic_frequency);
e4752dbb AB	134
e4752dbb AB	135	gic_clockevent_init();
778eeb1b	136	}
e12aa828 AB	137
	138	void __init gic_clocksource_init(unsigned int frequency)
	139	{
	140	gic_frequency = frequency;
	141	gic_timer_irq = MIPS_GIC_IRQ_BASE +
	142	GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
	143
	144	__gic_clocksource_init();
	145	}
	146
	147	static void __init gic_clocksource_of_init(struct device_node *node)
	148	{
	149	if (WARN_ON(!gic_present \|\| !node->parent \|\|
	150	!of_device_is_compatible(node->parent, "mti,gic")))
	151	return;
	152
	153	if (of_property_read_u32(node, "clock-frequency", &gic_frequency)) {
	154	pr_err("GIC frequency not specified.\n");
	155	return;
	156	}
	157	gic_timer_irq = irq_of_parse_and_map(node, 0);
	158	if (!gic_timer_irq) {
	159	pr_err("GIC timer IRQ not specified.\n");
	160	return;
	161	}
	162
	163	__gic_clocksource_init();
	164	}
	165	CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
	166	gic_clocksource_of_init);