[deliverable/linux.git] / drivers / clocksource / moxart_timer.c

/*
 * MOXA ART SoCs timer handling.
 *
 * Copyright (C) 2013 Jonas Jensen
 *
 * Jonas Jensen <jonas.jensen@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/bitops.h>

#define TIMER1_BASE		0x00
#define TIMER2_BASE		0x10
#define TIMER3_BASE		0x20

#define REG_COUNT		0x0 /* writable */
#define REG_LOAD		0x4
#define REG_MATCH1		0x8
#define REG_MATCH2		0xC

#define TIMER_CR		0x30
#define TIMER_INTR_STATE	0x34
#define TIMER_INTR_MASK		0x38

/*
 * TIMER_CR flags:
 *
 * TIMEREG_CR_*_CLOCK	0: PCLK, 1: EXT1CLK
 * TIMEREG_CR_*_INT	overflow interrupt enable bit
 */
#define TIMEREG_CR_1_ENABLE	BIT(0)
#define TIMEREG_CR_1_CLOCK	BIT(1)
#define TIMEREG_CR_1_INT	BIT(2)
#define TIMEREG_CR_2_ENABLE	BIT(3)
#define TIMEREG_CR_2_CLOCK	BIT(4)
#define TIMEREG_CR_2_INT	BIT(5)
#define TIMEREG_CR_3_ENABLE	BIT(6)
#define TIMEREG_CR_3_CLOCK	BIT(7)
#define TIMEREG_CR_3_INT	BIT(8)
#define TIMEREG_CR_COUNT_UP	BIT(9)

#define TIMER1_ENABLE		(TIMEREG_CR_2_ENABLE | TIMEREG_CR_1_ENABLE)
#define TIMER1_DISABLE		(TIMEREG_CR_2_ENABLE)

static void __iomem *base;
static unsigned int clock_count_per_tick;

static int moxart_shutdown(struct clock_event_device *evt)
{
	writel(TIMER1_DISABLE, base + TIMER_CR);
	return 0;
}

static int moxart_set_oneshot(struct clock_event_device *evt)
{
	writel(TIMER1_DISABLE, base + TIMER_CR);
	writel(~0, base + TIMER1_BASE + REG_LOAD);
	return 0;
}

static int moxart_set_periodic(struct clock_event_device *evt)
{
	writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
	writel(TIMER1_ENABLE, base + TIMER_CR);
	return 0;
}

static int moxart_clkevt_next_event(unsigned long cycles,
				    struct clock_event_device *unused)
{
	u32 u;

	writel(TIMER1_DISABLE, base + TIMER_CR);

	u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;
	writel(u, base + TIMER1_BASE + REG_MATCH1);

	writel(TIMER1_ENABLE, base + TIMER_CR);

	return 0;
}

static struct clock_event_device moxart_clockevent = {
	.name			= "moxart_timer",
	.rating			= 200,
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown	= moxart_shutdown,
	.set_state_periodic	= moxart_set_periodic,
	.set_state_oneshot	= moxart_set_oneshot,
	.tick_resume		= moxart_set_oneshot,
	.set_next_event		= moxart_clkevt_next_event,
};

static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction moxart_timer_irq = {
	.name		= "moxart-timer",
	.flags		= IRQF_TIMER,
	.handler	= moxart_timer_interrupt,
	.dev_id		= &moxart_clockevent,
};

static int __init moxart_timer_init(struct device_node *node)
{
	int ret, irq;
	unsigned long pclk;
	struct clk *clk;

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("%s: of_iomap failed\n", node->full_name);
		return -ENXIO;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0) {
		pr_err("%s: irq_of_parse_and_map failed\n", node->full_name);
		return -EINVAL;
	}

	ret = setup_irq(irq, &moxart_timer_irq);
	if (ret) {
		pr_err("%s: setup_irq failed\n", node->full_name);
		return ret;
	}

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk))  {
		pr_err("%s: of_clk_get failed\n", node->full_name);
		return PTR_ERR(clk);
	}

	pclk = clk_get_rate(clk);

	ret = clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT,
				    "moxart_timer", pclk, 200, 32,
				    clocksource_mmio_readl_down);
	if (ret) {
		pr_err("%s: clocksource_mmio_init failed\n", node->full_name);
		return ret;
	}

	clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);

	writel(~0, base + TIMER2_BASE + REG_LOAD);
	writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR);

	moxart_clockevent.cpumask = cpumask_of(0);
	moxart_clockevent.irq = irq;

	/*
	 * documentation is not publicly available:
	 * min_delta / max_delta obtained by trial-and-error,
	 * max_delta 0xfffffffe should be ok because count
	 * register size is u32
	 */
	clockevents_config_and_register(&moxart_clockevent, pclk,
					0x4, 0xfffffffe);

	return 0;
}
CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);
Commit	Line	Data
07862c1c JJ	1	/*
	2	* MOXA ART SoCs timer handling.
	3	*
	4	* Copyright (C) 2013 Jonas Jensen
	5	*
	6	* Jonas Jensen <jonas.jensen@gmail.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/clockchips.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/irq.h>
	17	#include <linux/irqreturn.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/io.h>
	22	#include <linux/clocksource.h>
adf157eb	23	#include <linux/bitops.h>
07862c1c JJ	24
	25	#define TIMER1_BASE 0x00
	26	#define TIMER2_BASE 0x10
	27	#define TIMER3_BASE 0x20
	28
	29	#define REG_COUNT 0x0 /* writable */
	30	#define REG_LOAD 0x4
	31	#define REG_MATCH1 0x8
	32	#define REG_MATCH2 0xC
	33
	34	#define TIMER_CR 0x30
	35	#define TIMER_INTR_STATE 0x34
	36	#define TIMER_INTR_MASK 0x38
	37
	38	/*
	39	* TIMER_CR flags:
	40	*
	41	* TIMEREG_CR_*_CLOCK 0: PCLK, 1: EXT1CLK
	42	* TIMEREG_CR_*_INT overflow interrupt enable bit
	43	*/
	44	#define TIMEREG_CR_1_ENABLE BIT(0)
	45	#define TIMEREG_CR_1_CLOCK BIT(1)
	46	#define TIMEREG_CR_1_INT BIT(2)
	47	#define TIMEREG_CR_2_ENABLE BIT(3)
	48	#define TIMEREG_CR_2_CLOCK BIT(4)
	49	#define TIMEREG_CR_2_INT BIT(5)
	50	#define TIMEREG_CR_3_ENABLE BIT(6)
	51	#define TIMEREG_CR_3_CLOCK BIT(7)
	52	#define TIMEREG_CR_3_INT BIT(8)
	53	#define TIMEREG_CR_COUNT_UP BIT(9)
	54
	55	#define TIMER1_ENABLE (TIMEREG_CR_2_ENABLE \| TIMEREG_CR_1_ENABLE)
	56	#define TIMER1_DISABLE (TIMEREG_CR_2_ENABLE)
	57
	58	static void __iomem *base;
	59	static unsigned int clock_count_per_tick;
	60
37ae2471	61	static int moxart_shutdown(struct clock_event_device *evt)
07862c1c	62	{
37ae2471 VK	63	writel(TIMER1_DISABLE, base + TIMER_CR);
	64	return 0;
	65	}
	66
	67	static int moxart_set_oneshot(struct clock_event_device *evt)
	68	{
	69	writel(TIMER1_DISABLE, base + TIMER_CR);
	70	writel(~0, base + TIMER1_BASE + REG_LOAD);
	71	return 0;
	72	}
	73
	74	static int moxart_set_periodic(struct clock_event_device *evt)
	75	{
	76	writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD);
	77	writel(TIMER1_ENABLE, base + TIMER_CR);
	78	return 0;
07862c1c JJ	79	}
	80
	81	static int moxart_clkevt_next_event(unsigned long cycles,
	82	struct clock_event_device *unused)
	83	{
	84	u32 u;
	85
	86	writel(TIMER1_DISABLE, base + TIMER_CR);
	87
	88	u = readl(base + TIMER1_BASE + REG_COUNT) - cycles;
	89	writel(u, base + TIMER1_BASE + REG_MATCH1);
	90
	91	writel(TIMER1_ENABLE, base + TIMER_CR);
	92
	93	return 0;
	94	}
	95
	96	static struct clock_event_device moxart_clockevent = {
37ae2471 VK	97	.name = "moxart_timer",
	98	.rating = 200,
	99	.features = CLOCK_EVT_FEAT_PERIODIC \|
	100	CLOCK_EVT_FEAT_ONESHOT,
	101	.set_state_shutdown = moxart_shutdown,
	102	.set_state_periodic = moxart_set_periodic,
	103	.set_state_oneshot = moxart_set_oneshot,
	104	.tick_resume = moxart_set_oneshot,
	105	.set_next_event = moxart_clkevt_next_event,
07862c1c JJ	106	};
	107
	108	static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
	109	{
	110	struct clock_event_device *evt = dev_id;
	111	evt->event_handler(evt);
	112	return IRQ_HANDLED;
	113	}
	114
	115	static struct irqaction moxart_timer_irq = {
	116	.name = "moxart-timer",
	117	.flags = IRQF_TIMER,
	118	.handler = moxart_timer_interrupt,
	119	.dev_id = &moxart_clockevent,
	120	};
	121
b7357e65	122	static int __init moxart_timer_init(struct device_node *node)
07862c1c JJ	123	{
	124	int ret, irq;
	125	unsigned long pclk;
	126	struct clk *clk;
	127
	128	base = of_iomap(node, 0);
b7357e65 DL	129	if (!base) {
	130	pr_err("%s: of_iomap failed\n", node->full_name);
	131	return -ENXIO;
	132	}
07862c1c JJ	133
07862c1c JJ	134	irq = irq_of_parse_and_map(node, 0);
b7357e65 DL	135	if (irq <= 0) {
	136	pr_err("%s: irq_of_parse_and_map failed\n", node->full_name);
	137	return -EINVAL;
	138	}
07862c1c JJ	139
07862c1c JJ	140	ret = setup_irq(irq, &moxart_timer_irq);
b7357e65 DL	141	if (ret) {
	142	pr_err("%s: setup_irq failed\n", node->full_name);
	143	return ret;
	144	}
07862c1c JJ	145
07862c1c JJ	146	clk = of_clk_get(node, 0);
b7357e65 DL	147	if (IS_ERR(clk)) {
	148	pr_err("%s: of_clk_get failed\n", node->full_name);
	149	return PTR_ERR(clk);
	150	}
07862c1c JJ	151
	152	pclk = clk_get_rate(clk);
	153
b7357e65 DL	154	ret = clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT,
	155	"moxart_timer", pclk, 200, 32,
	156	clocksource_mmio_readl_down);
	157	if (ret) {
	158	pr_err("%s: clocksource_mmio_init failed\n", node->full_name);
	159	return ret;
	160	}
07862c1c JJ	161
	162	clock_count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
	163
	164	writel(~0, base + TIMER2_BASE + REG_LOAD);
	165	writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR);
	166
	167	moxart_clockevent.cpumask = cpumask_of(0);
	168	moxart_clockevent.irq = irq;
	169
	170	/*
	171	* documentation is not publicly available:
	172	* min_delta / max_delta obtained by trial-and-error,
	173	* max_delta 0xfffffffe should be ok because count
	174	* register size is u32
	175	*/
	176	clockevents_config_and_register(&moxart_clockevent, pclk,
	177	0x4, 0xfffffffe);
b7357e65 DL	178
b7357e65 DL	179	return 0;
07862c1c	180	}
177cf6e5	181	CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);