[deliverable/linux.git] / drivers / clocksource / pxa_timer.c

/*
 * arch/arm/mach-pxa/time.c
 *
 * PXA clocksource, clockevents, and OST interrupt handlers.
 * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
 *
 * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
 * by MontaVista Software, Inc.  (Nico, your code rocks!)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <asm/div64.h>

#define OSMR0		0x00	/* OS Timer 0 Match Register */
#define OSMR1		0x04	/* OS Timer 1 Match Register */
#define OSMR2		0x08	/* OS Timer 2 Match Register */
#define OSMR3		0x0C	/* OS Timer 3 Match Register */

#define OSCR		0x10	/* OS Timer Counter Register */
#define OSSR		0x14	/* OS Timer Status Register */
#define OWER		0x18	/* OS Timer Watchdog Enable Register */
#define OIER		0x1C	/* OS Timer Interrupt Enable Register */

#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
#define OSSR_M0		(1 << 0)	/* Match status channel 0 */

#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */

/*
 * This is PXA's sched_clock implementation. This has a resolution
 * of at least 308 ns and a maximum value of 208 days.
 *
 * The return value is guaranteed to be monotonic in that range as
 * long as there is always less than 582 seconds between successive
 * calls to sched_clock() which should always be the case in practice.
 */

#define timer_readl(reg) readl_relaxed(timer_base + (reg))
#define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))

static void __iomem *timer_base;

static u64 notrace pxa_read_sched_clock(void)
{
	return timer_readl(OSCR);
}


#define MIN_OSCR_DELTA 16

static irqreturn_t
pxa_ost0_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *c = dev_id;

	/* Disarm the compare/match, signal the event. */
	timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
	timer_writel(OSSR_M0, OSSR);
	c->event_handler(c);

	return IRQ_HANDLED;
}

static int
pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
{
	unsigned long next, oscr;

	timer_writel(timer_readl(OIER) | OIER_E0, OIER);
	next = timer_readl(OSCR) + delta;
	timer_writel(next, OSMR0);
	oscr = timer_readl(OSCR);

	return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
}

static void
pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
	switch (mode) {
	case CLOCK_EVT_MODE_ONESHOT:
		timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
		timer_writel(OSSR_M0, OSSR);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		/* initializing, released, or preparing for suspend */
		timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
		timer_writel(OSSR_M0, OSSR);
		break;

	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		break;
	}
}

#ifdef CONFIG_PM
static unsigned long osmr[4], oier, oscr;

static void pxa_timer_suspend(struct clock_event_device *cedev)
{
	osmr[0] = timer_readl(OSMR0);
	osmr[1] = timer_readl(OSMR1);
	osmr[2] = timer_readl(OSMR2);
	osmr[3] = timer_readl(OSMR3);
	oier = timer_readl(OIER);
	oscr = timer_readl(OSCR);
}

static void pxa_timer_resume(struct clock_event_device *cedev)
{
	/*
	 * Ensure that we have at least MIN_OSCR_DELTA between match
	 * register 0 and the OSCR, to guarantee that we will receive
	 * the one-shot timer interrupt.  We adjust OSMR0 in preference
	 * to OSCR to guarantee that OSCR is monotonically incrementing.
	 */
	if (osmr[0] - oscr < MIN_OSCR_DELTA)
		osmr[0] += MIN_OSCR_DELTA;

	timer_writel(osmr[0], OSMR0);
	timer_writel(osmr[1], OSMR1);
	timer_writel(osmr[2], OSMR2);
	timer_writel(osmr[3], OSMR3);
	timer_writel(oier, OIER);
	timer_writel(oscr, OSCR);
}
#else
#define pxa_timer_suspend NULL
#define pxa_timer_resume NULL
#endif

static struct clock_event_device ckevt_pxa_osmr0 = {
	.name		= "osmr0",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.set_next_event	= pxa_osmr0_set_next_event,
	.set_mode	= pxa_osmr0_set_mode,
	.suspend	= pxa_timer_suspend,
	.resume		= pxa_timer_resume,
};

static struct irqaction pxa_ost0_irq = {
	.name		= "ost0",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= pxa_ost0_interrupt,
	.dev_id		= &ckevt_pxa_osmr0,
};

static void pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
{
	timer_writel(0, OIER);
	timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);

	sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);

	ckevt_pxa_osmr0.cpumask = cpumask_of(0);

	setup_irq(irq, &pxa_ost0_irq);

	clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
			      32, clocksource_mmio_readl_up);
	clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
					MIN_OSCR_DELTA * 2, 0x7fffffff);
}

static void __init pxa_timer_dt_init(struct device_node *np)
{
	struct clk *clk;
	int irq;

	/* timer registers are shared with watchdog timer */
	timer_base = of_iomap(np, 0);
	if (!timer_base)
		panic("%s: unable to map resource\n", np->name);

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_crit("%s: unable to get clk\n", np->name);
		return;
	}
	clk_prepare_enable(clk);

	/* we are only interested in OS-timer0 irq */
	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0) {
		pr_crit("%s: unable to parse OS-timer0 irq\n", np->name);
		return;
	}

	pxa_timer_common_init(irq, clk_get_rate(clk));
}
CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);

/*
 * Legacy timer init for non device-tree boards.
 */
void __init pxa_timer_nodt_init(int irq, void __iomem *base,
	unsigned long clock_tick_rate)
{
	struct clk *clk;

	timer_base = base;
	clk = clk_get(NULL, "OSTIMER0");
	if (clk && !IS_ERR(clk))
		clk_prepare_enable(clk);
	else
		pr_crit("%s: unable to get clk\n", __func__);

	pxa_timer_common_init(irq, clock_tick_rate);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/arm/mach-pxa/time.c
	3	*
7bbb18c9 BG	4	* PXA clocksource, clockevents, and OST interrupt handlers.
	5	* Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
	6	*
	7	* Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
	8	* by MontaVista Software, Inc. (Nico, your code rocks!)
1da177e4 LT	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
1da177e4 LT	15	#include <linux/kernel.h>
1da177e4 LT	16	#include <linux/init.h>
1da177e4	17	#include <linux/interrupt.h>
ab5354c4	18	#include <linux/clk.h>
7bbb18c9	19	#include <linux/clockchips.h>
ab5354c4 RJ	20	#include <linux/of_address.h>
ab5354c4 RJ	21	#include <linux/of_irq.h>
38ff87f7	22	#include <linux/sched_clock.h>
7bbb18c9	23
6c3a1583	24	#include <asm/div64.h>
ab5354c4 RJ	25
	26	#define OSMR0 0x00 /* OS Timer 0 Match Register */
	27	#define OSMR1 0x04 /* OS Timer 1 Match Register */
	28	#define OSMR2 0x08 /* OS Timer 2 Match Register */
	29	#define OSMR3 0x0C /* OS Timer 3 Match Register */
	30
	31	#define OSCR 0x10 /* OS Timer Counter Register */
	32	#define OSSR 0x14 /* OS Timer Status Register */
	33	#define OWER 0x18 /* OS Timer Watchdog Enable Register */
	34	#define OIER 0x1C /* OS Timer Interrupt Enable Register */
	35
	36	#define OSSR_M3 (1 << 3) /* Match status channel 3 */
	37	#define OSSR_M2 (1 << 2) /* Match status channel 2 */
	38	#define OSSR_M1 (1 << 1) /* Match status channel 1 */
	39	#define OSSR_M0 (1 << 0) /* Match status channel 0 */
	40
	41	#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
1da177e4	42
6c3a1583 NP	43	/*
	44	* This is PXA's sched_clock implementation. This has a resolution
	45	* of at least 308 ns and a maximum value of 208 days.
	46	*
	47	* The return value is guaranteed to be monotonic in that range as
	48	* long as there is always less than 582 seconds between successive
	49	* calls to sched_clock() which should always be the case in practice.
	50	*/
	51
ab5354c4 RJ	52	#define timer_readl(reg) readl_relaxed(timer_base + (reg))
	53	#define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
	54
	55	static void __iomem *timer_base;
	56
364ed1e0	57	static u64 notrace pxa_read_sched_clock(void)
6c3a1583	58	{
ab5354c4	59	return timer_readl(OSCR);
6c3a1583 NP	60	}
	61
	62
a88264c2 RK	63	#define MIN_OSCR_DELTA 16
a88264c2 RK	64
1da177e4	65	static irqreturn_t
7bbb18c9	66	pxa_ost0_interrupt(int irq, void *dev_id)
1da177e4	67	{
7bbb18c9 BG	68	struct clock_event_device *c = dev_id;
7bbb18c9 BG	69
a88264c2	70	/* Disarm the compare/match, signal the event. */
ab5354c4 RJ	71	timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
ab5354c4 RJ	72	timer_writel(OSSR_M0, OSSR);
a88264c2	73	c->event_handler(c);
1da177e4 LT	74
	75	return IRQ_HANDLED;
	76	}
	77
7bbb18c9 BG	78	static int
	79	pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
	80	{
a602f0f2	81	unsigned long next, oscr;
7bbb18c9	82
ab5354c4 RJ	83	timer_writel(timer_readl(OIER) \| OIER_E0, OIER);
	84	next = timer_readl(OSCR) + delta;
	85	timer_writel(next, OSMR0);
	86	oscr = timer_readl(OSCR);
91bc51d8 RK	87
91bc51d8 RK	88	return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
7bbb18c9 BG	89	}
	90
	91	static void
	92	pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
	93	{
7bbb18c9	94	switch (mode) {
7bbb18c9	95	case CLOCK_EVT_MODE_ONESHOT:
ab5354c4 RJ	96	timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
ab5354c4 RJ	97	timer_writel(OSSR_M0, OSSR);
7bbb18c9 BG	98	break;
	99
	100	case CLOCK_EVT_MODE_UNUSED:
	101	case CLOCK_EVT_MODE_SHUTDOWN:
	102	/* initializing, released, or preparing for suspend */
ab5354c4 RJ	103	timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
ab5354c4 RJ	104	timer_writel(OSSR_M0, OSSR);
7bbb18c9	105	break;
df43309b RK	106
df43309b RK	107	case CLOCK_EVT_MODE_RESUME:
a88264c2	108	case CLOCK_EVT_MODE_PERIODIC:
df43309b	109	break;
7bbb18c9 BG	110	}
	111	}
	112
5b30d5bf SW	113	#ifdef CONFIG_PM
	114	static unsigned long osmr[4], oier, oscr;
	115
	116	static void pxa_timer_suspend(struct clock_event_device *cedev)
	117	{
ab5354c4 RJ	118	osmr[0] = timer_readl(OSMR0);
	119	osmr[1] = timer_readl(OSMR1);
	120	osmr[2] = timer_readl(OSMR2);
	121	osmr[3] = timer_readl(OSMR3);
	122	oier = timer_readl(OIER);
	123	oscr = timer_readl(OSCR);
5b30d5bf SW	124	}
	125
	126	static void pxa_timer_resume(struct clock_event_device *cedev)
	127	{
	128	/*
	129	* Ensure that we have at least MIN_OSCR_DELTA between match
	130	* register 0 and the OSCR, to guarantee that we will receive
	131	* the one-shot timer interrupt. We adjust OSMR0 in preference
	132	* to OSCR to guarantee that OSCR is monotonically incrementing.
	133	*/
	134	if (osmr[0] - oscr < MIN_OSCR_DELTA)
	135	osmr[0] += MIN_OSCR_DELTA;
	136
ab5354c4 RJ	137	timer_writel(osmr[0], OSMR0);
	138	timer_writel(osmr[1], OSMR1);
	139	timer_writel(osmr[2], OSMR2);
	140	timer_writel(osmr[3], OSMR3);
	141	timer_writel(oier, OIER);
	142	timer_writel(oscr, OSCR);
5b30d5bf SW	143	}
	144	#else
	145	#define pxa_timer_suspend NULL
	146	#define pxa_timer_resume NULL
	147	#endif
	148
7bbb18c9 BG	149	static struct clock_event_device ckevt_pxa_osmr0 = {
7bbb18c9 BG	150	.name = "osmr0",
a88264c2	151	.features = CLOCK_EVT_FEAT_ONESHOT,
7bbb18c9	152	.rating = 200,
7bbb18c9 BG	153	.set_next_event = pxa_osmr0_set_next_event,
7bbb18c9 BG	154	.set_mode = pxa_osmr0_set_mode,
5b30d5bf SW	155	.suspend = pxa_timer_suspend,
5b30d5bf SW	156	.resume = pxa_timer_resume,
1da177e4 LT	157	};
1da177e4 LT	158
7bbb18c9 BG	159	static struct irqaction pxa_ost0_irq = {
7bbb18c9 BG	160	.name = "ost0",
ed7936f9	161	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
7bbb18c9 BG	162	.handler = pxa_ost0_interrupt,
	163	.dev_id = &ckevt_pxa_osmr0,
	164	};
	165
ab5354c4	166	static void pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
1da177e4	167	{
ab5354c4 RJ	168	timer_writel(0, OIER);
ab5354c4 RJ	169	timer_writel(OSSR_M0 \| OSSR_M1 \| OSSR_M2 \| OSSR_M3, OSSR);
1da177e4	170
364ed1e0	171	sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);
6c3a1583	172
320ab2b0	173	ckevt_pxa_osmr0.cpumask = cpumask_of(0);
1da177e4	174
ab5354c4	175	setup_irq(irq, &pxa_ost0_irq);
5c53ff08	176
ab5354c4 RJ	177	clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
ab5354c4 RJ	178	32, clocksource_mmio_readl_up);
8d84981e	179	clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
ab5354c4 RJ	180	MIN_OSCR_DELTA * 2, 0x7fffffff);
	181	}
	182
	183	static void __init pxa_timer_dt_init(struct device_node *np)
	184	{
	185	struct clk *clk;
	186	int irq;
	187
	188	/* timer registers are shared with watchdog timer */
	189	timer_base = of_iomap(np, 0);
	190	if (!timer_base)
	191	panic("%s: unable to map resource\n", np->name);
	192
	193	clk = of_clk_get(np, 0);
	194	if (IS_ERR(clk)) {
	195	pr_crit("%s: unable to get clk\n", np->name);
	196	return;
	197	}
	198	clk_prepare_enable(clk);
	199
	200	/* we are only interested in OS-timer0 irq */
	201	irq = irq_of_parse_and_map(np, 0);
	202	if (irq <= 0) {
	203	pr_crit("%s: unable to parse OS-timer0 irq\n", np->name);
	204	return;
	205	}
	206
	207	pxa_timer_common_init(irq, clk_get_rate(clk));
	208	}
	209	CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
	210
	211	/*
	212	* Legacy timer init for non device-tree boards.
	213	*/
	214	void __init pxa_timer_nodt_init(int irq, void __iomem *base,
	215	unsigned long clock_tick_rate)
	216	{
	217	struct clk *clk;
	218
	219	timer_base = base;
	220	clk = clk_get(NULL, "OSTIMER0");
	221	if (clk && !IS_ERR(clk))
	222	clk_prepare_enable(clk);
	223	else
	224	pr_crit("%s: unable to get clk\n", __func__);
	225
	226	pxa_timer_common_init(irq, clock_tick_rate);
5c53ff08	227	}