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468b8c4c DL |
1 | /* |
2 | * Rockchip timer support | |
3 | * | |
4 | * Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/clk.h> | |
11 | #include <linux/clockchips.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
17 | ||
18 | #define TIMER_NAME "rk_timer" | |
19 | ||
20 | #define TIMER_LOAD_COUNT0 0x00 | |
21 | #define TIMER_LOAD_COUNT1 0x04 | |
22 | #define TIMER_CONTROL_REG 0x10 | |
23 | #define TIMER_INT_STATUS 0x18 | |
24 | ||
25 | #define TIMER_DISABLE 0x0 | |
26 | #define TIMER_ENABLE 0x1 | |
27 | #define TIMER_MODE_FREE_RUNNING (0 << 1) | |
28 | #define TIMER_MODE_USER_DEFINED_COUNT (1 << 1) | |
29 | #define TIMER_INT_UNMASK (1 << 2) | |
30 | ||
31 | struct bc_timer { | |
32 | struct clock_event_device ce; | |
33 | void __iomem *base; | |
34 | u32 freq; | |
35 | }; | |
36 | ||
37 | static struct bc_timer bc_timer; | |
38 | ||
39 | static inline struct bc_timer *rk_timer(struct clock_event_device *ce) | |
40 | { | |
41 | return container_of(ce, struct bc_timer, ce); | |
42 | } | |
43 | ||
44 | static inline void __iomem *rk_base(struct clock_event_device *ce) | |
45 | { | |
46 | return rk_timer(ce)->base; | |
47 | } | |
48 | ||
49 | static inline void rk_timer_disable(struct clock_event_device *ce) | |
50 | { | |
51 | writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG); | |
52 | dsb(); | |
53 | } | |
54 | ||
55 | static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags) | |
56 | { | |
57 | writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags, | |
58 | rk_base(ce) + TIMER_CONTROL_REG); | |
59 | dsb(); | |
60 | } | |
61 | ||
62 | static void rk_timer_update_counter(unsigned long cycles, | |
63 | struct clock_event_device *ce) | |
64 | { | |
65 | writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0); | |
66 | writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1); | |
67 | dsb(); | |
68 | } | |
69 | ||
70 | static void rk_timer_interrupt_clear(struct clock_event_device *ce) | |
71 | { | |
72 | writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS); | |
73 | dsb(); | |
74 | } | |
75 | ||
76 | static inline int rk_timer_set_next_event(unsigned long cycles, | |
77 | struct clock_event_device *ce) | |
78 | { | |
79 | rk_timer_disable(ce); | |
80 | rk_timer_update_counter(cycles, ce); | |
81 | rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT); | |
82 | return 0; | |
83 | } | |
84 | ||
99b3fa72 | 85 | static int rk_timer_shutdown(struct clock_event_device *ce) |
468b8c4c | 86 | { |
99b3fa72 VK |
87 | rk_timer_disable(ce); |
88 | return 0; | |
89 | } | |
90 | ||
91 | static int rk_timer_set_periodic(struct clock_event_device *ce) | |
92 | { | |
93 | rk_timer_disable(ce); | |
94 | rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce); | |
95 | rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING); | |
96 | return 0; | |
468b8c4c DL |
97 | } |
98 | ||
99 | static irqreturn_t rk_timer_interrupt(int irq, void *dev_id) | |
100 | { | |
101 | struct clock_event_device *ce = dev_id; | |
102 | ||
103 | rk_timer_interrupt_clear(ce); | |
104 | ||
99b3fa72 | 105 | if (clockevent_state_oneshot(ce)) |
468b8c4c DL |
106 | rk_timer_disable(ce); |
107 | ||
108 | ce->event_handler(ce); | |
109 | ||
110 | return IRQ_HANDLED; | |
111 | } | |
112 | ||
113 | static void __init rk_timer_init(struct device_node *np) | |
114 | { | |
115 | struct clock_event_device *ce = &bc_timer.ce; | |
116 | struct clk *timer_clk; | |
117 | struct clk *pclk; | |
118 | int ret, irq; | |
119 | ||
120 | bc_timer.base = of_iomap(np, 0); | |
121 | if (!bc_timer.base) { | |
122 | pr_err("Failed to get base address for '%s'\n", TIMER_NAME); | |
123 | return; | |
124 | } | |
125 | ||
126 | pclk = of_clk_get_by_name(np, "pclk"); | |
127 | if (IS_ERR(pclk)) { | |
128 | pr_err("Failed to get pclk for '%s'\n", TIMER_NAME); | |
129 | return; | |
130 | } | |
131 | ||
132 | if (clk_prepare_enable(pclk)) { | |
133 | pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME); | |
134 | return; | |
135 | } | |
136 | ||
137 | timer_clk = of_clk_get_by_name(np, "timer"); | |
138 | if (IS_ERR(timer_clk)) { | |
139 | pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME); | |
140 | return; | |
141 | } | |
142 | ||
143 | if (clk_prepare_enable(timer_clk)) { | |
144 | pr_err("Failed to enable timer clock\n"); | |
145 | return; | |
146 | } | |
147 | ||
148 | bc_timer.freq = clk_get_rate(timer_clk); | |
149 | ||
150 | irq = irq_of_parse_and_map(np, 0); | |
151 | if (irq == NO_IRQ) { | |
152 | pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME); | |
153 | return; | |
154 | } | |
155 | ||
156 | ce->name = TIMER_NAME; | |
157 | ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; | |
158 | ce->set_next_event = rk_timer_set_next_event; | |
99b3fa72 VK |
159 | ce->set_state_shutdown = rk_timer_shutdown; |
160 | ce->set_state_periodic = rk_timer_set_periodic; | |
468b8c4c DL |
161 | ce->irq = irq; |
162 | ce->cpumask = cpumask_of(0); | |
163 | ce->rating = 250; | |
164 | ||
165 | rk_timer_interrupt_clear(ce); | |
166 | rk_timer_disable(ce); | |
167 | ||
168 | ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce); | |
169 | if (ret) { | |
170 | pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret); | |
171 | return; | |
172 | } | |
173 | ||
174 | clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX); | |
175 | } | |
176 | CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init); |