[deliverable/linux.git] / drivers / clocksource / samsung_pwm_timer.c

/*
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com/
 *
 * samsung - Common hr-timer support (s3c and s5p)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <clocksource/samsung_pwm.h>

#include <asm/sched_clock.h>

/*
 * Clocksource driver
 */

#define REG_TCFG0			0x00
#define REG_TCFG1			0x04
#define REG_TCON			0x08
#define REG_TINT_CSTAT			0x44

#define REG_TCNTB(chan)			(0x0c + 12 * (chan))
#define REG_TCMPB(chan)			(0x10 + 12 * (chan))

#define TCFG0_PRESCALER_MASK		0xff
#define TCFG0_PRESCALER1_SHIFT		8

#define TCFG1_SHIFT(x)	  		((x) * 4)
#define TCFG1_MUX_MASK	  		0xf

#define TCON_START(chan)		(1 << (4 * (chan) + 0))
#define TCON_MANUALUPDATE(chan)		(1 << (4 * (chan) + 1))
#define TCON_INVERT(chan)		(1 << (4 * (chan) + 2))
#define TCON_AUTORELOAD(chan)		(1 << (4 * (chan) + 3))

DEFINE_SPINLOCK(samsung_pwm_lock);
EXPORT_SYMBOL(samsung_pwm_lock);

struct samsung_pwm_clocksource {
	void __iomem *base;
	unsigned int irq[SAMSUNG_PWM_NUM];
	struct samsung_pwm_variant variant;

	struct clk *timerclk;

	unsigned int event_id;
	unsigned int source_id;
	unsigned int tcnt_max;
	unsigned int tscaler_div;
	unsigned int tdiv;

	unsigned long clock_count_per_tick;
};

static struct samsung_pwm_clocksource pwm;

static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
{
	unsigned long flags;
	u8 shift = 0;
	u32 reg;

	if (channel >= 2)
		shift = TCFG0_PRESCALER1_SHIFT;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG0);
	reg &= ~(TCFG0_PRESCALER_MASK << shift);
	reg |= (prescale - 1) << shift;
	writel(reg, pwm.base + REG_TCFG0);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
{
	u8 shift = TCFG1_SHIFT(channel);
	unsigned long flags;
	u32 reg;
	u8 bits;

	bits = (fls(divisor) - 1) - pwm.variant.div_base;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	reg = readl(pwm.base + REG_TCFG1);
	reg &= ~(TCFG1_MUX_MASK << shift);
	reg |= bits << shift;
	writel(reg, pwm.base + REG_TCFG1);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_stop(unsigned int channel)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);
	tcon &= ~TCON_START(channel);
	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
{
	unsigned long tcon;
	unsigned long flags;
	unsigned int tcon_chan = channel;

	if (tcon_chan > 0)
		++tcon_chan;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);

	tcnt--;

	tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
	tcon |= TCON_MANUALUPDATE(tcon_chan);

	__raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
	__raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static void samsung_time_start(unsigned int channel, bool periodic)
{
	unsigned long tcon;
	unsigned long flags;

	if (channel > 0)
		++channel;

	spin_lock_irqsave(&samsung_pwm_lock, flags);

	tcon = __raw_readl(pwm.base + REG_TCON);

	tcon &= ~TCON_MANUALUPDATE(channel);
	tcon |= TCON_START(channel);

	if (periodic)
		tcon |= TCON_AUTORELOAD(channel);
	else
		tcon &= ~TCON_AUTORELOAD(channel);

	__raw_writel(tcon, pwm.base + REG_TCON);

	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}

static int samsung_set_next_event(unsigned long cycles,
				struct clock_event_device *evt)
{
	samsung_time_setup(pwm.event_id, cycles);
	samsung_time_start(pwm.event_id, false);

	return 0;
}

static void samsung_timer_resume(void)
{
	/* event timer restart */
	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick);
	samsung_time_start(pwm.event_id, true);

	/* source timer restart */
	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);
}

static void samsung_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	samsung_time_stop(pwm.event_id);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick);
		samsung_time_start(pwm.event_id, true);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		break;

	case CLOCK_EVT_MODE_RESUME:
		samsung_timer_resume();
		break;
	}
}

static struct clock_event_device time_event_device = {
	.name		= "samsung_event_timer",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 200,
	.set_next_event	= samsung_set_next_event,
	.set_mode	= samsung_set_mode,
};

static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction samsung_clock_event_irq = {
	.name		= "samsung_time_irq",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= samsung_clock_event_isr,
	.dev_id		= &time_event_device,
};

static void __init samsung_clockevent_init(void)
{
	unsigned long pclk;
	unsigned long clock_rate;
	unsigned int irq_number;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
	pwm.clock_count_per_tick = clock_rate / HZ;

	time_event_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);

	irq_number = pwm.irq[pwm.event_id];
	setup_irq(irq_number, &samsung_clock_event_irq);

	if (pwm.variant.has_tint_cstat) {
		u32 mask = (1 << pwm.event_id);
		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
	}
}

static void __iomem *samsung_timer_reg(void)
{
	switch (pwm.source_id) {
	case 0:
	case 1:
	case 2:
	case 3:
		return pwm.base + pwm.source_id * 0x0c + 0x14;

	case 4:
		return pwm.base + 0x40;

	default:
		BUG();
	}
}

/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel. We accept that
 * this wraps around for now, since it is just a relative time
 * stamp. (Inspired by U300 implementation.)
 */
static u32 notrace samsung_read_sched_clock(void)
{
	void __iomem *reg = samsung_timer_reg();

	if (!reg)
		return 0;

	return ~__raw_readl(reg);
}

static void __init samsung_clocksource_init(void)
{
	void __iomem *reg = samsung_timer_reg();
	unsigned long pclk;
	unsigned long clock_rate;
	int ret;

	pclk = clk_get_rate(pwm.timerclk);

	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);

	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);

	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
	samsung_time_start(pwm.source_id, true);

	setup_sched_clock(samsung_read_sched_clock,
						pwm.variant.bits, clock_rate);

	ret = clocksource_mmio_init(reg, "samsung_clocksource_timer",
					clock_rate, 250, pwm.variant.bits,
					clocksource_mmio_readl_down);
	if (ret)
		panic("samsung_clocksource_timer: can't register clocksource\n");
}

static void __init samsung_timer_resources(void)
{
	pwm.timerclk = clk_get(NULL, "timers");
	if (IS_ERR(pwm.timerclk))
		panic("failed to get timers clock for timer");

	clk_prepare_enable(pwm.timerclk);

	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	if (pwm.variant.bits == 16) {
		pwm.tscaler_div = 25;
		pwm.tdiv = 2;
	} else {
		pwm.tscaler_div = 2;
		pwm.tdiv = 1;
	}
}

/*
 * PWM master driver
 */
static void __init samsung_pwm_clocksource_init(void)
{
	u8 mask;
	int channel;

	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
	channel = fls(mask) - 1;
	if (channel < 0)
		panic("failed to find PWM channel for clocksource");
	pwm.source_id = channel;

	mask &= ~(1 << channel);
	channel = fls(mask) - 1;
	if (channel < 0)
		panic("failed to find PWM channel for clock event");
	pwm.event_id = channel;

	samsung_timer_resources();
	samsung_clockevent_init();
	samsung_clocksource_init();
}

static void __init samsung_pwm_alloc(struct device_node *np,
				     const struct samsung_pwm_variant *variant)
{
	struct resource res;
	struct property *prop;
	const __be32 *cur;
	u32 val;
	int i;

	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
		pwm.irq[i] = irq_of_parse_and_map(np, i);

	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
		if (val >= SAMSUNG_PWM_NUM) {
			pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
								__func__);
			continue;
		}
		pwm.variant.output_mask |= 1 << val;
	}

	of_address_to_resource(np, 0, &res);
	if (!request_mem_region(res.start,
				resource_size(&res), "samsung-pwm")) {
		pr_err("%s: failed to request IO mem region\n", __func__);
		return;
	}

	pwm.base = ioremap(res.start, resource_size(&res));
	if (!pwm.base) {
		pr_err("%s: failed to map PWM registers\n", __func__);
		release_mem_region(res.start, resource_size(&res));
		return;
	}

	samsung_pwm_clocksource_init();
}

static const struct samsung_pwm_variant s3c24xx_variant = {
	.bits		= 16,
	.div_base	= 1,
	.has_tint_cstat	= false,
	.tclk_mask	= (1 << 4),
};

static void __init s3c2410_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s3c24xx_variant);
}
CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);

static const struct samsung_pwm_variant s3c64xx_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 7) | (1 << 6) | (1 << 5),
};

static void __init s3c64xx_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s3c64xx_variant);
}
CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p64x0_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= 0,
};

static void __init s5p64x0_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s5p64x0_variant);
}
CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);

static const struct samsung_pwm_variant s5p_variant = {
	.bits		= 32,
	.div_base	= 0,
	.has_tint_cstat	= true,
	.tclk_mask	= (1 << 5),
};

static void __init s5p_pwm_clocksource_init(struct device_node *np)
{
	samsung_pwm_alloc(np, &s5p_variant);
}
CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
Commit	Line	Data
f1189989 TF	1	/*
	2	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com/
	4	*
	5	* samsung - Common hr-timer support (s3c and s5p)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/interrupt.h>
	13	#include <linux/irq.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/clockchips.h>
	17	#include <linux/list.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/slab.h>
	24
	25	#include <clocksource/samsung_pwm.h>
	26
	27	#include <asm/sched_clock.h>
	28
	29	/*
	30	* Clocksource driver
	31	*/
	32
	33	#define REG_TCFG0 0x00
	34	#define REG_TCFG1 0x04
	35	#define REG_TCON 0x08
	36	#define REG_TINT_CSTAT 0x44
	37
	38	#define REG_TCNTB(chan) (0x0c + 12 * (chan))
	39	#define REG_TCMPB(chan) (0x10 + 12 * (chan))
	40
	41	#define TCFG0_PRESCALER_MASK 0xff
	42	#define TCFG0_PRESCALER1_SHIFT 8
	43
	44	#define TCFG1_SHIFT(x) ((x) * 4)
	45	#define TCFG1_MUX_MASK 0xf
	46
	47	#define TCON_START(chan) (1 << (4 * (chan) + 0))
	48	#define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1))
	49	#define TCON_INVERT(chan) (1 << (4 * (chan) + 2))
	50	#define TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
	51
7aac482e TF	52	DEFINE_SPINLOCK(samsung_pwm_lock);
	53	EXPORT_SYMBOL(samsung_pwm_lock);
	54
030c2a1e TF	55	struct samsung_pwm_clocksource {
	56	void __iomem *base;
	57	unsigned int irq[SAMSUNG_PWM_NUM];
	58	struct samsung_pwm_variant variant;
	59
	60	struct clk *timerclk;
	61
f1189989 TF	62	unsigned int event_id;
	63	unsigned int source_id;
	64	unsigned int tcnt_max;
	65	unsigned int tscaler_div;
	66	unsigned int tdiv;
030c2a1e TF	67
030c2a1e TF	68	unsigned long clock_count_per_tick;
f1189989 TF	69	};
f1189989 TF	70
030c2a1e	71	static struct samsung_pwm_clocksource pwm;
f1189989	72
030c2a1e	73	static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
f1189989 TF	74	{
	75	unsigned long flags;
	76	u8 shift = 0;
	77	u32 reg;
	78
	79	if (channel >= 2)
	80	shift = TCFG0_PRESCALER1_SHIFT;
	81
7aac482e	82	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	83
030c2a1e	84	reg = readl(pwm.base + REG_TCFG0);
f1189989 TF	85	reg &= ~(TCFG0_PRESCALER_MASK << shift);
f1189989 TF	86	reg \|= (prescale - 1) << shift;
030c2a1e	87	writel(reg, pwm.base + REG_TCFG0);
f1189989	88
7aac482e	89	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	90	}
f1189989 TF	91
030c2a1e	92	static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
f1189989 TF	93	{
	94	u8 shift = TCFG1_SHIFT(channel);
	95	unsigned long flags;
	96	u32 reg;
	97	u8 bits;
	98
030c2a1e	99	bits = (fls(divisor) - 1) - pwm.variant.div_base;
f1189989	100
7aac482e	101	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	102
030c2a1e	103	reg = readl(pwm.base + REG_TCFG1);
f1189989 TF	104	reg &= ~(TCFG1_MUX_MASK << shift);
f1189989 TF	105	reg \|= bits << shift;
030c2a1e	106	writel(reg, pwm.base + REG_TCFG1);
f1189989	107
7aac482e	108	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	109	}
	110
	111	static void samsung_time_stop(unsigned int channel)
	112	{
	113	unsigned long tcon;
	114	unsigned long flags;
	115
	116	if (channel > 0)
	117	++channel;
	118
7aac482e	119	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	120
030c2a1e	121	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989	122	tcon &= ~TCON_START(channel);
030c2a1e	123	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	124
7aac482e	125	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	126	}
	127
	128	static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
	129	{
	130	unsigned long tcon;
	131	unsigned long flags;
	132	unsigned int tcon_chan = channel;
	133
	134	if (tcon_chan > 0)
	135	++tcon_chan;
	136
7aac482e	137	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	138
030c2a1e	139	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989 TF	140
	141	tcnt--;
	142
	143	tcon &= ~(TCON_START(tcon_chan) \| TCON_AUTORELOAD(tcon_chan));
	144	tcon \|= TCON_MANUALUPDATE(tcon_chan);
	145
030c2a1e TF	146	__raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
	147	__raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
	148	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	149
7aac482e	150	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	151	}
	152
	153	static void samsung_time_start(unsigned int channel, bool periodic)
	154	{
	155	unsigned long tcon;
	156	unsigned long flags;
	157
	158	if (channel > 0)
	159	++channel;
	160
7aac482e	161	spin_lock_irqsave(&samsung_pwm_lock, flags);
f1189989	162
030c2a1e	163	tcon = __raw_readl(pwm.base + REG_TCON);
f1189989 TF	164
	165	tcon &= ~TCON_MANUALUPDATE(channel);
	166	tcon \|= TCON_START(channel);
	167
	168	if (periodic)
	169	tcon \|= TCON_AUTORELOAD(channel);
	170	else
	171	tcon &= ~TCON_AUTORELOAD(channel);
	172
030c2a1e	173	__raw_writel(tcon, pwm.base + REG_TCON);
f1189989	174
7aac482e	175	spin_unlock_irqrestore(&samsung_pwm_lock, flags);
f1189989 TF	176	}
	177
	178	static int samsung_set_next_event(unsigned long cycles,
	179	struct clock_event_device *evt)
	180	{
030c2a1e TF	181	samsung_time_setup(pwm.event_id, cycles);
030c2a1e TF	182	samsung_time_start(pwm.event_id, false);
f1189989 TF	183
	184	return 0;
	185	}
	186
	187	static void samsung_timer_resume(void)
	188	{
	189	/* event timer restart */
030c2a1e TF	190	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick);
030c2a1e TF	191	samsung_time_start(pwm.event_id, true);
f1189989 TF	192
f1189989 TF	193	/* source timer restart */
030c2a1e TF	194	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	195	samsung_time_start(pwm.source_id, true);
f1189989 TF	196	}
	197
	198	static void samsung_set_mode(enum clock_event_mode mode,
	199	struct clock_event_device *evt)
	200	{
030c2a1e	201	samsung_time_stop(pwm.event_id);
f1189989 TF	202
	203	switch (mode) {
	204	case CLOCK_EVT_MODE_PERIODIC:
030c2a1e TF	205	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick);
030c2a1e TF	206	samsung_time_start(pwm.event_id, true);
f1189989 TF	207	break;
	208
	209	case CLOCK_EVT_MODE_ONESHOT:
	210	break;
	211
	212	case CLOCK_EVT_MODE_UNUSED:
	213	case CLOCK_EVT_MODE_SHUTDOWN:
	214	break;
	215
	216	case CLOCK_EVT_MODE_RESUME:
	217	samsung_timer_resume();
	218	break;
	219	}
	220	}
	221
	222	static struct clock_event_device time_event_device = {
	223	.name = "samsung_event_timer",
	224	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	225	.rating = 200,
	226	.set_next_event = samsung_set_next_event,
	227	.set_mode = samsung_set_mode,
	228	};
	229
	230	static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
	231	{
	232	struct clock_event_device *evt = dev_id;
	233
030c2a1e TF	234	if (pwm.variant.has_tint_cstat) {
	235	u32 mask = (1 << pwm.event_id);
	236	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	237	}
	238
	239	evt->event_handler(evt);
	240
	241	return IRQ_HANDLED;
	242	}
	243
	244	static struct irqaction samsung_clock_event_irq = {
	245	.name = "samsung_time_irq",
	246	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
	247	.handler = samsung_clock_event_isr,
	248	.dev_id = &time_event_device,
	249	};
	250
	251	static void __init samsung_clockevent_init(void)
	252	{
	253	unsigned long pclk;
	254	unsigned long clock_rate;
	255	unsigned int irq_number;
	256
030c2a1e	257	pclk = clk_get_rate(pwm.timerclk);
f1189989	258
030c2a1e TF	259	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
030c2a1e TF	260	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
f1189989	261
030c2a1e TF	262	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
030c2a1e TF	263	pwm.clock_count_per_tick = clock_rate / HZ;
f1189989 TF	264
	265	time_event_device.cpumask = cpumask_of(0);
	266	clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
	267
030c2a1e	268	irq_number = pwm.irq[pwm.event_id];
f1189989 TF	269	setup_irq(irq_number, &samsung_clock_event_irq);
f1189989 TF	270
030c2a1e TF	271	if (pwm.variant.has_tint_cstat) {
	272	u32 mask = (1 << pwm.event_id);
	273	writel(mask \| (mask << 5), pwm.base + REG_TINT_CSTAT);
f1189989 TF	274	}
	275	}
	276
	277	static void __iomem *samsung_timer_reg(void)
	278	{
030c2a1e	279	switch (pwm.source_id) {
f1189989 TF	280	case 0:
	281	case 1:
	282	case 2:
	283	case 3:
030c2a1e	284	return pwm.base + pwm.source_id * 0x0c + 0x14;
f1189989 TF	285
f1189989 TF	286	case 4:
030c2a1e	287	return pwm.base + 0x40;
f1189989 TF	288
	289	default:
	290	BUG();
	291	}
	292	}
	293
	294	/*
	295	* Override the global weak sched_clock symbol with this
	296	* local implementation which uses the clocksource to get some
	297	* better resolution when scheduling the kernel. We accept that
	298	* this wraps around for now, since it is just a relative time
	299	* stamp. (Inspired by U300 implementation.)
	300	*/
	301	static u32 notrace samsung_read_sched_clock(void)
	302	{
	303	void __iomem *reg = samsung_timer_reg();
	304
	305	if (!reg)
	306	return 0;
	307
	308	return ~__raw_readl(reg);
	309	}
	310
	311	static void __init samsung_clocksource_init(void)
	312	{
	313	void __iomem *reg = samsung_timer_reg();
	314	unsigned long pclk;
	315	unsigned long clock_rate;
	316	int ret;
	317
030c2a1e	318	pclk = clk_get_rate(pwm.timerclk);
f1189989	319
030c2a1e TF	320	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
030c2a1e TF	321	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
f1189989	322
030c2a1e	323	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
f1189989	324
030c2a1e TF	325	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
030c2a1e TF	326	samsung_time_start(pwm.source_id, true);
f1189989 TF	327
f1189989 TF	328	setup_sched_clock(samsung_read_sched_clock,
030c2a1e	329	pwm.variant.bits, clock_rate);
f1189989 TF	330
f1189989 TF	331	ret = clocksource_mmio_init(reg, "samsung_clocksource_timer",
030c2a1e	332	clock_rate, 250, pwm.variant.bits,
f1189989 TF	333	clocksource_mmio_readl_down);
	334	if (ret)
	335	panic("samsung_clocksource_timer: can't register clocksource\n");
	336	}
	337
	338	static void __init samsung_timer_resources(void)
	339	{
030c2a1e TF	340	pwm.timerclk = clk_get(NULL, "timers");
030c2a1e TF	341	if (IS_ERR(pwm.timerclk))
f1189989 TF	342	panic("failed to get timers clock for timer");
f1189989 TF	343
030c2a1e	344	clk_prepare_enable(pwm.timerclk);
f1189989	345
030c2a1e TF	346	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
	347	if (pwm.variant.bits == 16) {
	348	pwm.tscaler_div = 25;
	349	pwm.tdiv = 2;
f1189989	350	} else {
030c2a1e TF	351	pwm.tscaler_div = 2;
030c2a1e TF	352	pwm.tdiv = 1;
f1189989 TF	353	}
	354	}
	355
	356	/*
	357	* PWM master driver
	358	*/
	359	static void __init samsung_pwm_clocksource_init(void)
	360	{
	361	u8 mask;
	362	int channel;
	363
030c2a1e	364	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
f1189989 TF	365	channel = fls(mask) - 1;
	366	if (channel < 0)
	367	panic("failed to find PWM channel for clocksource");
030c2a1e	368	pwm.source_id = channel;
f1189989 TF	369
	370	mask &= ~(1 << channel);
	371	channel = fls(mask) - 1;
	372	if (channel < 0)
	373	panic("failed to find PWM channel for clock event");
030c2a1e	374	pwm.event_id = channel;
f1189989 TF	375
	376	samsung_timer_resources();
	377	samsung_clockevent_init();
	378	samsung_clocksource_init();
	379	}
	380
	381	static void __init samsung_pwm_alloc(struct device_node *np,
	382	const struct samsung_pwm_variant *variant)
	383	{
	384	struct resource res;
	385	struct property *prop;
	386	const __be32 *cur;
	387	u32 val;
	388	int i;
	389
030c2a1e	390	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
f1189989	391	for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
030c2a1e	392	pwm.irq[i] = irq_of_parse_and_map(np, i);
f1189989 TF	393
	394	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
	395	if (val >= SAMSUNG_PWM_NUM) {
	396	pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
	397	__func__);
	398	continue;
	399	}
030c2a1e	400	pwm.variant.output_mask \|= 1 << val;
f1189989 TF	401	}
	402
	403	of_address_to_resource(np, 0, &res);
	404	if (!request_mem_region(res.start,
	405	resource_size(&res), "samsung-pwm")) {
	406	pr_err("%s: failed to request IO mem region\n", __func__);
	407	return;
	408	}
	409
030c2a1e TF	410	pwm.base = ioremap(res.start, resource_size(&res));
030c2a1e TF	411	if (!pwm.base) {
f1189989 TF	412	pr_err("%s: failed to map PWM registers\n", __func__);
	413	release_mem_region(res.start, resource_size(&res));
	414	return;
	415	}
	416
	417	samsung_pwm_clocksource_init();
	418	}
	419
	420	static const struct samsung_pwm_variant s3c24xx_variant = {
	421	.bits = 16,
	422	.div_base = 1,
	423	.has_tint_cstat = false,
	424	.tclk_mask = (1 << 4),
	425	};
	426
	427	static void __init s3c2410_pwm_clocksource_init(struct device_node *np)
	428	{
	429	samsung_pwm_alloc(np, &s3c24xx_variant);
	430	}
	431	CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
	432
	433	static const struct samsung_pwm_variant s3c64xx_variant = {
	434	.bits = 32,
	435	.div_base = 0,
	436	.has_tint_cstat = true,
	437	.tclk_mask = (1 << 7) \| (1 << 6) \| (1 << 5),
	438	};
	439
	440	static void __init s3c64xx_pwm_clocksource_init(struct device_node *np)
	441	{
	442	samsung_pwm_alloc(np, &s3c64xx_variant);
	443	}
	444	CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
	445
	446	static const struct samsung_pwm_variant s5p64x0_variant = {
	447	.bits = 32,
	448	.div_base = 0,
	449	.has_tint_cstat = true,
	450	.tclk_mask = 0,
	451	};
	452
	453	static void __init s5p64x0_pwm_clocksource_init(struct device_node *np)
	454	{
	455	samsung_pwm_alloc(np, &s5p64x0_variant);
	456	}
	457	CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
	458
	459	static const struct samsung_pwm_variant s5p_variant = {
	460	.bits = 32,
	461	.div_base = 0,
	462	.has_tint_cstat = true,
	463	.tclk_mask = (1 << 5),
	464	};
	465
	466	static void __init s5p_pwm_clocksource_init(struct device_node *np)
	467	{
	468	samsung_pwm_alloc(np, &s5p_variant);
	469	}
	470	CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);