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3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
3fb1b6ad MD |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/err.h> | |
29 | #include <linux/clocksource.h> | |
30 | #include <linux/clockchips.h> | |
46a12f74 | 31 | #include <linux/sh_timer.h> |
3fb1b6ad MD |
32 | |
33 | struct sh_cmt_priv { | |
34 | void __iomem *mapbase; | |
35 | struct clk *clk; | |
36 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
37 | unsigned long overflow_bit; | |
38 | unsigned long clear_bits; | |
39 | struct irqaction irqaction; | |
40 | struct platform_device *pdev; | |
41 | ||
42 | unsigned long flags; | |
f6431732 | 43 | unsigned long flags_suspend; |
3fb1b6ad MD |
44 | unsigned long match_value; |
45 | unsigned long next_match_value; | |
46 | unsigned long max_match_value; | |
47 | unsigned long rate; | |
48 | spinlock_t lock; | |
49 | struct clock_event_device ced; | |
19bdc9d0 | 50 | struct clocksource cs; |
3fb1b6ad MD |
51 | unsigned long total_cycles; |
52 | }; | |
53 | ||
54 | static DEFINE_SPINLOCK(sh_cmt_lock); | |
55 | ||
56 | #define CMSTR -1 /* shared register */ | |
57 | #define CMCSR 0 /* channel register */ | |
58 | #define CMCNT 1 /* channel register */ | |
59 | #define CMCOR 2 /* channel register */ | |
60 | ||
61 | static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr) | |
62 | { | |
46a12f74 | 63 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
3fb1b6ad MD |
64 | void __iomem *base = p->mapbase; |
65 | unsigned long offs; | |
66 | ||
67 | if (reg_nr == CMSTR) { | |
68 | offs = 0; | |
69 | base -= cfg->channel_offset; | |
70 | } else | |
71 | offs = reg_nr; | |
72 | ||
73 | if (p->width == 16) | |
74 | offs <<= 1; | |
75 | else { | |
76 | offs <<= 2; | |
77 | if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) | |
78 | return ioread32(base + offs); | |
79 | } | |
80 | ||
81 | return ioread16(base + offs); | |
82 | } | |
83 | ||
84 | static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr, | |
85 | unsigned long value) | |
86 | { | |
46a12f74 | 87 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
3fb1b6ad MD |
88 | void __iomem *base = p->mapbase; |
89 | unsigned long offs; | |
90 | ||
91 | if (reg_nr == CMSTR) { | |
92 | offs = 0; | |
93 | base -= cfg->channel_offset; | |
94 | } else | |
95 | offs = reg_nr; | |
96 | ||
97 | if (p->width == 16) | |
98 | offs <<= 1; | |
99 | else { | |
100 | offs <<= 2; | |
101 | if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) { | |
102 | iowrite32(value, base + offs); | |
103 | return; | |
104 | } | |
105 | } | |
106 | ||
107 | iowrite16(value, base + offs); | |
108 | } | |
109 | ||
110 | static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p, | |
111 | int *has_wrapped) | |
112 | { | |
113 | unsigned long v1, v2, v3; | |
5b644c7a MD |
114 | int o1, o2; |
115 | ||
116 | o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit; | |
3fb1b6ad MD |
117 | |
118 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
119 | do { | |
5b644c7a | 120 | o2 = o1; |
3fb1b6ad MD |
121 | v1 = sh_cmt_read(p, CMCNT); |
122 | v2 = sh_cmt_read(p, CMCNT); | |
123 | v3 = sh_cmt_read(p, CMCNT); | |
5b644c7a MD |
124 | o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit; |
125 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) | |
126 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 127 | |
5b644c7a | 128 | *has_wrapped = o1; |
3fb1b6ad MD |
129 | return v2; |
130 | } | |
131 | ||
132 | ||
133 | static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start) | |
134 | { | |
46a12f74 | 135 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
3fb1b6ad MD |
136 | unsigned long flags, value; |
137 | ||
138 | /* start stop register shared by multiple timer channels */ | |
139 | spin_lock_irqsave(&sh_cmt_lock, flags); | |
140 | value = sh_cmt_read(p, CMSTR); | |
141 | ||
142 | if (start) | |
143 | value |= 1 << cfg->timer_bit; | |
144 | else | |
145 | value &= ~(1 << cfg->timer_bit); | |
146 | ||
147 | sh_cmt_write(p, CMSTR, value); | |
148 | spin_unlock_irqrestore(&sh_cmt_lock, flags); | |
149 | } | |
150 | ||
151 | static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) | |
152 | { | |
46a12f74 | 153 | struct sh_timer_config *cfg = p->pdev->dev.platform_data; |
3fb1b6ad MD |
154 | int ret; |
155 | ||
156 | /* enable clock */ | |
157 | ret = clk_enable(p->clk); | |
158 | if (ret) { | |
159 | pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk); | |
160 | return ret; | |
161 | } | |
3fb1b6ad MD |
162 | |
163 | /* make sure channel is disabled */ | |
164 | sh_cmt_start_stop_ch(p, 0); | |
165 | ||
166 | /* configure channel, periodic mode and maximum timeout */ | |
3014f474 MD |
167 | if (p->width == 16) { |
168 | *rate = clk_get_rate(p->clk) / 512; | |
169 | sh_cmt_write(p, CMCSR, 0x43); | |
170 | } else { | |
171 | *rate = clk_get_rate(p->clk) / 8; | |
3fb1b6ad | 172 | sh_cmt_write(p, CMCSR, 0x01a4); |
3014f474 | 173 | } |
3fb1b6ad MD |
174 | |
175 | sh_cmt_write(p, CMCOR, 0xffffffff); | |
176 | sh_cmt_write(p, CMCNT, 0); | |
177 | ||
178 | /* enable channel */ | |
179 | sh_cmt_start_stop_ch(p, 1); | |
180 | return 0; | |
181 | } | |
182 | ||
183 | static void sh_cmt_disable(struct sh_cmt_priv *p) | |
184 | { | |
185 | /* disable channel */ | |
186 | sh_cmt_start_stop_ch(p, 0); | |
187 | ||
be890a1a MD |
188 | /* disable interrupts in CMT block */ |
189 | sh_cmt_write(p, CMCSR, 0); | |
190 | ||
3fb1b6ad MD |
191 | /* stop clock */ |
192 | clk_disable(p->clk); | |
193 | } | |
194 | ||
195 | /* private flags */ | |
196 | #define FLAG_CLOCKEVENT (1 << 0) | |
197 | #define FLAG_CLOCKSOURCE (1 << 1) | |
198 | #define FLAG_REPROGRAM (1 << 2) | |
199 | #define FLAG_SKIPEVENT (1 << 3) | |
200 | #define FLAG_IRQCONTEXT (1 << 4) | |
201 | ||
202 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p, | |
203 | int absolute) | |
204 | { | |
205 | unsigned long new_match; | |
206 | unsigned long value = p->next_match_value; | |
207 | unsigned long delay = 0; | |
208 | unsigned long now = 0; | |
209 | int has_wrapped; | |
210 | ||
211 | now = sh_cmt_get_counter(p, &has_wrapped); | |
212 | p->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
213 | ||
214 | if (has_wrapped) { | |
215 | /* we're competing with the interrupt handler. | |
216 | * -> let the interrupt handler reprogram the timer. | |
217 | * -> interrupt number two handles the event. | |
218 | */ | |
219 | p->flags |= FLAG_SKIPEVENT; | |
220 | return; | |
221 | } | |
222 | ||
223 | if (absolute) | |
224 | now = 0; | |
225 | ||
226 | do { | |
227 | /* reprogram the timer hardware, | |
228 | * but don't save the new match value yet. | |
229 | */ | |
230 | new_match = now + value + delay; | |
231 | if (new_match > p->max_match_value) | |
232 | new_match = p->max_match_value; | |
233 | ||
234 | sh_cmt_write(p, CMCOR, new_match); | |
235 | ||
236 | now = sh_cmt_get_counter(p, &has_wrapped); | |
237 | if (has_wrapped && (new_match > p->match_value)) { | |
238 | /* we are changing to a greater match value, | |
239 | * so this wrap must be caused by the counter | |
240 | * matching the old value. | |
241 | * -> first interrupt reprograms the timer. | |
242 | * -> interrupt number two handles the event. | |
243 | */ | |
244 | p->flags |= FLAG_SKIPEVENT; | |
245 | break; | |
246 | } | |
247 | ||
248 | if (has_wrapped) { | |
249 | /* we are changing to a smaller match value, | |
250 | * so the wrap must be caused by the counter | |
251 | * matching the new value. | |
252 | * -> save programmed match value. | |
253 | * -> let isr handle the event. | |
254 | */ | |
255 | p->match_value = new_match; | |
256 | break; | |
257 | } | |
258 | ||
259 | /* be safe: verify hardware settings */ | |
260 | if (now < new_match) { | |
261 | /* timer value is below match value, all good. | |
262 | * this makes sure we won't miss any match events. | |
263 | * -> save programmed match value. | |
264 | * -> let isr handle the event. | |
265 | */ | |
266 | p->match_value = new_match; | |
267 | break; | |
268 | } | |
269 | ||
270 | /* the counter has reached a value greater | |
271 | * than our new match value. and since the | |
272 | * has_wrapped flag isn't set we must have | |
273 | * programmed a too close event. | |
274 | * -> increase delay and retry. | |
275 | */ | |
276 | if (delay) | |
277 | delay <<= 1; | |
278 | else | |
279 | delay = 1; | |
280 | ||
281 | if (!delay) | |
282 | pr_warning("sh_cmt: too long delay\n"); | |
283 | ||
284 | } while (delay); | |
285 | } | |
286 | ||
287 | static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta) | |
288 | { | |
289 | unsigned long flags; | |
290 | ||
291 | if (delta > p->max_match_value) | |
292 | pr_warning("sh_cmt: delta out of range\n"); | |
293 | ||
294 | spin_lock_irqsave(&p->lock, flags); | |
295 | p->next_match_value = delta; | |
296 | sh_cmt_clock_event_program_verify(p, 0); | |
297 | spin_unlock_irqrestore(&p->lock, flags); | |
298 | } | |
299 | ||
300 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
301 | { | |
302 | struct sh_cmt_priv *p = dev_id; | |
303 | ||
304 | /* clear flags */ | |
305 | sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits); | |
306 | ||
307 | /* update clock source counter to begin with if enabled | |
308 | * the wrap flag should be cleared by the timer specific | |
309 | * isr before we end up here. | |
310 | */ | |
311 | if (p->flags & FLAG_CLOCKSOURCE) | |
312 | p->total_cycles += p->match_value; | |
313 | ||
314 | if (!(p->flags & FLAG_REPROGRAM)) | |
315 | p->next_match_value = p->max_match_value; | |
316 | ||
317 | p->flags |= FLAG_IRQCONTEXT; | |
318 | ||
319 | if (p->flags & FLAG_CLOCKEVENT) { | |
320 | if (!(p->flags & FLAG_SKIPEVENT)) { | |
321 | if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
322 | p->next_match_value = p->max_match_value; | |
323 | p->flags |= FLAG_REPROGRAM; | |
324 | } | |
325 | ||
326 | p->ced.event_handler(&p->ced); | |
327 | } | |
328 | } | |
329 | ||
330 | p->flags &= ~FLAG_SKIPEVENT; | |
331 | ||
332 | if (p->flags & FLAG_REPROGRAM) { | |
333 | p->flags &= ~FLAG_REPROGRAM; | |
334 | sh_cmt_clock_event_program_verify(p, 1); | |
335 | ||
336 | if (p->flags & FLAG_CLOCKEVENT) | |
337 | if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
338 | || (p->match_value == p->next_match_value)) | |
339 | p->flags &= ~FLAG_REPROGRAM; | |
340 | } | |
341 | ||
342 | p->flags &= ~FLAG_IRQCONTEXT; | |
343 | ||
344 | return IRQ_HANDLED; | |
345 | } | |
346 | ||
347 | static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag) | |
348 | { | |
349 | int ret = 0; | |
350 | unsigned long flags; | |
351 | ||
352 | spin_lock_irqsave(&p->lock, flags); | |
353 | ||
354 | if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) | |
355 | ret = sh_cmt_enable(p, &p->rate); | |
356 | ||
357 | if (ret) | |
358 | goto out; | |
359 | p->flags |= flag; | |
360 | ||
361 | /* setup timeout if no clockevent */ | |
362 | if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT))) | |
363 | sh_cmt_set_next(p, p->max_match_value); | |
364 | out: | |
365 | spin_unlock_irqrestore(&p->lock, flags); | |
366 | ||
367 | return ret; | |
368 | } | |
369 | ||
370 | static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag) | |
371 | { | |
372 | unsigned long flags; | |
373 | unsigned long f; | |
374 | ||
375 | spin_lock_irqsave(&p->lock, flags); | |
376 | ||
377 | f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); | |
378 | p->flags &= ~flag; | |
379 | ||
380 | if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) | |
381 | sh_cmt_disable(p); | |
382 | ||
383 | /* adjust the timeout to maximum if only clocksource left */ | |
384 | if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE)) | |
385 | sh_cmt_set_next(p, p->max_match_value); | |
386 | ||
387 | spin_unlock_irqrestore(&p->lock, flags); | |
388 | } | |
389 | ||
19bdc9d0 MD |
390 | static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs) |
391 | { | |
392 | return container_of(cs, struct sh_cmt_priv, cs); | |
393 | } | |
394 | ||
395 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
396 | { | |
397 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); | |
398 | unsigned long flags, raw; | |
399 | unsigned long value; | |
400 | int has_wrapped; | |
401 | ||
402 | spin_lock_irqsave(&p->lock, flags); | |
403 | value = p->total_cycles; | |
404 | raw = sh_cmt_get_counter(p, &has_wrapped); | |
405 | ||
406 | if (unlikely(has_wrapped)) | |
5b644c7a | 407 | raw += p->match_value; |
19bdc9d0 MD |
408 | spin_unlock_irqrestore(&p->lock, flags); |
409 | ||
410 | return value + raw; | |
411 | } | |
412 | ||
413 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
414 | { | |
415 | struct sh_cmt_priv *p = cs_to_sh_cmt(cs); | |
416 | int ret; | |
417 | ||
418 | p->total_cycles = 0; | |
419 | ||
420 | ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); | |
421 | if (ret) | |
422 | return ret; | |
423 | ||
424 | /* TODO: calculate good shift from rate and counter bit width */ | |
425 | cs->shift = 0; | |
426 | cs->mult = clocksource_hz2mult(p->rate, cs->shift); | |
427 | return 0; | |
428 | } | |
429 | ||
430 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
431 | { | |
432 | sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE); | |
433 | } | |
434 | ||
435 | static int sh_cmt_register_clocksource(struct sh_cmt_priv *p, | |
436 | char *name, unsigned long rating) | |
437 | { | |
438 | struct clocksource *cs = &p->cs; | |
439 | ||
440 | cs->name = name; | |
441 | cs->rating = rating; | |
442 | cs->read = sh_cmt_clocksource_read; | |
443 | cs->enable = sh_cmt_clocksource_enable; | |
444 | cs->disable = sh_cmt_clocksource_disable; | |
445 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); | |
446 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
447 | pr_info("sh_cmt: %s used as clock source\n", cs->name); | |
448 | clocksource_register(cs); | |
449 | return 0; | |
450 | } | |
451 | ||
3fb1b6ad MD |
452 | static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced) |
453 | { | |
454 | return container_of(ced, struct sh_cmt_priv, ced); | |
455 | } | |
456 | ||
457 | static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic) | |
458 | { | |
459 | struct clock_event_device *ced = &p->ced; | |
460 | ||
461 | sh_cmt_start(p, FLAG_CLOCKEVENT); | |
462 | ||
463 | /* TODO: calculate good shift from rate and counter bit width */ | |
464 | ||
465 | ced->shift = 32; | |
466 | ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift); | |
467 | ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced); | |
468 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); | |
469 | ||
470 | if (periodic) | |
471 | sh_cmt_set_next(p, (p->rate + HZ/2) / HZ); | |
472 | else | |
473 | sh_cmt_set_next(p, p->max_match_value); | |
474 | } | |
475 | ||
476 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
477 | struct clock_event_device *ced) | |
478 | { | |
479 | struct sh_cmt_priv *p = ced_to_sh_cmt(ced); | |
480 | ||
481 | /* deal with old setting first */ | |
482 | switch (ced->mode) { | |
483 | case CLOCK_EVT_MODE_PERIODIC: | |
484 | case CLOCK_EVT_MODE_ONESHOT: | |
485 | sh_cmt_stop(p, FLAG_CLOCKEVENT); | |
486 | break; | |
487 | default: | |
488 | break; | |
489 | } | |
490 | ||
491 | switch (mode) { | |
492 | case CLOCK_EVT_MODE_PERIODIC: | |
493 | pr_info("sh_cmt: %s used for periodic clock events\n", | |
494 | ced->name); | |
495 | sh_cmt_clock_event_start(p, 1); | |
496 | break; | |
497 | case CLOCK_EVT_MODE_ONESHOT: | |
498 | pr_info("sh_cmt: %s used for oneshot clock events\n", | |
499 | ced->name); | |
500 | sh_cmt_clock_event_start(p, 0); | |
501 | break; | |
502 | case CLOCK_EVT_MODE_SHUTDOWN: | |
503 | case CLOCK_EVT_MODE_UNUSED: | |
504 | sh_cmt_stop(p, FLAG_CLOCKEVENT); | |
505 | break; | |
506 | default: | |
507 | break; | |
508 | } | |
509 | } | |
510 | ||
511 | static int sh_cmt_clock_event_next(unsigned long delta, | |
512 | struct clock_event_device *ced) | |
513 | { | |
514 | struct sh_cmt_priv *p = ced_to_sh_cmt(ced); | |
515 | ||
516 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
517 | if (likely(p->flags & FLAG_IRQCONTEXT)) | |
518 | p->next_match_value = delta; | |
519 | else | |
520 | sh_cmt_set_next(p, delta); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static void sh_cmt_register_clockevent(struct sh_cmt_priv *p, | |
526 | char *name, unsigned long rating) | |
527 | { | |
528 | struct clock_event_device *ced = &p->ced; | |
529 | ||
530 | memset(ced, 0, sizeof(*ced)); | |
531 | ||
532 | ced->name = name; | |
533 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
534 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
535 | ced->rating = rating; | |
536 | ced->cpumask = cpumask_of(0); | |
537 | ced->set_next_event = sh_cmt_clock_event_next; | |
538 | ced->set_mode = sh_cmt_clock_event_mode; | |
539 | ||
540 | pr_info("sh_cmt: %s used for clock events\n", ced->name); | |
3fb1b6ad MD |
541 | clockevents_register_device(ced); |
542 | } | |
543 | ||
d1fcc0a8 PM |
544 | static int sh_cmt_register(struct sh_cmt_priv *p, char *name, |
545 | unsigned long clockevent_rating, | |
546 | unsigned long clocksource_rating) | |
3fb1b6ad MD |
547 | { |
548 | if (p->width == (sizeof(p->max_match_value) * 8)) | |
549 | p->max_match_value = ~0; | |
550 | else | |
551 | p->max_match_value = (1 << p->width) - 1; | |
552 | ||
553 | p->match_value = p->max_match_value; | |
554 | spin_lock_init(&p->lock); | |
555 | ||
556 | if (clockevent_rating) | |
557 | sh_cmt_register_clockevent(p, name, clockevent_rating); | |
558 | ||
19bdc9d0 MD |
559 | if (clocksource_rating) |
560 | sh_cmt_register_clocksource(p, name, clocksource_rating); | |
561 | ||
3fb1b6ad MD |
562 | return 0; |
563 | } | |
564 | ||
565 | static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev) | |
566 | { | |
46a12f74 | 567 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
3fb1b6ad MD |
568 | struct resource *res; |
569 | int irq, ret; | |
570 | ret = -ENXIO; | |
571 | ||
572 | memset(p, 0, sizeof(*p)); | |
573 | p->pdev = pdev; | |
574 | ||
575 | if (!cfg) { | |
576 | dev_err(&p->pdev->dev, "missing platform data\n"); | |
577 | goto err0; | |
578 | } | |
579 | ||
580 | platform_set_drvdata(pdev, p); | |
581 | ||
582 | res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0); | |
583 | if (!res) { | |
584 | dev_err(&p->pdev->dev, "failed to get I/O memory\n"); | |
585 | goto err0; | |
586 | } | |
587 | ||
588 | irq = platform_get_irq(p->pdev, 0); | |
589 | if (irq < 0) { | |
590 | dev_err(&p->pdev->dev, "failed to get irq\n"); | |
591 | goto err0; | |
592 | } | |
593 | ||
594 | /* map memory, let mapbase point to our channel */ | |
595 | p->mapbase = ioremap_nocache(res->start, resource_size(res)); | |
596 | if (p->mapbase == NULL) { | |
597 | pr_err("sh_cmt: failed to remap I/O memory\n"); | |
598 | goto err0; | |
599 | } | |
600 | ||
601 | /* request irq using setup_irq() (too early for request_irq()) */ | |
602 | p->irqaction.name = cfg->name; | |
603 | p->irqaction.handler = sh_cmt_interrupt; | |
604 | p->irqaction.dev_id = p; | |
605 | p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL; | |
3fb1b6ad MD |
606 | ret = setup_irq(irq, &p->irqaction); |
607 | if (ret) { | |
608 | pr_err("sh_cmt: failed to request irq %d\n", irq); | |
609 | goto err1; | |
610 | } | |
611 | ||
612 | /* get hold of clock */ | |
613 | p->clk = clk_get(&p->pdev->dev, cfg->clk); | |
614 | if (IS_ERR(p->clk)) { | |
615 | pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk); | |
616 | ret = PTR_ERR(p->clk); | |
617 | goto err2; | |
618 | } | |
619 | ||
620 | if (resource_size(res) == 6) { | |
621 | p->width = 16; | |
622 | p->overflow_bit = 0x80; | |
3014f474 | 623 | p->clear_bits = ~0x80; |
3fb1b6ad MD |
624 | } else { |
625 | p->width = 32; | |
626 | p->overflow_bit = 0x8000; | |
627 | p->clear_bits = ~0xc000; | |
628 | } | |
629 | ||
630 | return sh_cmt_register(p, cfg->name, | |
631 | cfg->clockevent_rating, | |
632 | cfg->clocksource_rating); | |
633 | err2: | |
3093e78e | 634 | remove_irq(irq, &p->irqaction); |
3fb1b6ad MD |
635 | err1: |
636 | iounmap(p->mapbase); | |
637 | err0: | |
638 | return ret; | |
639 | } | |
640 | ||
641 | static int __devinit sh_cmt_probe(struct platform_device *pdev) | |
642 | { | |
643 | struct sh_cmt_priv *p = platform_get_drvdata(pdev); | |
46a12f74 | 644 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
3fb1b6ad MD |
645 | int ret; |
646 | ||
e475eedb MD |
647 | if (p) { |
648 | pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name); | |
649 | return 0; | |
650 | } | |
651 | ||
8e0b8429 | 652 | p = kmalloc(sizeof(*p), GFP_KERNEL); |
3fb1b6ad MD |
653 | if (p == NULL) { |
654 | dev_err(&pdev->dev, "failed to allocate driver data\n"); | |
655 | return -ENOMEM; | |
656 | } | |
657 | ||
658 | ret = sh_cmt_setup(p, pdev); | |
659 | if (ret) { | |
8e0b8429 | 660 | kfree(p); |
3fb1b6ad MD |
661 | platform_set_drvdata(pdev, NULL); |
662 | } | |
663 | return ret; | |
664 | } | |
665 | ||
666 | static int __devexit sh_cmt_remove(struct platform_device *pdev) | |
667 | { | |
668 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
669 | } | |
670 | ||
f6431732 MD |
671 | static int sh_cmt_suspend(struct device *dev) |
672 | { | |
673 | struct platform_device *pdev = to_platform_device(dev); | |
674 | struct sh_cmt_priv *p = platform_get_drvdata(pdev); | |
675 | ||
676 | /* save flag state and stop CMT channel */ | |
677 | p->flags_suspend = p->flags; | |
678 | sh_cmt_stop(p, p->flags); | |
679 | return 0; | |
680 | } | |
681 | ||
682 | static int sh_cmt_resume(struct device *dev) | |
683 | { | |
684 | struct platform_device *pdev = to_platform_device(dev); | |
685 | struct sh_cmt_priv *p = platform_get_drvdata(pdev); | |
686 | ||
687 | /* start CMT channel from saved state */ | |
688 | sh_cmt_start(p, p->flags_suspend); | |
689 | return 0; | |
690 | } | |
691 | ||
692 | static struct dev_pm_ops sh_cmt_dev_pm_ops = { | |
693 | .suspend = sh_cmt_suspend, | |
694 | .resume = sh_cmt_resume, | |
695 | }; | |
696 | ||
3fb1b6ad MD |
697 | static struct platform_driver sh_cmt_device_driver = { |
698 | .probe = sh_cmt_probe, | |
699 | .remove = __devexit_p(sh_cmt_remove), | |
700 | .driver = { | |
701 | .name = "sh_cmt", | |
f6431732 | 702 | .pm = &sh_cmt_dev_pm_ops, |
3fb1b6ad MD |
703 | } |
704 | }; | |
705 | ||
706 | static int __init sh_cmt_init(void) | |
707 | { | |
708 | return platform_driver_register(&sh_cmt_device_driver); | |
709 | } | |
710 | ||
711 | static void __exit sh_cmt_exit(void) | |
712 | { | |
713 | platform_driver_unregister(&sh_cmt_device_driver); | |
714 | } | |
715 | ||
e475eedb | 716 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
3fb1b6ad MD |
717 | module_init(sh_cmt_init); |
718 | module_exit(sh_cmt_exit); | |
719 | ||
720 | MODULE_AUTHOR("Magnus Damm"); | |
721 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
722 | MODULE_LICENSE("GPL v2"); |