Commit | Line | Data |
---|---|---|
3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
3fb1b6ad MD |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/err.h> | |
3f7e5e24 | 29 | #include <linux/delay.h> |
3fb1b6ad MD |
30 | #include <linux/clocksource.h> |
31 | #include <linux/clockchips.h> | |
46a12f74 | 32 | #include <linux/sh_timer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
7deeab5d | 34 | #include <linux/module.h> |
615a445f | 35 | #include <linux/pm_domain.h> |
bad81383 | 36 | #include <linux/pm_runtime.h> |
3fb1b6ad | 37 | |
2653caf4 | 38 | struct sh_cmt_device; |
7269f933 LP |
39 | |
40 | struct sh_cmt_channel { | |
2653caf4 | 41 | struct sh_cmt_device *cmt; |
3fb1b6ad MD |
42 | |
43 | unsigned long flags; | |
44 | unsigned long match_value; | |
45 | unsigned long next_match_value; | |
46 | unsigned long max_match_value; | |
47 | unsigned long rate; | |
7d0c399f | 48 | raw_spinlock_t lock; |
3fb1b6ad | 49 | struct clock_event_device ced; |
19bdc9d0 | 50 | struct clocksource cs; |
3fb1b6ad | 51 | unsigned long total_cycles; |
bad81383 | 52 | bool cs_enabled; |
7269f933 LP |
53 | }; |
54 | ||
2653caf4 | 55 | struct sh_cmt_device { |
7269f933 LP |
56 | struct platform_device *pdev; |
57 | ||
58 | void __iomem *mapbase; | |
59 | void __iomem *mapbase_str; | |
60 | struct clk *clk; | |
61 | ||
62 | struct sh_cmt_channel channel; | |
63 | ||
64 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
65 | unsigned long overflow_bit; | |
66 | unsigned long clear_bits; | |
a6a912ca | 67 | |
cccd7045 MD |
68 | /* callbacks for CMSTR and CMCSR access */ |
69 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
70 | void (*write_control)(void __iomem *base, unsigned long offs, | |
71 | unsigned long value); | |
72 | ||
a6a912ca MD |
73 | /* callbacks for CMCNT and CMCOR access */ |
74 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
75 | void (*write_count)(void __iomem *base, unsigned long offs, | |
76 | unsigned long value); | |
3fb1b6ad MD |
77 | }; |
78 | ||
118aee4d MD |
79 | /* Examples of supported CMT timer register layouts and I/O access widths: |
80 | * | |
81 | * "16-bit counter and 16-bit control" as found on sh7263: | |
82 | * CMSTR 0xfffec000 16-bit | |
83 | * CMCSR 0xfffec002 16-bit | |
84 | * CMCNT 0xfffec004 16-bit | |
85 | * CMCOR 0xfffec006 16-bit | |
86 | * | |
87 | * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740: | |
88 | * CMSTR 0xffca0000 16-bit | |
89 | * CMCSR 0xffca0060 16-bit | |
90 | * CMCNT 0xffca0064 32-bit | |
91 | * CMCOR 0xffca0068 32-bit | |
8874c5e3 MD |
92 | * |
93 | * "32-bit counter and 32-bit control" as found on r8a73a4 and r8a7790: | |
94 | * CMSTR 0xffca0500 32-bit | |
95 | * CMCSR 0xffca0510 32-bit | |
96 | * CMCNT 0xffca0514 32-bit | |
97 | * CMCOR 0xffca0518 32-bit | |
118aee4d MD |
98 | */ |
99 | ||
a6a912ca | 100 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
101 | { |
102 | return ioread16(base + (offs << 1)); | |
103 | } | |
104 | ||
a6a912ca MD |
105 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
106 | { | |
107 | return ioread32(base + (offs << 2)); | |
108 | } | |
109 | ||
110 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
111 | unsigned long value) | |
587acb3d MD |
112 | { |
113 | iowrite16(value, base + (offs << 1)); | |
114 | } | |
3fb1b6ad | 115 | |
a6a912ca MD |
116 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
117 | unsigned long value) | |
118 | { | |
119 | iowrite32(value, base + (offs << 2)); | |
120 | } | |
121 | ||
3fb1b6ad MD |
122 | #define CMCSR 0 /* channel register */ |
123 | #define CMCNT 1 /* channel register */ | |
124 | #define CMCOR 2 /* channel register */ | |
125 | ||
7269f933 | 126 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 127 | { |
7269f933 | 128 | return ch->cmt->read_control(ch->cmt->mapbase_str, 0); |
1b56b96b MD |
129 | } |
130 | ||
7269f933 | 131 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 132 | { |
7269f933 | 133 | return ch->cmt->read_control(ch->cmt->mapbase, CMCSR); |
1b56b96b MD |
134 | } |
135 | ||
7269f933 | 136 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 137 | { |
7269f933 | 138 | return ch->cmt->read_count(ch->cmt->mapbase, CMCNT); |
3fb1b6ad MD |
139 | } |
140 | ||
7269f933 | 141 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
1b56b96b MD |
142 | unsigned long value) |
143 | { | |
7269f933 | 144 | ch->cmt->write_control(ch->cmt->mapbase_str, 0, value); |
1b56b96b MD |
145 | } |
146 | ||
7269f933 | 147 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
148 | unsigned long value) |
149 | { | |
7269f933 | 150 | ch->cmt->write_control(ch->cmt->mapbase, CMCSR, value); |
1b56b96b MD |
151 | } |
152 | ||
7269f933 | 153 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
154 | unsigned long value) |
155 | { | |
7269f933 | 156 | ch->cmt->write_count(ch->cmt->mapbase, CMCNT, value); |
1b56b96b MD |
157 | } |
158 | ||
7269f933 | 159 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
160 | unsigned long value) |
161 | { | |
7269f933 | 162 | ch->cmt->write_count(ch->cmt->mapbase, CMCOR, value); |
1b56b96b MD |
163 | } |
164 | ||
7269f933 | 165 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
166 | int *has_wrapped) |
167 | { | |
168 | unsigned long v1, v2, v3; | |
5b644c7a MD |
169 | int o1, o2; |
170 | ||
7269f933 | 171 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->overflow_bit; |
3fb1b6ad MD |
172 | |
173 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
174 | do { | |
5b644c7a | 175 | o2 = o1; |
7269f933 LP |
176 | v1 = sh_cmt_read_cmcnt(ch); |
177 | v2 = sh_cmt_read_cmcnt(ch); | |
178 | v3 = sh_cmt_read_cmcnt(ch); | |
179 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->overflow_bit; | |
5b644c7a MD |
180 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
181 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 182 | |
5b644c7a | 183 | *has_wrapped = o1; |
3fb1b6ad MD |
184 | return v2; |
185 | } | |
186 | ||
587acb3d | 187 | static DEFINE_RAW_SPINLOCK(sh_cmt_lock); |
3fb1b6ad | 188 | |
7269f933 | 189 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 190 | { |
7269f933 | 191 | struct sh_timer_config *cfg = ch->cmt->pdev->dev.platform_data; |
3fb1b6ad MD |
192 | unsigned long flags, value; |
193 | ||
194 | /* start stop register shared by multiple timer channels */ | |
7d0c399f | 195 | raw_spin_lock_irqsave(&sh_cmt_lock, flags); |
7269f933 | 196 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
197 | |
198 | if (start) | |
199 | value |= 1 << cfg->timer_bit; | |
200 | else | |
201 | value &= ~(1 << cfg->timer_bit); | |
202 | ||
7269f933 | 203 | sh_cmt_write_cmstr(ch, value); |
7d0c399f | 204 | raw_spin_unlock_irqrestore(&sh_cmt_lock, flags); |
3fb1b6ad MD |
205 | } |
206 | ||
7269f933 | 207 | static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) |
3fb1b6ad | 208 | { |
3f7e5e24 | 209 | int k, ret; |
3fb1b6ad | 210 | |
7269f933 LP |
211 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
212 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 213 | |
9436b4ab | 214 | /* enable clock */ |
7269f933 | 215 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 216 | if (ret) { |
7269f933 | 217 | dev_err(&ch->cmt->pdev->dev, "cannot enable clock\n"); |
3f7e5e24 | 218 | goto err0; |
3fb1b6ad | 219 | } |
3fb1b6ad MD |
220 | |
221 | /* make sure channel is disabled */ | |
7269f933 | 222 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
223 | |
224 | /* configure channel, periodic mode and maximum timeout */ | |
7269f933 LP |
225 | if (ch->cmt->width == 16) { |
226 | *rate = clk_get_rate(ch->cmt->clk) / 512; | |
227 | sh_cmt_write_cmcsr(ch, 0x43); | |
3014f474 | 228 | } else { |
7269f933 LP |
229 | *rate = clk_get_rate(ch->cmt->clk) / 8; |
230 | sh_cmt_write_cmcsr(ch, 0x01a4); | |
3014f474 | 231 | } |
3fb1b6ad | 232 | |
7269f933 LP |
233 | sh_cmt_write_cmcor(ch, 0xffffffff); |
234 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 235 | |
3f7e5e24 MD |
236 | /* |
237 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
238 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
239 | * modifying CMCNT register; two RCLK cycles are necessary before | |
240 | * this register is either read or any modification of the value | |
241 | * it holds is reflected in the LSI's actual operation. | |
242 | * | |
243 | * While at it, we're supposed to clear out the CMCNT as of this | |
244 | * moment, so make sure it's processed properly here. This will | |
245 | * take RCLKx2 at maximum. | |
246 | */ | |
247 | for (k = 0; k < 100; k++) { | |
7269f933 | 248 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
249 | break; |
250 | udelay(1); | |
251 | } | |
252 | ||
7269f933 LP |
253 | if (sh_cmt_read_cmcnt(ch)) { |
254 | dev_err(&ch->cmt->pdev->dev, "cannot clear CMCNT\n"); | |
3f7e5e24 MD |
255 | ret = -ETIMEDOUT; |
256 | goto err1; | |
257 | } | |
258 | ||
3fb1b6ad | 259 | /* enable channel */ |
7269f933 | 260 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 261 | return 0; |
3f7e5e24 MD |
262 | err1: |
263 | /* stop clock */ | |
7269f933 | 264 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
265 | |
266 | err0: | |
267 | return ret; | |
3fb1b6ad MD |
268 | } |
269 | ||
7269f933 | 270 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
271 | { |
272 | /* disable channel */ | |
7269f933 | 273 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 274 | |
be890a1a | 275 | /* disable interrupts in CMT block */ |
7269f933 | 276 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 277 | |
9436b4ab | 278 | /* stop clock */ |
7269f933 | 279 | clk_disable(ch->cmt->clk); |
bad81383 | 280 | |
7269f933 LP |
281 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
282 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
283 | } |
284 | ||
285 | /* private flags */ | |
286 | #define FLAG_CLOCKEVENT (1 << 0) | |
287 | #define FLAG_CLOCKSOURCE (1 << 1) | |
288 | #define FLAG_REPROGRAM (1 << 2) | |
289 | #define FLAG_SKIPEVENT (1 << 3) | |
290 | #define FLAG_IRQCONTEXT (1 << 4) | |
291 | ||
7269f933 | 292 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
293 | int absolute) |
294 | { | |
295 | unsigned long new_match; | |
7269f933 | 296 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
297 | unsigned long delay = 0; |
298 | unsigned long now = 0; | |
299 | int has_wrapped; | |
300 | ||
7269f933 LP |
301 | now = sh_cmt_get_counter(ch, &has_wrapped); |
302 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
303 | |
304 | if (has_wrapped) { | |
305 | /* we're competing with the interrupt handler. | |
306 | * -> let the interrupt handler reprogram the timer. | |
307 | * -> interrupt number two handles the event. | |
308 | */ | |
7269f933 | 309 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
310 | return; |
311 | } | |
312 | ||
313 | if (absolute) | |
314 | now = 0; | |
315 | ||
316 | do { | |
317 | /* reprogram the timer hardware, | |
318 | * but don't save the new match value yet. | |
319 | */ | |
320 | new_match = now + value + delay; | |
7269f933 LP |
321 | if (new_match > ch->max_match_value) |
322 | new_match = ch->max_match_value; | |
3fb1b6ad | 323 | |
7269f933 | 324 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 325 | |
7269f933 LP |
326 | now = sh_cmt_get_counter(ch, &has_wrapped); |
327 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
328 | /* we are changing to a greater match value, |
329 | * so this wrap must be caused by the counter | |
330 | * matching the old value. | |
331 | * -> first interrupt reprograms the timer. | |
332 | * -> interrupt number two handles the event. | |
333 | */ | |
7269f933 | 334 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
335 | break; |
336 | } | |
337 | ||
338 | if (has_wrapped) { | |
339 | /* we are changing to a smaller match value, | |
340 | * so the wrap must be caused by the counter | |
341 | * matching the new value. | |
342 | * -> save programmed match value. | |
343 | * -> let isr handle the event. | |
344 | */ | |
7269f933 | 345 | ch->match_value = new_match; |
3fb1b6ad MD |
346 | break; |
347 | } | |
348 | ||
349 | /* be safe: verify hardware settings */ | |
350 | if (now < new_match) { | |
351 | /* timer value is below match value, all good. | |
352 | * this makes sure we won't miss any match events. | |
353 | * -> save programmed match value. | |
354 | * -> let isr handle the event. | |
355 | */ | |
7269f933 | 356 | ch->match_value = new_match; |
3fb1b6ad MD |
357 | break; |
358 | } | |
359 | ||
360 | /* the counter has reached a value greater | |
361 | * than our new match value. and since the | |
362 | * has_wrapped flag isn't set we must have | |
363 | * programmed a too close event. | |
364 | * -> increase delay and retry. | |
365 | */ | |
366 | if (delay) | |
367 | delay <<= 1; | |
368 | else | |
369 | delay = 1; | |
370 | ||
371 | if (!delay) | |
7269f933 | 372 | dev_warn(&ch->cmt->pdev->dev, "too long delay\n"); |
3fb1b6ad MD |
373 | |
374 | } while (delay); | |
375 | } | |
376 | ||
7269f933 | 377 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 378 | { |
7269f933 LP |
379 | if (delta > ch->max_match_value) |
380 | dev_warn(&ch->cmt->pdev->dev, "delta out of range\n"); | |
3fb1b6ad | 381 | |
7269f933 LP |
382 | ch->next_match_value = delta; |
383 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
384 | } |
385 | ||
7269f933 | 386 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
387 | { |
388 | unsigned long flags; | |
389 | ||
7269f933 LP |
390 | raw_spin_lock_irqsave(&ch->lock, flags); |
391 | __sh_cmt_set_next(ch, delta); | |
392 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
393 | } |
394 | ||
395 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
396 | { | |
7269f933 | 397 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
398 | |
399 | /* clear flags */ | |
7269f933 | 400 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & ch->cmt->clear_bits); |
3fb1b6ad MD |
401 | |
402 | /* update clock source counter to begin with if enabled | |
403 | * the wrap flag should be cleared by the timer specific | |
404 | * isr before we end up here. | |
405 | */ | |
7269f933 LP |
406 | if (ch->flags & FLAG_CLOCKSOURCE) |
407 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 408 | |
7269f933 LP |
409 | if (!(ch->flags & FLAG_REPROGRAM)) |
410 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 411 | |
7269f933 | 412 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 413 | |
7269f933 LP |
414 | if (ch->flags & FLAG_CLOCKEVENT) { |
415 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
416 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
417 | ch->next_match_value = ch->max_match_value; | |
418 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
419 | } |
420 | ||
7269f933 | 421 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
422 | } |
423 | } | |
424 | ||
7269f933 | 425 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 426 | |
7269f933 LP |
427 | if (ch->flags & FLAG_REPROGRAM) { |
428 | ch->flags &= ~FLAG_REPROGRAM; | |
429 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 430 | |
7269f933 LP |
431 | if (ch->flags & FLAG_CLOCKEVENT) |
432 | if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
433 | || (ch->match_value == ch->next_match_value)) | |
434 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
435 | } |
436 | ||
7269f933 | 437 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
438 | |
439 | return IRQ_HANDLED; | |
440 | } | |
441 | ||
7269f933 | 442 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
443 | { |
444 | int ret = 0; | |
445 | unsigned long flags; | |
446 | ||
7269f933 | 447 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 448 | |
7269f933 LP |
449 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
450 | ret = sh_cmt_enable(ch, &ch->rate); | |
3fb1b6ad MD |
451 | |
452 | if (ret) | |
453 | goto out; | |
7269f933 | 454 | ch->flags |= flag; |
3fb1b6ad MD |
455 | |
456 | /* setup timeout if no clockevent */ | |
7269f933 LP |
457 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
458 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 459 | out: |
7269f933 | 460 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
461 | |
462 | return ret; | |
463 | } | |
464 | ||
7269f933 | 465 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
466 | { |
467 | unsigned long flags; | |
468 | unsigned long f; | |
469 | ||
7269f933 | 470 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 471 | |
7269f933 LP |
472 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
473 | ch->flags &= ~flag; | |
3fb1b6ad | 474 | |
7269f933 LP |
475 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
476 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
477 | |
478 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
479 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
480 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 481 | |
7269f933 | 482 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
483 | } |
484 | ||
7269f933 | 485 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 486 | { |
7269f933 | 487 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
488 | } |
489 | ||
490 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
491 | { | |
7269f933 | 492 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
493 | unsigned long flags, raw; |
494 | unsigned long value; | |
495 | int has_wrapped; | |
496 | ||
7269f933 LP |
497 | raw_spin_lock_irqsave(&ch->lock, flags); |
498 | value = ch->total_cycles; | |
499 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
500 | |
501 | if (unlikely(has_wrapped)) | |
7269f933 LP |
502 | raw += ch->match_value + 1; |
503 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
504 | |
505 | return value + raw; | |
506 | } | |
507 | ||
508 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
509 | { | |
3593f5fe | 510 | int ret; |
7269f933 | 511 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 512 | |
7269f933 | 513 | WARN_ON(ch->cs_enabled); |
bad81383 | 514 | |
7269f933 | 515 | ch->total_cycles = 0; |
19bdc9d0 | 516 | |
7269f933 | 517 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
bad81383 | 518 | if (!ret) { |
7269f933 LP |
519 | __clocksource_updatefreq_hz(cs, ch->rate); |
520 | ch->cs_enabled = true; | |
bad81383 | 521 | } |
3593f5fe | 522 | return ret; |
19bdc9d0 MD |
523 | } |
524 | ||
525 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
526 | { | |
7269f933 | 527 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 528 | |
7269f933 | 529 | WARN_ON(!ch->cs_enabled); |
bad81383 | 530 | |
7269f933 LP |
531 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
532 | ch->cs_enabled = false; | |
19bdc9d0 MD |
533 | } |
534 | ||
9bb5ec88 RW |
535 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
536 | { | |
7269f933 | 537 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 538 | |
7269f933 LP |
539 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
540 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
541 | } |
542 | ||
c8162884 MD |
543 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
544 | { | |
7269f933 | 545 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 546 | |
7269f933 LP |
547 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
548 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
549 | } |
550 | ||
7269f933 | 551 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
19bdc9d0 MD |
552 | char *name, unsigned long rating) |
553 | { | |
7269f933 | 554 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
555 | |
556 | cs->name = name; | |
557 | cs->rating = rating; | |
558 | cs->read = sh_cmt_clocksource_read; | |
559 | cs->enable = sh_cmt_clocksource_enable; | |
560 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 561 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 562 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
563 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
564 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 565 | |
7269f933 | 566 | dev_info(&ch->cmt->pdev->dev, "used as clock source\n"); |
f4d7c356 | 567 | |
3593f5fe MD |
568 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ |
569 | clocksource_register_hz(cs, 1); | |
19bdc9d0 MD |
570 | return 0; |
571 | } | |
572 | ||
7269f933 | 573 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 574 | { |
7269f933 | 575 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
576 | } |
577 | ||
7269f933 | 578 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 579 | { |
7269f933 | 580 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad | 581 | |
7269f933 | 582 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
583 | |
584 | /* TODO: calculate good shift from rate and counter bit width */ | |
585 | ||
586 | ced->shift = 32; | |
7269f933 LP |
587 | ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift); |
588 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
3fb1b6ad MD |
589 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
590 | ||
591 | if (periodic) | |
7269f933 | 592 | sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 593 | else |
7269f933 | 594 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
595 | } |
596 | ||
597 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
598 | struct clock_event_device *ced) | |
599 | { | |
7269f933 | 600 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
601 | |
602 | /* deal with old setting first */ | |
603 | switch (ced->mode) { | |
604 | case CLOCK_EVT_MODE_PERIODIC: | |
605 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 606 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
607 | break; |
608 | default: | |
609 | break; | |
610 | } | |
611 | ||
612 | switch (mode) { | |
613 | case CLOCK_EVT_MODE_PERIODIC: | |
7269f933 LP |
614 | dev_info(&ch->cmt->pdev->dev, |
615 | "used for periodic clock events\n"); | |
616 | sh_cmt_clock_event_start(ch, 1); | |
3fb1b6ad MD |
617 | break; |
618 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 LP |
619 | dev_info(&ch->cmt->pdev->dev, |
620 | "used for oneshot clock events\n"); | |
621 | sh_cmt_clock_event_start(ch, 0); | |
3fb1b6ad MD |
622 | break; |
623 | case CLOCK_EVT_MODE_SHUTDOWN: | |
624 | case CLOCK_EVT_MODE_UNUSED: | |
7269f933 | 625 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
626 | break; |
627 | default: | |
628 | break; | |
629 | } | |
630 | } | |
631 | ||
632 | static int sh_cmt_clock_event_next(unsigned long delta, | |
633 | struct clock_event_device *ced) | |
634 | { | |
7269f933 | 635 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
636 | |
637 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
7269f933 LP |
638 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
639 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 640 | else |
7269f933 | 641 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
642 | |
643 | return 0; | |
644 | } | |
645 | ||
9bb5ec88 RW |
646 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
647 | { | |
7269f933 | 648 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 649 | |
7269f933 LP |
650 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
651 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
652 | } |
653 | ||
654 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
655 | { | |
7269f933 | 656 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 657 | |
7269f933 LP |
658 | clk_prepare(ch->cmt->clk); |
659 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
660 | } |
661 | ||
7269f933 | 662 | static void sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
663 | char *name, unsigned long rating) |
664 | { | |
7269f933 | 665 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad MD |
666 | |
667 | memset(ced, 0, sizeof(*ced)); | |
668 | ||
669 | ced->name = name; | |
670 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
671 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
672 | ced->rating = rating; | |
673 | ced->cpumask = cpumask_of(0); | |
674 | ced->set_next_event = sh_cmt_clock_event_next; | |
675 | ced->set_mode = sh_cmt_clock_event_mode; | |
9bb5ec88 RW |
676 | ced->suspend = sh_cmt_clock_event_suspend; |
677 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 678 | |
7269f933 | 679 | dev_info(&ch->cmt->pdev->dev, "used for clock events\n"); |
3fb1b6ad MD |
680 | clockevents_register_device(ced); |
681 | } | |
682 | ||
7269f933 | 683 | static int sh_cmt_register(struct sh_cmt_channel *ch, char *name, |
d1fcc0a8 PM |
684 | unsigned long clockevent_rating, |
685 | unsigned long clocksource_rating) | |
3fb1b6ad | 686 | { |
3fb1b6ad | 687 | if (clockevent_rating) |
7269f933 | 688 | sh_cmt_register_clockevent(ch, name, clockevent_rating); |
3fb1b6ad | 689 | |
19bdc9d0 | 690 | if (clocksource_rating) |
7269f933 | 691 | sh_cmt_register_clocksource(ch, name, clocksource_rating); |
19bdc9d0 | 692 | |
3fb1b6ad MD |
693 | return 0; |
694 | } | |
695 | ||
2653caf4 | 696 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
3fb1b6ad | 697 | { |
46a12f74 | 698 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
2653caf4 | 699 | struct sh_cmt_channel *ch = &cmt->channel; |
8874c5e3 | 700 | struct resource *res, *res2; |
3fb1b6ad MD |
701 | int irq, ret; |
702 | ret = -ENXIO; | |
703 | ||
2653caf4 LP |
704 | memset(cmt, 0, sizeof(*cmt)); |
705 | cmt->pdev = pdev; | |
3fb1b6ad MD |
706 | |
707 | if (!cfg) { | |
2653caf4 | 708 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
3fb1b6ad MD |
709 | goto err0; |
710 | } | |
711 | ||
2653caf4 | 712 | res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
3fb1b6ad | 713 | if (!res) { |
2653caf4 | 714 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); |
3fb1b6ad MD |
715 | goto err0; |
716 | } | |
717 | ||
8874c5e3 | 718 | /* optional resource for the shared timer start/stop register */ |
2653caf4 | 719 | res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1); |
8874c5e3 | 720 | |
2653caf4 | 721 | irq = platform_get_irq(cmt->pdev, 0); |
3fb1b6ad | 722 | if (irq < 0) { |
2653caf4 | 723 | dev_err(&cmt->pdev->dev, "failed to get irq\n"); |
3fb1b6ad MD |
724 | goto err0; |
725 | } | |
726 | ||
727 | /* map memory, let mapbase point to our channel */ | |
2653caf4 LP |
728 | cmt->mapbase = ioremap_nocache(res->start, resource_size(res)); |
729 | if (cmt->mapbase == NULL) { | |
730 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
3fb1b6ad MD |
731 | goto err0; |
732 | } | |
733 | ||
8874c5e3 | 734 | /* map second resource for CMSTR */ |
2653caf4 LP |
735 | cmt->mapbase_str = ioremap_nocache(res2 ? res2->start : |
736 | res->start - cfg->channel_offset, | |
737 | res2 ? resource_size(res2) : 2); | |
738 | if (cmt->mapbase_str == NULL) { | |
739 | dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n"); | |
8874c5e3 MD |
740 | goto err1; |
741 | } | |
742 | ||
3fb1b6ad | 743 | /* get hold of clock */ |
2653caf4 LP |
744 | cmt->clk = clk_get(&cmt->pdev->dev, "cmt_fck"); |
745 | if (IS_ERR(cmt->clk)) { | |
746 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
747 | ret = PTR_ERR(cmt->clk); | |
8874c5e3 | 748 | goto err2; |
3fb1b6ad MD |
749 | } |
750 | ||
2653caf4 | 751 | ret = clk_prepare(cmt->clk); |
57dee992 LP |
752 | if (ret < 0) |
753 | goto err3; | |
754 | ||
8874c5e3 MD |
755 | if (res2 && (resource_size(res2) == 4)) { |
756 | /* assume both CMSTR and CMCSR to be 32-bit */ | |
2653caf4 LP |
757 | cmt->read_control = sh_cmt_read32; |
758 | cmt->write_control = sh_cmt_write32; | |
8874c5e3 | 759 | } else { |
2653caf4 LP |
760 | cmt->read_control = sh_cmt_read16; |
761 | cmt->write_control = sh_cmt_write16; | |
8874c5e3 | 762 | } |
cccd7045 | 763 | |
3fb1b6ad | 764 | if (resource_size(res) == 6) { |
2653caf4 LP |
765 | cmt->width = 16; |
766 | cmt->read_count = sh_cmt_read16; | |
767 | cmt->write_count = sh_cmt_write16; | |
768 | cmt->overflow_bit = 0x80; | |
769 | cmt->clear_bits = ~0x80; | |
3fb1b6ad | 770 | } else { |
2653caf4 LP |
771 | cmt->width = 32; |
772 | cmt->read_count = sh_cmt_read32; | |
773 | cmt->write_count = sh_cmt_write32; | |
774 | cmt->overflow_bit = 0x8000; | |
775 | cmt->clear_bits = ~0xc000; | |
3fb1b6ad MD |
776 | } |
777 | ||
2653caf4 | 778 | if (cmt->width == (sizeof(ch->max_match_value) * 8)) |
7269f933 | 779 | ch->max_match_value = ~0; |
44a10f94 | 780 | else |
2653caf4 | 781 | ch->max_match_value = (1 << cmt->width) - 1; |
44a10f94 | 782 | |
2653caf4 | 783 | ch->cmt = cmt; |
7269f933 LP |
784 | ch->match_value = ch->max_match_value; |
785 | raw_spin_lock_init(&ch->lock); | |
44a10f94 | 786 | |
2653caf4 | 787 | ret = sh_cmt_register(ch, (char *)dev_name(&cmt->pdev->dev), |
da64c2a8 PM |
788 | cfg->clockevent_rating, |
789 | cfg->clocksource_rating); | |
790 | if (ret) { | |
2653caf4 | 791 | dev_err(&cmt->pdev->dev, "registration failed\n"); |
57dee992 | 792 | goto err4; |
da64c2a8 | 793 | } |
7269f933 | 794 | ch->cs_enabled = false; |
da64c2a8 | 795 | |
dc2eadec LP |
796 | ret = request_irq(irq, sh_cmt_interrupt, |
797 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
2653caf4 | 798 | dev_name(&cmt->pdev->dev), ch); |
da64c2a8 | 799 | if (ret) { |
2653caf4 | 800 | dev_err(&cmt->pdev->dev, "failed to request irq %d\n", irq); |
57dee992 | 801 | goto err4; |
da64c2a8 PM |
802 | } |
803 | ||
2653caf4 | 804 | platform_set_drvdata(pdev, cmt); |
adccc69e | 805 | |
da64c2a8 | 806 | return 0; |
57dee992 | 807 | err4: |
2653caf4 | 808 | clk_unprepare(cmt->clk); |
8874c5e3 | 809 | err3: |
2653caf4 | 810 | clk_put(cmt->clk); |
8874c5e3 | 811 | err2: |
2653caf4 | 812 | iounmap(cmt->mapbase_str); |
da64c2a8 | 813 | err1: |
2653caf4 | 814 | iounmap(cmt->mapbase); |
da64c2a8 | 815 | err0: |
3fb1b6ad MD |
816 | return ret; |
817 | } | |
818 | ||
1850514b | 819 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 820 | { |
2653caf4 | 821 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
bad81383 | 822 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
3fb1b6ad MD |
823 | int ret; |
824 | ||
9bb5ec88 | 825 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
826 | pm_runtime_set_active(&pdev->dev); |
827 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 828 | } |
615a445f | 829 | |
2653caf4 | 830 | if (cmt) { |
214a607a | 831 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 832 | goto out; |
e475eedb MD |
833 | } |
834 | ||
2653caf4 LP |
835 | cmt = kmalloc(sizeof(*cmt), GFP_KERNEL); |
836 | if (cmt == NULL) { | |
3fb1b6ad MD |
837 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
838 | return -ENOMEM; | |
839 | } | |
840 | ||
2653caf4 | 841 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 842 | if (ret) { |
2653caf4 | 843 | kfree(cmt); |
bad81383 RW |
844 | pm_runtime_idle(&pdev->dev); |
845 | return ret; | |
3fb1b6ad | 846 | } |
bad81383 RW |
847 | if (is_early_platform_device(pdev)) |
848 | return 0; | |
849 | ||
850 | out: | |
851 | if (cfg->clockevent_rating || cfg->clocksource_rating) | |
852 | pm_runtime_irq_safe(&pdev->dev); | |
853 | else | |
854 | pm_runtime_idle(&pdev->dev); | |
855 | ||
856 | return 0; | |
3fb1b6ad MD |
857 | } |
858 | ||
1850514b | 859 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
860 | { |
861 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
862 | } | |
863 | ||
864 | static struct platform_driver sh_cmt_device_driver = { | |
865 | .probe = sh_cmt_probe, | |
1850514b | 866 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
867 | .driver = { |
868 | .name = "sh_cmt", | |
869 | } | |
870 | }; | |
871 | ||
872 | static int __init sh_cmt_init(void) | |
873 | { | |
874 | return platform_driver_register(&sh_cmt_device_driver); | |
875 | } | |
876 | ||
877 | static void __exit sh_cmt_exit(void) | |
878 | { | |
879 | platform_driver_unregister(&sh_cmt_device_driver); | |
880 | } | |
881 | ||
e475eedb | 882 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 883 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
884 | module_exit(sh_cmt_exit); |
885 | ||
886 | MODULE_AUTHOR("Magnus Damm"); | |
887 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
888 | MODULE_LICENSE("GPL v2"); |