Commit | Line | Data |
---|---|---|
3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
3fb1b6ad MD |
14 | */ |
15 | ||
e7a9bcc2 LP |
16 | #include <linux/clk.h> |
17 | #include <linux/clockchips.h> | |
18 | #include <linux/clocksource.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/err.h> | |
3fb1b6ad | 21 | #include <linux/init.h> |
3fb1b6ad | 22 | #include <linux/interrupt.h> |
3fb1b6ad | 23 | #include <linux/io.h> |
e7a9bcc2 | 24 | #include <linux/ioport.h> |
3fb1b6ad | 25 | #include <linux/irq.h> |
7deeab5d | 26 | #include <linux/module.h> |
e7a9bcc2 | 27 | #include <linux/platform_device.h> |
615a445f | 28 | #include <linux/pm_domain.h> |
bad81383 | 29 | #include <linux/pm_runtime.h> |
e7a9bcc2 LP |
30 | #include <linux/sh_timer.h> |
31 | #include <linux/slab.h> | |
32 | #include <linux/spinlock.h> | |
3fb1b6ad | 33 | |
2653caf4 | 34 | struct sh_cmt_device; |
7269f933 | 35 | |
2cda3ac4 LP |
36 | /* |
37 | * The CMT comes in 5 different identified flavours, depending not only on the | |
38 | * SoC but also on the particular instance. The following table lists the main | |
39 | * characteristics of those flavours. | |
40 | * | |
41 | * 16B 32B 32B-F 48B 48B-2 | |
42 | * ----------------------------------------------------------------------------- | |
43 | * Channels 2 1/4 1 6 2/8 | |
44 | * Control Width 16 16 16 16 32 | |
45 | * Counter Width 16 32 32 32/48 32/48 | |
46 | * Shared Start/Stop Y Y Y Y N | |
47 | * | |
48 | * The 48-bit gen2 version has a per-channel start/stop register located in the | |
49 | * channel registers block. All other versions have a shared start/stop register | |
50 | * located in the global space. | |
51 | * | |
81b3b271 LP |
52 | * Channels are indexed from 0 to N-1 in the documentation. The channel index |
53 | * infers the start/stop bit position in the control register and the channel | |
54 | * registers block address. Some CMT instances have a subset of channels | |
55 | * available, in which case the index in the documentation doesn't match the | |
56 | * "real" index as implemented in hardware. This is for instance the case with | |
57 | * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0 | |
58 | * in the documentation but using start/stop bit 5 and having its registers | |
59 | * block at 0x60. | |
60 | * | |
61 | * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit | |
2cda3ac4 LP |
62 | * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable. |
63 | */ | |
64 | ||
65 | enum sh_cmt_model { | |
66 | SH_CMT_16BIT, | |
67 | SH_CMT_32BIT, | |
68 | SH_CMT_32BIT_FAST, | |
69 | SH_CMT_48BIT, | |
70 | SH_CMT_48BIT_GEN2, | |
71 | }; | |
72 | ||
73 | struct sh_cmt_info { | |
74 | enum sh_cmt_model model; | |
75 | ||
76 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
77 | unsigned long overflow_bit; | |
78 | unsigned long clear_bits; | |
79 | ||
80 | /* callbacks for CMSTR and CMCSR access */ | |
81 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
82 | void (*write_control)(void __iomem *base, unsigned long offs, | |
83 | unsigned long value); | |
84 | ||
85 | /* callbacks for CMCNT and CMCOR access */ | |
86 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
87 | void (*write_count)(void __iomem *base, unsigned long offs, | |
88 | unsigned long value); | |
89 | }; | |
90 | ||
7269f933 | 91 | struct sh_cmt_channel { |
2653caf4 | 92 | struct sh_cmt_device *cmt; |
3fb1b6ad | 93 | |
81b3b271 LP |
94 | unsigned int index; /* Index in the documentation */ |
95 | unsigned int hwidx; /* Real hardware index */ | |
96 | ||
97 | void __iomem *iostart; | |
98 | void __iomem *ioctrl; | |
c924d2d2 | 99 | |
81b3b271 | 100 | unsigned int timer_bit; |
3fb1b6ad MD |
101 | unsigned long flags; |
102 | unsigned long match_value; | |
103 | unsigned long next_match_value; | |
104 | unsigned long max_match_value; | |
105 | unsigned long rate; | |
7d0c399f | 106 | raw_spinlock_t lock; |
3fb1b6ad | 107 | struct clock_event_device ced; |
19bdc9d0 | 108 | struct clocksource cs; |
3fb1b6ad | 109 | unsigned long total_cycles; |
bad81383 | 110 | bool cs_enabled; |
7269f933 LP |
111 | }; |
112 | ||
2653caf4 | 113 | struct sh_cmt_device { |
7269f933 LP |
114 | struct platform_device *pdev; |
115 | ||
2cda3ac4 LP |
116 | const struct sh_cmt_info *info; |
117 | ||
7269f933 | 118 | void __iomem *mapbase; |
7269f933 LP |
119 | struct clk *clk; |
120 | ||
de599c88 LP |
121 | raw_spinlock_t lock; /* Protect the shared start/stop register */ |
122 | ||
f5ec9b19 LP |
123 | struct sh_cmt_channel *channels; |
124 | unsigned int num_channels; | |
81b3b271 LP |
125 | |
126 | bool has_clockevent; | |
127 | bool has_clocksource; | |
3fb1b6ad MD |
128 | }; |
129 | ||
d14be99b LP |
130 | #define SH_CMT16_CMCSR_CMF (1 << 7) |
131 | #define SH_CMT16_CMCSR_CMIE (1 << 6) | |
132 | #define SH_CMT16_CMCSR_CKS8 (0 << 0) | |
133 | #define SH_CMT16_CMCSR_CKS32 (1 << 0) | |
134 | #define SH_CMT16_CMCSR_CKS128 (2 << 0) | |
135 | #define SH_CMT16_CMCSR_CKS512 (3 << 0) | |
136 | #define SH_CMT16_CMCSR_CKS_MASK (3 << 0) | |
137 | ||
138 | #define SH_CMT32_CMCSR_CMF (1 << 15) | |
139 | #define SH_CMT32_CMCSR_OVF (1 << 14) | |
140 | #define SH_CMT32_CMCSR_WRFLG (1 << 13) | |
141 | #define SH_CMT32_CMCSR_STTF (1 << 12) | |
142 | #define SH_CMT32_CMCSR_STPF (1 << 11) | |
143 | #define SH_CMT32_CMCSR_SSIE (1 << 10) | |
144 | #define SH_CMT32_CMCSR_CMS (1 << 9) | |
145 | #define SH_CMT32_CMCSR_CMM (1 << 8) | |
146 | #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7) | |
147 | #define SH_CMT32_CMCSR_CMR_NONE (0 << 4) | |
148 | #define SH_CMT32_CMCSR_CMR_DMA (1 << 4) | |
149 | #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4) | |
150 | #define SH_CMT32_CMCSR_CMR_MASK (3 << 4) | |
151 | #define SH_CMT32_CMCSR_DBGIVD (1 << 3) | |
152 | #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0) | |
153 | #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0) | |
154 | #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0) | |
155 | #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0) | |
156 | #define SH_CMT32_CMCSR_CKS_MASK (7 << 0) | |
157 | ||
a6a912ca | 158 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
159 | { |
160 | return ioread16(base + (offs << 1)); | |
161 | } | |
162 | ||
a6a912ca MD |
163 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
164 | { | |
165 | return ioread32(base + (offs << 2)); | |
166 | } | |
167 | ||
168 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
169 | unsigned long value) | |
587acb3d MD |
170 | { |
171 | iowrite16(value, base + (offs << 1)); | |
172 | } | |
3fb1b6ad | 173 | |
a6a912ca MD |
174 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
175 | unsigned long value) | |
176 | { | |
177 | iowrite32(value, base + (offs << 2)); | |
178 | } | |
179 | ||
2cda3ac4 LP |
180 | static const struct sh_cmt_info sh_cmt_info[] = { |
181 | [SH_CMT_16BIT] = { | |
182 | .model = SH_CMT_16BIT, | |
183 | .width = 16, | |
d14be99b LP |
184 | .overflow_bit = SH_CMT16_CMCSR_CMF, |
185 | .clear_bits = ~SH_CMT16_CMCSR_CMF, | |
2cda3ac4 LP |
186 | .read_control = sh_cmt_read16, |
187 | .write_control = sh_cmt_write16, | |
188 | .read_count = sh_cmt_read16, | |
189 | .write_count = sh_cmt_write16, | |
190 | }, | |
191 | [SH_CMT_32BIT] = { | |
192 | .model = SH_CMT_32BIT, | |
193 | .width = 32, | |
d14be99b LP |
194 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
195 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
196 | .read_control = sh_cmt_read16, |
197 | .write_control = sh_cmt_write16, | |
198 | .read_count = sh_cmt_read32, | |
199 | .write_count = sh_cmt_write32, | |
200 | }, | |
201 | [SH_CMT_32BIT_FAST] = { | |
202 | .model = SH_CMT_32BIT_FAST, | |
203 | .width = 32, | |
d14be99b LP |
204 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
205 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
206 | .read_control = sh_cmt_read16, |
207 | .write_control = sh_cmt_write16, | |
208 | .read_count = sh_cmt_read32, | |
209 | .write_count = sh_cmt_write32, | |
210 | }, | |
211 | [SH_CMT_48BIT] = { | |
212 | .model = SH_CMT_48BIT, | |
213 | .width = 32, | |
d14be99b LP |
214 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
215 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
216 | .read_control = sh_cmt_read32, |
217 | .write_control = sh_cmt_write32, | |
218 | .read_count = sh_cmt_read32, | |
219 | .write_count = sh_cmt_write32, | |
220 | }, | |
221 | [SH_CMT_48BIT_GEN2] = { | |
222 | .model = SH_CMT_48BIT_GEN2, | |
223 | .width = 32, | |
d14be99b LP |
224 | .overflow_bit = SH_CMT32_CMCSR_CMF, |
225 | .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF), | |
2cda3ac4 LP |
226 | .read_control = sh_cmt_read32, |
227 | .write_control = sh_cmt_write32, | |
228 | .read_count = sh_cmt_read32, | |
229 | .write_count = sh_cmt_write32, | |
230 | }, | |
231 | }; | |
232 | ||
3fb1b6ad MD |
233 | #define CMCSR 0 /* channel register */ |
234 | #define CMCNT 1 /* channel register */ | |
235 | #define CMCOR 2 /* channel register */ | |
236 | ||
7269f933 | 237 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 238 | { |
81b3b271 LP |
239 | if (ch->iostart) |
240 | return ch->cmt->info->read_control(ch->iostart, 0); | |
241 | else | |
242 | return ch->cmt->info->read_control(ch->cmt->mapbase, 0); | |
1b56b96b MD |
243 | } |
244 | ||
81b3b271 LP |
245 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
246 | unsigned long value) | |
1b56b96b | 247 | { |
81b3b271 LP |
248 | if (ch->iostart) |
249 | ch->cmt->info->write_control(ch->iostart, 0, value); | |
250 | else | |
251 | ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); | |
1b56b96b MD |
252 | } |
253 | ||
81b3b271 | 254 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 255 | { |
81b3b271 | 256 | return ch->cmt->info->read_control(ch->ioctrl, CMCSR); |
3fb1b6ad MD |
257 | } |
258 | ||
81b3b271 | 259 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
260 | unsigned long value) |
261 | { | |
81b3b271 | 262 | ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); |
1b56b96b MD |
263 | } |
264 | ||
81b3b271 | 265 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 266 | { |
81b3b271 | 267 | return ch->cmt->info->read_count(ch->ioctrl, CMCNT); |
1b56b96b MD |
268 | } |
269 | ||
7269f933 | 270 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
271 | unsigned long value) |
272 | { | |
81b3b271 | 273 | ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); |
1b56b96b MD |
274 | } |
275 | ||
7269f933 | 276 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
277 | unsigned long value) |
278 | { | |
81b3b271 | 279 | ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); |
1b56b96b MD |
280 | } |
281 | ||
7269f933 | 282 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
283 | int *has_wrapped) |
284 | { | |
285 | unsigned long v1, v2, v3; | |
5b644c7a MD |
286 | int o1, o2; |
287 | ||
2cda3ac4 | 288 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
3fb1b6ad MD |
289 | |
290 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
291 | do { | |
5b644c7a | 292 | o2 = o1; |
7269f933 LP |
293 | v1 = sh_cmt_read_cmcnt(ch); |
294 | v2 = sh_cmt_read_cmcnt(ch); | |
295 | v3 = sh_cmt_read_cmcnt(ch); | |
2cda3ac4 | 296 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; |
5b644c7a MD |
297 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
298 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 299 | |
5b644c7a | 300 | *has_wrapped = o1; |
3fb1b6ad MD |
301 | return v2; |
302 | } | |
303 | ||
7269f933 | 304 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 305 | { |
3fb1b6ad MD |
306 | unsigned long flags, value; |
307 | ||
308 | /* start stop register shared by multiple timer channels */ | |
de599c88 | 309 | raw_spin_lock_irqsave(&ch->cmt->lock, flags); |
7269f933 | 310 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
311 | |
312 | if (start) | |
81b3b271 | 313 | value |= 1 << ch->timer_bit; |
3fb1b6ad | 314 | else |
81b3b271 | 315 | value &= ~(1 << ch->timer_bit); |
3fb1b6ad | 316 | |
7269f933 | 317 | sh_cmt_write_cmstr(ch, value); |
de599c88 | 318 | raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); |
3fb1b6ad MD |
319 | } |
320 | ||
7269f933 | 321 | static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) |
3fb1b6ad | 322 | { |
3f7e5e24 | 323 | int k, ret; |
3fb1b6ad | 324 | |
7269f933 LP |
325 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
326 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 327 | |
9436b4ab | 328 | /* enable clock */ |
7269f933 | 329 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 330 | if (ret) { |
740a9518 LP |
331 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
332 | ch->index); | |
3f7e5e24 | 333 | goto err0; |
3fb1b6ad | 334 | } |
3fb1b6ad MD |
335 | |
336 | /* make sure channel is disabled */ | |
7269f933 | 337 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
338 | |
339 | /* configure channel, periodic mode and maximum timeout */ | |
2cda3ac4 | 340 | if (ch->cmt->info->width == 16) { |
7269f933 | 341 | *rate = clk_get_rate(ch->cmt->clk) / 512; |
d14be99b LP |
342 | sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE | |
343 | SH_CMT16_CMCSR_CKS512); | |
3014f474 | 344 | } else { |
7269f933 | 345 | *rate = clk_get_rate(ch->cmt->clk) / 8; |
d14be99b LP |
346 | sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM | |
347 | SH_CMT32_CMCSR_CMTOUT_IE | | |
348 | SH_CMT32_CMCSR_CMR_IRQ | | |
349 | SH_CMT32_CMCSR_CKS_RCLK8); | |
3014f474 | 350 | } |
3fb1b6ad | 351 | |
7269f933 LP |
352 | sh_cmt_write_cmcor(ch, 0xffffffff); |
353 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 354 | |
3f7e5e24 MD |
355 | /* |
356 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
357 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
358 | * modifying CMCNT register; two RCLK cycles are necessary before | |
359 | * this register is either read or any modification of the value | |
360 | * it holds is reflected in the LSI's actual operation. | |
361 | * | |
362 | * While at it, we're supposed to clear out the CMCNT as of this | |
363 | * moment, so make sure it's processed properly here. This will | |
364 | * take RCLKx2 at maximum. | |
365 | */ | |
366 | for (k = 0; k < 100; k++) { | |
7269f933 | 367 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
368 | break; |
369 | udelay(1); | |
370 | } | |
371 | ||
7269f933 | 372 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
373 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
374 | ch->index); | |
3f7e5e24 MD |
375 | ret = -ETIMEDOUT; |
376 | goto err1; | |
377 | } | |
378 | ||
3fb1b6ad | 379 | /* enable channel */ |
7269f933 | 380 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 381 | return 0; |
3f7e5e24 MD |
382 | err1: |
383 | /* stop clock */ | |
7269f933 | 384 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
385 | |
386 | err0: | |
387 | return ret; | |
3fb1b6ad MD |
388 | } |
389 | ||
7269f933 | 390 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
391 | { |
392 | /* disable channel */ | |
7269f933 | 393 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 394 | |
be890a1a | 395 | /* disable interrupts in CMT block */ |
7269f933 | 396 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 397 | |
9436b4ab | 398 | /* stop clock */ |
7269f933 | 399 | clk_disable(ch->cmt->clk); |
bad81383 | 400 | |
7269f933 LP |
401 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
402 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
403 | } |
404 | ||
405 | /* private flags */ | |
406 | #define FLAG_CLOCKEVENT (1 << 0) | |
407 | #define FLAG_CLOCKSOURCE (1 << 1) | |
408 | #define FLAG_REPROGRAM (1 << 2) | |
409 | #define FLAG_SKIPEVENT (1 << 3) | |
410 | #define FLAG_IRQCONTEXT (1 << 4) | |
411 | ||
7269f933 | 412 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
413 | int absolute) |
414 | { | |
415 | unsigned long new_match; | |
7269f933 | 416 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
417 | unsigned long delay = 0; |
418 | unsigned long now = 0; | |
419 | int has_wrapped; | |
420 | ||
7269f933 LP |
421 | now = sh_cmt_get_counter(ch, &has_wrapped); |
422 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
423 | |
424 | if (has_wrapped) { | |
425 | /* we're competing with the interrupt handler. | |
426 | * -> let the interrupt handler reprogram the timer. | |
427 | * -> interrupt number two handles the event. | |
428 | */ | |
7269f933 | 429 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
430 | return; |
431 | } | |
432 | ||
433 | if (absolute) | |
434 | now = 0; | |
435 | ||
436 | do { | |
437 | /* reprogram the timer hardware, | |
438 | * but don't save the new match value yet. | |
439 | */ | |
440 | new_match = now + value + delay; | |
7269f933 LP |
441 | if (new_match > ch->max_match_value) |
442 | new_match = ch->max_match_value; | |
3fb1b6ad | 443 | |
7269f933 | 444 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 445 | |
7269f933 LP |
446 | now = sh_cmt_get_counter(ch, &has_wrapped); |
447 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
448 | /* we are changing to a greater match value, |
449 | * so this wrap must be caused by the counter | |
450 | * matching the old value. | |
451 | * -> first interrupt reprograms the timer. | |
452 | * -> interrupt number two handles the event. | |
453 | */ | |
7269f933 | 454 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
455 | break; |
456 | } | |
457 | ||
458 | if (has_wrapped) { | |
459 | /* we are changing to a smaller match value, | |
460 | * so the wrap must be caused by the counter | |
461 | * matching the new value. | |
462 | * -> save programmed match value. | |
463 | * -> let isr handle the event. | |
464 | */ | |
7269f933 | 465 | ch->match_value = new_match; |
3fb1b6ad MD |
466 | break; |
467 | } | |
468 | ||
469 | /* be safe: verify hardware settings */ | |
470 | if (now < new_match) { | |
471 | /* timer value is below match value, all good. | |
472 | * this makes sure we won't miss any match events. | |
473 | * -> save programmed match value. | |
474 | * -> let isr handle the event. | |
475 | */ | |
7269f933 | 476 | ch->match_value = new_match; |
3fb1b6ad MD |
477 | break; |
478 | } | |
479 | ||
480 | /* the counter has reached a value greater | |
481 | * than our new match value. and since the | |
482 | * has_wrapped flag isn't set we must have | |
483 | * programmed a too close event. | |
484 | * -> increase delay and retry. | |
485 | */ | |
486 | if (delay) | |
487 | delay <<= 1; | |
488 | else | |
489 | delay = 1; | |
490 | ||
491 | if (!delay) | |
740a9518 LP |
492 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
493 | ch->index); | |
3fb1b6ad MD |
494 | |
495 | } while (delay); | |
496 | } | |
497 | ||
7269f933 | 498 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 499 | { |
7269f933 | 500 | if (delta > ch->max_match_value) |
740a9518 LP |
501 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
502 | ch->index); | |
3fb1b6ad | 503 | |
7269f933 LP |
504 | ch->next_match_value = delta; |
505 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
506 | } |
507 | ||
7269f933 | 508 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
509 | { |
510 | unsigned long flags; | |
511 | ||
7269f933 LP |
512 | raw_spin_lock_irqsave(&ch->lock, flags); |
513 | __sh_cmt_set_next(ch, delta); | |
514 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
515 | } |
516 | ||
517 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
518 | { | |
7269f933 | 519 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
520 | |
521 | /* clear flags */ | |
2cda3ac4 LP |
522 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & |
523 | ch->cmt->info->clear_bits); | |
3fb1b6ad MD |
524 | |
525 | /* update clock source counter to begin with if enabled | |
526 | * the wrap flag should be cleared by the timer specific | |
527 | * isr before we end up here. | |
528 | */ | |
7269f933 LP |
529 | if (ch->flags & FLAG_CLOCKSOURCE) |
530 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 531 | |
7269f933 LP |
532 | if (!(ch->flags & FLAG_REPROGRAM)) |
533 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 534 | |
7269f933 | 535 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 536 | |
7269f933 LP |
537 | if (ch->flags & FLAG_CLOCKEVENT) { |
538 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
539 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
540 | ch->next_match_value = ch->max_match_value; | |
541 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
542 | } |
543 | ||
7269f933 | 544 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
545 | } |
546 | } | |
547 | ||
7269f933 | 548 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 549 | |
7269f933 LP |
550 | if (ch->flags & FLAG_REPROGRAM) { |
551 | ch->flags &= ~FLAG_REPROGRAM; | |
552 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 553 | |
7269f933 LP |
554 | if (ch->flags & FLAG_CLOCKEVENT) |
555 | if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
556 | || (ch->match_value == ch->next_match_value)) | |
557 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
558 | } |
559 | ||
7269f933 | 560 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
561 | |
562 | return IRQ_HANDLED; | |
563 | } | |
564 | ||
7269f933 | 565 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
566 | { |
567 | int ret = 0; | |
568 | unsigned long flags; | |
569 | ||
7269f933 | 570 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 571 | |
7269f933 LP |
572 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
573 | ret = sh_cmt_enable(ch, &ch->rate); | |
3fb1b6ad MD |
574 | |
575 | if (ret) | |
576 | goto out; | |
7269f933 | 577 | ch->flags |= flag; |
3fb1b6ad MD |
578 | |
579 | /* setup timeout if no clockevent */ | |
7269f933 LP |
580 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
581 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 582 | out: |
7269f933 | 583 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
584 | |
585 | return ret; | |
586 | } | |
587 | ||
7269f933 | 588 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
589 | { |
590 | unsigned long flags; | |
591 | unsigned long f; | |
592 | ||
7269f933 | 593 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 594 | |
7269f933 LP |
595 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
596 | ch->flags &= ~flag; | |
3fb1b6ad | 597 | |
7269f933 LP |
598 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
599 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
600 | |
601 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
602 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
603 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 604 | |
7269f933 | 605 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
606 | } |
607 | ||
7269f933 | 608 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 609 | { |
7269f933 | 610 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
611 | } |
612 | ||
613 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
614 | { | |
7269f933 | 615 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
616 | unsigned long flags, raw; |
617 | unsigned long value; | |
618 | int has_wrapped; | |
619 | ||
7269f933 LP |
620 | raw_spin_lock_irqsave(&ch->lock, flags); |
621 | value = ch->total_cycles; | |
622 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
623 | |
624 | if (unlikely(has_wrapped)) | |
7269f933 LP |
625 | raw += ch->match_value + 1; |
626 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
627 | |
628 | return value + raw; | |
629 | } | |
630 | ||
631 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
632 | { | |
3593f5fe | 633 | int ret; |
7269f933 | 634 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 635 | |
7269f933 | 636 | WARN_ON(ch->cs_enabled); |
bad81383 | 637 | |
7269f933 | 638 | ch->total_cycles = 0; |
19bdc9d0 | 639 | |
7269f933 | 640 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
bad81383 | 641 | if (!ret) { |
7269f933 LP |
642 | __clocksource_updatefreq_hz(cs, ch->rate); |
643 | ch->cs_enabled = true; | |
bad81383 | 644 | } |
3593f5fe | 645 | return ret; |
19bdc9d0 MD |
646 | } |
647 | ||
648 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
649 | { | |
7269f933 | 650 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 651 | |
7269f933 | 652 | WARN_ON(!ch->cs_enabled); |
bad81383 | 653 | |
7269f933 LP |
654 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
655 | ch->cs_enabled = false; | |
19bdc9d0 MD |
656 | } |
657 | ||
9bb5ec88 RW |
658 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
659 | { | |
7269f933 | 660 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 661 | |
7269f933 LP |
662 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
663 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
664 | } |
665 | ||
c8162884 MD |
666 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
667 | { | |
7269f933 | 668 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 669 | |
7269f933 LP |
670 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
671 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
672 | } |
673 | ||
7269f933 | 674 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
fb28a659 | 675 | const char *name) |
19bdc9d0 | 676 | { |
7269f933 | 677 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
678 | |
679 | cs->name = name; | |
fb28a659 | 680 | cs->rating = 125; |
19bdc9d0 MD |
681 | cs->read = sh_cmt_clocksource_read; |
682 | cs->enable = sh_cmt_clocksource_enable; | |
683 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 684 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 685 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
686 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
687 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 688 | |
740a9518 LP |
689 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
690 | ch->index); | |
f4d7c356 | 691 | |
3593f5fe MD |
692 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ |
693 | clocksource_register_hz(cs, 1); | |
19bdc9d0 MD |
694 | return 0; |
695 | } | |
696 | ||
7269f933 | 697 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 698 | { |
7269f933 | 699 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
700 | } |
701 | ||
7269f933 | 702 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 703 | { |
7269f933 | 704 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad | 705 | |
7269f933 | 706 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
707 | |
708 | /* TODO: calculate good shift from rate and counter bit width */ | |
709 | ||
710 | ced->shift = 32; | |
7269f933 LP |
711 | ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift); |
712 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
3fb1b6ad MD |
713 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
714 | ||
715 | if (periodic) | |
7269f933 | 716 | sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 717 | else |
7269f933 | 718 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
719 | } |
720 | ||
721 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
722 | struct clock_event_device *ced) | |
723 | { | |
7269f933 | 724 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
725 | |
726 | /* deal with old setting first */ | |
727 | switch (ced->mode) { | |
728 | case CLOCK_EVT_MODE_PERIODIC: | |
729 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 730 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
731 | break; |
732 | default: | |
733 | break; | |
734 | } | |
735 | ||
736 | switch (mode) { | |
737 | case CLOCK_EVT_MODE_PERIODIC: | |
7269f933 | 738 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 739 | "ch%u: used for periodic clock events\n", ch->index); |
7269f933 | 740 | sh_cmt_clock_event_start(ch, 1); |
3fb1b6ad MD |
741 | break; |
742 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 743 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 744 | "ch%u: used for oneshot clock events\n", ch->index); |
7269f933 | 745 | sh_cmt_clock_event_start(ch, 0); |
3fb1b6ad MD |
746 | break; |
747 | case CLOCK_EVT_MODE_SHUTDOWN: | |
748 | case CLOCK_EVT_MODE_UNUSED: | |
7269f933 | 749 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
750 | break; |
751 | default: | |
752 | break; | |
753 | } | |
754 | } | |
755 | ||
756 | static int sh_cmt_clock_event_next(unsigned long delta, | |
757 | struct clock_event_device *ced) | |
758 | { | |
7269f933 | 759 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
760 | |
761 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
7269f933 LP |
762 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
763 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 764 | else |
7269f933 | 765 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
766 | |
767 | return 0; | |
768 | } | |
769 | ||
9bb5ec88 RW |
770 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
771 | { | |
7269f933 | 772 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 773 | |
7269f933 LP |
774 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
775 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
776 | } |
777 | ||
778 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
779 | { | |
7269f933 | 780 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 781 | |
7269f933 LP |
782 | clk_prepare(ch->cmt->clk); |
783 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
784 | } |
785 | ||
bfa76bb1 LP |
786 | static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
787 | const char *name) | |
3fb1b6ad | 788 | { |
7269f933 | 789 | struct clock_event_device *ced = &ch->ced; |
bfa76bb1 LP |
790 | int irq; |
791 | int ret; | |
792 | ||
31e912f5 | 793 | irq = platform_get_irq(ch->cmt->pdev, ch->index); |
bfa76bb1 LP |
794 | if (irq < 0) { |
795 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n", | |
796 | ch->index); | |
797 | return irq; | |
798 | } | |
799 | ||
800 | ret = request_irq(irq, sh_cmt_interrupt, | |
801 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
802 | dev_name(&ch->cmt->pdev->dev), ch); | |
803 | if (ret) { | |
804 | dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", | |
805 | ch->index, irq); | |
806 | return ret; | |
807 | } | |
3fb1b6ad | 808 | |
3fb1b6ad MD |
809 | ced->name = name; |
810 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
811 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
b7fcbb0f | 812 | ced->rating = 125; |
f1ebe1e4 | 813 | ced->cpumask = cpu_possible_mask; |
3fb1b6ad MD |
814 | ced->set_next_event = sh_cmt_clock_event_next; |
815 | ced->set_mode = sh_cmt_clock_event_mode; | |
9bb5ec88 RW |
816 | ced->suspend = sh_cmt_clock_event_suspend; |
817 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 818 | |
740a9518 LP |
819 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
820 | ch->index); | |
3fb1b6ad | 821 | clockevents_register_device(ced); |
bfa76bb1 LP |
822 | |
823 | return 0; | |
3fb1b6ad MD |
824 | } |
825 | ||
1d053e1d | 826 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
fb28a659 | 827 | bool clockevent, bool clocksource) |
3fb1b6ad | 828 | { |
bfa76bb1 LP |
829 | int ret; |
830 | ||
81b3b271 LP |
831 | if (clockevent) { |
832 | ch->cmt->has_clockevent = true; | |
bfa76bb1 LP |
833 | ret = sh_cmt_register_clockevent(ch, name); |
834 | if (ret < 0) | |
835 | return ret; | |
81b3b271 | 836 | } |
3fb1b6ad | 837 | |
81b3b271 LP |
838 | if (clocksource) { |
839 | ch->cmt->has_clocksource = true; | |
fb28a659 | 840 | sh_cmt_register_clocksource(ch, name); |
81b3b271 | 841 | } |
19bdc9d0 | 842 | |
3fb1b6ad MD |
843 | return 0; |
844 | } | |
845 | ||
740a9518 | 846 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
81b3b271 LP |
847 | unsigned int hwidx, bool clockevent, |
848 | bool clocksource, struct sh_cmt_device *cmt) | |
b882e7b1 | 849 | { |
b882e7b1 LP |
850 | int ret; |
851 | ||
81b3b271 LP |
852 | /* Skip unused channels. */ |
853 | if (!clockevent && !clocksource) | |
854 | return 0; | |
855 | ||
b882e7b1 | 856 | ch->cmt = cmt; |
740a9518 | 857 | ch->index = index; |
81b3b271 LP |
858 | ch->hwidx = hwidx; |
859 | ||
860 | /* | |
861 | * Compute the address of the channel control register block. For the | |
862 | * timers with a per-channel start/stop register, compute its address | |
863 | * as well. | |
81b3b271 | 864 | */ |
31e912f5 LP |
865 | switch (cmt->info->model) { |
866 | case SH_CMT_16BIT: | |
867 | ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; | |
868 | break; | |
869 | case SH_CMT_32BIT: | |
870 | case SH_CMT_48BIT: | |
871 | ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; | |
872 | break; | |
873 | case SH_CMT_32BIT_FAST: | |
874 | /* | |
875 | * The 32-bit "fast" timer has a single channel at hwidx 5 but | |
876 | * is located at offset 0x40 instead of 0x60 for some reason. | |
877 | */ | |
878 | ch->ioctrl = cmt->mapbase + 0x40; | |
879 | break; | |
880 | case SH_CMT_48BIT_GEN2: | |
881 | ch->iostart = cmt->mapbase + ch->hwidx * 0x100; | |
882 | ch->ioctrl = ch->iostart + 0x10; | |
883 | break; | |
81b3b271 LP |
884 | } |
885 | ||
2cda3ac4 | 886 | if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) |
b882e7b1 LP |
887 | ch->max_match_value = ~0; |
888 | else | |
2cda3ac4 | 889 | ch->max_match_value = (1 << cmt->info->width) - 1; |
b882e7b1 LP |
890 | |
891 | ch->match_value = ch->max_match_value; | |
892 | raw_spin_lock_init(&ch->lock); | |
893 | ||
31e912f5 | 894 | ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx; |
81b3b271 | 895 | |
1d053e1d | 896 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
81b3b271 | 897 | clockevent, clocksource); |
b882e7b1 | 898 | if (ret) { |
740a9518 LP |
899 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
900 | ch->index); | |
b882e7b1 LP |
901 | return ret; |
902 | } | |
903 | ch->cs_enabled = false; | |
904 | ||
b882e7b1 LP |
905 | return 0; |
906 | } | |
907 | ||
81b3b271 | 908 | static int sh_cmt_map_memory(struct sh_cmt_device *cmt) |
3fb1b6ad | 909 | { |
81b3b271 | 910 | struct resource *mem; |
3fb1b6ad | 911 | |
81b3b271 LP |
912 | mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
913 | if (!mem) { | |
914 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); | |
915 | return -ENXIO; | |
916 | } | |
3fb1b6ad | 917 | |
81b3b271 LP |
918 | cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem)); |
919 | if (cmt->mapbase == NULL) { | |
920 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); | |
921 | return -ENXIO; | |
3fb1b6ad MD |
922 | } |
923 | ||
81b3b271 LP |
924 | return 0; |
925 | } | |
926 | ||
81b3b271 LP |
927 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
928 | { | |
929 | struct sh_timer_config *cfg = pdev->dev.platform_data; | |
930 | const struct platform_device_id *id = pdev->id_entry; | |
31e912f5 LP |
931 | unsigned int mask; |
932 | unsigned int i; | |
81b3b271 LP |
933 | int ret; |
934 | ||
935 | memset(cmt, 0, sizeof(*cmt)); | |
936 | cmt->pdev = pdev; | |
de599c88 | 937 | raw_spin_lock_init(&cmt->lock); |
81b3b271 LP |
938 | |
939 | if (!cfg) { | |
940 | dev_err(&cmt->pdev->dev, "missing platform data\n"); | |
941 | return -ENXIO; | |
942 | } | |
943 | ||
944 | cmt->info = (const struct sh_cmt_info *)id->driver_data; | |
81b3b271 LP |
945 | |
946 | /* Get hold of clock. */ | |
31e912f5 | 947 | cmt->clk = clk_get(&cmt->pdev->dev, "fck"); |
2653caf4 LP |
948 | if (IS_ERR(cmt->clk)) { |
949 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
81b3b271 | 950 | return PTR_ERR(cmt->clk); |
3fb1b6ad MD |
951 | } |
952 | ||
2653caf4 | 953 | ret = clk_prepare(cmt->clk); |
57dee992 | 954 | if (ret < 0) |
81b3b271 | 955 | goto err_clk_put; |
57dee992 | 956 | |
31e912f5 LP |
957 | /* Map the memory resource(s). */ |
958 | ret = sh_cmt_map_memory(cmt); | |
81b3b271 LP |
959 | if (ret < 0) |
960 | goto err_clk_unprepare; | |
961 | ||
962 | /* Allocate and setup the channels. */ | |
31e912f5 | 963 | cmt->num_channels = hweight8(cfg->channels_mask); |
81b3b271 LP |
964 | |
965 | cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels), | |
966 | GFP_KERNEL); | |
f5ec9b19 LP |
967 | if (cmt->channels == NULL) { |
968 | ret = -ENOMEM; | |
81b3b271 | 969 | goto err_unmap; |
f5ec9b19 LP |
970 | } |
971 | ||
31e912f5 LP |
972 | /* |
973 | * Use the first channel as a clock event device and the second channel | |
974 | * as a clock source. If only one channel is available use it for both. | |
975 | */ | |
976 | for (i = 0, mask = cfg->channels_mask; i < cmt->num_channels; ++i) { | |
977 | unsigned int hwidx = ffs(mask) - 1; | |
978 | bool clocksource = i == 1 || cmt->num_channels == 1; | |
979 | bool clockevent = i == 0; | |
980 | ||
981 | ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, | |
982 | clockevent, clocksource, cmt); | |
81b3b271 LP |
983 | if (ret < 0) |
984 | goto err_unmap; | |
f5ec9b19 | 985 | |
31e912f5 | 986 | mask &= ~(1 << hwidx); |
81b3b271 | 987 | } |
da64c2a8 | 988 | |
2653caf4 | 989 | platform_set_drvdata(pdev, cmt); |
adccc69e | 990 | |
da64c2a8 | 991 | return 0; |
81b3b271 LP |
992 | |
993 | err_unmap: | |
f5ec9b19 | 994 | kfree(cmt->channels); |
31e912f5 | 995 | iounmap(cmt->mapbase); |
81b3b271 | 996 | err_clk_unprepare: |
2653caf4 | 997 | clk_unprepare(cmt->clk); |
81b3b271 | 998 | err_clk_put: |
2653caf4 | 999 | clk_put(cmt->clk); |
3fb1b6ad MD |
1000 | return ret; |
1001 | } | |
1002 | ||
1850514b | 1003 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 1004 | { |
2653caf4 | 1005 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
3fb1b6ad MD |
1006 | int ret; |
1007 | ||
9bb5ec88 | 1008 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
1009 | pm_runtime_set_active(&pdev->dev); |
1010 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 1011 | } |
615a445f | 1012 | |
2653caf4 | 1013 | if (cmt) { |
214a607a | 1014 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 1015 | goto out; |
e475eedb MD |
1016 | } |
1017 | ||
b262bc74 | 1018 | cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); |
0178f41d | 1019 | if (cmt == NULL) |
3fb1b6ad | 1020 | return -ENOMEM; |
3fb1b6ad | 1021 | |
2653caf4 | 1022 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 1023 | if (ret) { |
2653caf4 | 1024 | kfree(cmt); |
bad81383 RW |
1025 | pm_runtime_idle(&pdev->dev); |
1026 | return ret; | |
3fb1b6ad | 1027 | } |
bad81383 RW |
1028 | if (is_early_platform_device(pdev)) |
1029 | return 0; | |
1030 | ||
1031 | out: | |
81b3b271 | 1032 | if (cmt->has_clockevent || cmt->has_clocksource) |
bad81383 RW |
1033 | pm_runtime_irq_safe(&pdev->dev); |
1034 | else | |
1035 | pm_runtime_idle(&pdev->dev); | |
1036 | ||
1037 | return 0; | |
3fb1b6ad MD |
1038 | } |
1039 | ||
1850514b | 1040 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
1041 | { |
1042 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
1043 | } | |
1044 | ||
81b3b271 | 1045 | static const struct platform_device_id sh_cmt_id_table[] = { |
81b3b271 LP |
1046 | { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] }, |
1047 | { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] }, | |
1048 | { "sh-cmt-32-fast", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT_FAST] }, | |
1049 | { "sh-cmt-48", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT] }, | |
1050 | { "sh-cmt-48-gen2", (kernel_ulong_t)&sh_cmt_info[SH_CMT_48BIT_GEN2] }, | |
1051 | { } | |
1052 | }; | |
1053 | MODULE_DEVICE_TABLE(platform, sh_cmt_id_table); | |
1054 | ||
3fb1b6ad MD |
1055 | static struct platform_driver sh_cmt_device_driver = { |
1056 | .probe = sh_cmt_probe, | |
1850514b | 1057 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
1058 | .driver = { |
1059 | .name = "sh_cmt", | |
81b3b271 LP |
1060 | }, |
1061 | .id_table = sh_cmt_id_table, | |
3fb1b6ad MD |
1062 | }; |
1063 | ||
1064 | static int __init sh_cmt_init(void) | |
1065 | { | |
1066 | return platform_driver_register(&sh_cmt_device_driver); | |
1067 | } | |
1068 | ||
1069 | static void __exit sh_cmt_exit(void) | |
1070 | { | |
1071 | platform_driver_unregister(&sh_cmt_device_driver); | |
1072 | } | |
1073 | ||
e475eedb | 1074 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 1075 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
1076 | module_exit(sh_cmt_exit); |
1077 | ||
1078 | MODULE_AUTHOR("Magnus Damm"); | |
1079 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
1080 | MODULE_LICENSE("GPL v2"); |