Commit | Line | Data |
---|---|---|
3fb1b6ad MD |
1 | /* |
2 | * SuperH Timer Support - CMT | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
3fb1b6ad MD |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/err.h> | |
3f7e5e24 | 29 | #include <linux/delay.h> |
3fb1b6ad MD |
30 | #include <linux/clocksource.h> |
31 | #include <linux/clockchips.h> | |
46a12f74 | 32 | #include <linux/sh_timer.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
7deeab5d | 34 | #include <linux/module.h> |
615a445f | 35 | #include <linux/pm_domain.h> |
bad81383 | 36 | #include <linux/pm_runtime.h> |
3fb1b6ad | 37 | |
2653caf4 | 38 | struct sh_cmt_device; |
7269f933 LP |
39 | |
40 | struct sh_cmt_channel { | |
2653caf4 | 41 | struct sh_cmt_device *cmt; |
740a9518 | 42 | unsigned int index; |
3fb1b6ad | 43 | |
c924d2d2 LP |
44 | void __iomem *base; |
45 | ||
3fb1b6ad MD |
46 | unsigned long flags; |
47 | unsigned long match_value; | |
48 | unsigned long next_match_value; | |
49 | unsigned long max_match_value; | |
50 | unsigned long rate; | |
7d0c399f | 51 | raw_spinlock_t lock; |
3fb1b6ad | 52 | struct clock_event_device ced; |
19bdc9d0 | 53 | struct clocksource cs; |
3fb1b6ad | 54 | unsigned long total_cycles; |
bad81383 | 55 | bool cs_enabled; |
7269f933 LP |
56 | }; |
57 | ||
2653caf4 | 58 | struct sh_cmt_device { |
7269f933 LP |
59 | struct platform_device *pdev; |
60 | ||
36f1ac98 | 61 | void __iomem *mapbase_ch; |
7269f933 | 62 | void __iomem *mapbase; |
7269f933 LP |
63 | struct clk *clk; |
64 | ||
65 | struct sh_cmt_channel channel; | |
66 | ||
67 | unsigned long width; /* 16 or 32 bit version of hardware block */ | |
68 | unsigned long overflow_bit; | |
69 | unsigned long clear_bits; | |
a6a912ca | 70 | |
cccd7045 MD |
71 | /* callbacks for CMSTR and CMCSR access */ |
72 | unsigned long (*read_control)(void __iomem *base, unsigned long offs); | |
73 | void (*write_control)(void __iomem *base, unsigned long offs, | |
74 | unsigned long value); | |
75 | ||
a6a912ca MD |
76 | /* callbacks for CMCNT and CMCOR access */ |
77 | unsigned long (*read_count)(void __iomem *base, unsigned long offs); | |
78 | void (*write_count)(void __iomem *base, unsigned long offs, | |
79 | unsigned long value); | |
3fb1b6ad MD |
80 | }; |
81 | ||
118aee4d MD |
82 | /* Examples of supported CMT timer register layouts and I/O access widths: |
83 | * | |
84 | * "16-bit counter and 16-bit control" as found on sh7263: | |
85 | * CMSTR 0xfffec000 16-bit | |
86 | * CMCSR 0xfffec002 16-bit | |
87 | * CMCNT 0xfffec004 16-bit | |
88 | * CMCOR 0xfffec006 16-bit | |
89 | * | |
90 | * "32-bit counter and 16-bit control" as found on sh7372, sh73a0, r8a7740: | |
91 | * CMSTR 0xffca0000 16-bit | |
92 | * CMCSR 0xffca0060 16-bit | |
93 | * CMCNT 0xffca0064 32-bit | |
94 | * CMCOR 0xffca0068 32-bit | |
8874c5e3 MD |
95 | * |
96 | * "32-bit counter and 32-bit control" as found on r8a73a4 and r8a7790: | |
97 | * CMSTR 0xffca0500 32-bit | |
98 | * CMCSR 0xffca0510 32-bit | |
99 | * CMCNT 0xffca0514 32-bit | |
100 | * CMCOR 0xffca0518 32-bit | |
118aee4d MD |
101 | */ |
102 | ||
a6a912ca | 103 | static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs) |
587acb3d MD |
104 | { |
105 | return ioread16(base + (offs << 1)); | |
106 | } | |
107 | ||
a6a912ca MD |
108 | static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs) |
109 | { | |
110 | return ioread32(base + (offs << 2)); | |
111 | } | |
112 | ||
113 | static void sh_cmt_write16(void __iomem *base, unsigned long offs, | |
114 | unsigned long value) | |
587acb3d MD |
115 | { |
116 | iowrite16(value, base + (offs << 1)); | |
117 | } | |
3fb1b6ad | 118 | |
a6a912ca MD |
119 | static void sh_cmt_write32(void __iomem *base, unsigned long offs, |
120 | unsigned long value) | |
121 | { | |
122 | iowrite32(value, base + (offs << 2)); | |
123 | } | |
124 | ||
3fb1b6ad MD |
125 | #define CMCSR 0 /* channel register */ |
126 | #define CMCNT 1 /* channel register */ | |
127 | #define CMCOR 2 /* channel register */ | |
128 | ||
7269f933 | 129 | static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch) |
1b56b96b | 130 | { |
36f1ac98 | 131 | return ch->cmt->read_control(ch->cmt->mapbase, 0); |
1b56b96b MD |
132 | } |
133 | ||
7269f933 | 134 | static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_channel *ch) |
1b56b96b | 135 | { |
c924d2d2 | 136 | return ch->cmt->read_control(ch->base, CMCSR); |
1b56b96b MD |
137 | } |
138 | ||
7269f933 | 139 | static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_channel *ch) |
1b56b96b | 140 | { |
c924d2d2 | 141 | return ch->cmt->read_count(ch->base, CMCNT); |
3fb1b6ad MD |
142 | } |
143 | ||
7269f933 | 144 | static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, |
1b56b96b MD |
145 | unsigned long value) |
146 | { | |
36f1ac98 | 147 | ch->cmt->write_control(ch->cmt->mapbase, 0, value); |
1b56b96b MD |
148 | } |
149 | ||
7269f933 | 150 | static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, |
1b56b96b MD |
151 | unsigned long value) |
152 | { | |
c924d2d2 | 153 | ch->cmt->write_control(ch->base, CMCSR, value); |
1b56b96b MD |
154 | } |
155 | ||
7269f933 | 156 | static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, |
1b56b96b MD |
157 | unsigned long value) |
158 | { | |
c924d2d2 | 159 | ch->cmt->write_count(ch->base, CMCNT, value); |
1b56b96b MD |
160 | } |
161 | ||
7269f933 | 162 | static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, |
1b56b96b MD |
163 | unsigned long value) |
164 | { | |
c924d2d2 | 165 | ch->cmt->write_count(ch->base, CMCOR, value); |
1b56b96b MD |
166 | } |
167 | ||
7269f933 | 168 | static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
169 | int *has_wrapped) |
170 | { | |
171 | unsigned long v1, v2, v3; | |
5b644c7a MD |
172 | int o1, o2; |
173 | ||
7269f933 | 174 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->overflow_bit; |
3fb1b6ad MD |
175 | |
176 | /* Make sure the timer value is stable. Stolen from acpi_pm.c */ | |
177 | do { | |
5b644c7a | 178 | o2 = o1; |
7269f933 LP |
179 | v1 = sh_cmt_read_cmcnt(ch); |
180 | v2 = sh_cmt_read_cmcnt(ch); | |
181 | v3 = sh_cmt_read_cmcnt(ch); | |
182 | o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->overflow_bit; | |
5b644c7a MD |
183 | } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3) |
184 | || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2))); | |
3fb1b6ad | 185 | |
5b644c7a | 186 | *has_wrapped = o1; |
3fb1b6ad MD |
187 | return v2; |
188 | } | |
189 | ||
587acb3d | 190 | static DEFINE_RAW_SPINLOCK(sh_cmt_lock); |
3fb1b6ad | 191 | |
7269f933 | 192 | static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) |
3fb1b6ad | 193 | { |
7269f933 | 194 | struct sh_timer_config *cfg = ch->cmt->pdev->dev.platform_data; |
3fb1b6ad MD |
195 | unsigned long flags, value; |
196 | ||
197 | /* start stop register shared by multiple timer channels */ | |
7d0c399f | 198 | raw_spin_lock_irqsave(&sh_cmt_lock, flags); |
7269f933 | 199 | value = sh_cmt_read_cmstr(ch); |
3fb1b6ad MD |
200 | |
201 | if (start) | |
202 | value |= 1 << cfg->timer_bit; | |
203 | else | |
204 | value &= ~(1 << cfg->timer_bit); | |
205 | ||
7269f933 | 206 | sh_cmt_write_cmstr(ch, value); |
7d0c399f | 207 | raw_spin_unlock_irqrestore(&sh_cmt_lock, flags); |
3fb1b6ad MD |
208 | } |
209 | ||
7269f933 | 210 | static int sh_cmt_enable(struct sh_cmt_channel *ch, unsigned long *rate) |
3fb1b6ad | 211 | { |
3f7e5e24 | 212 | int k, ret; |
3fb1b6ad | 213 | |
7269f933 LP |
214 | pm_runtime_get_sync(&ch->cmt->pdev->dev); |
215 | dev_pm_syscore_device(&ch->cmt->pdev->dev, true); | |
bad81383 | 216 | |
9436b4ab | 217 | /* enable clock */ |
7269f933 | 218 | ret = clk_enable(ch->cmt->clk); |
3fb1b6ad | 219 | if (ret) { |
740a9518 LP |
220 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", |
221 | ch->index); | |
3f7e5e24 | 222 | goto err0; |
3fb1b6ad | 223 | } |
3fb1b6ad MD |
224 | |
225 | /* make sure channel is disabled */ | |
7269f933 | 226 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad MD |
227 | |
228 | /* configure channel, periodic mode and maximum timeout */ | |
7269f933 LP |
229 | if (ch->cmt->width == 16) { |
230 | *rate = clk_get_rate(ch->cmt->clk) / 512; | |
231 | sh_cmt_write_cmcsr(ch, 0x43); | |
3014f474 | 232 | } else { |
7269f933 LP |
233 | *rate = clk_get_rate(ch->cmt->clk) / 8; |
234 | sh_cmt_write_cmcsr(ch, 0x01a4); | |
3014f474 | 235 | } |
3fb1b6ad | 236 | |
7269f933 LP |
237 | sh_cmt_write_cmcor(ch, 0xffffffff); |
238 | sh_cmt_write_cmcnt(ch, 0); | |
3fb1b6ad | 239 | |
3f7e5e24 MD |
240 | /* |
241 | * According to the sh73a0 user's manual, as CMCNT can be operated | |
242 | * only by the RCLK (Pseudo 32 KHz), there's one restriction on | |
243 | * modifying CMCNT register; two RCLK cycles are necessary before | |
244 | * this register is either read or any modification of the value | |
245 | * it holds is reflected in the LSI's actual operation. | |
246 | * | |
247 | * While at it, we're supposed to clear out the CMCNT as of this | |
248 | * moment, so make sure it's processed properly here. This will | |
249 | * take RCLKx2 at maximum. | |
250 | */ | |
251 | for (k = 0; k < 100; k++) { | |
7269f933 | 252 | if (!sh_cmt_read_cmcnt(ch)) |
3f7e5e24 MD |
253 | break; |
254 | udelay(1); | |
255 | } | |
256 | ||
7269f933 | 257 | if (sh_cmt_read_cmcnt(ch)) { |
740a9518 LP |
258 | dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", |
259 | ch->index); | |
3f7e5e24 MD |
260 | ret = -ETIMEDOUT; |
261 | goto err1; | |
262 | } | |
263 | ||
3fb1b6ad | 264 | /* enable channel */ |
7269f933 | 265 | sh_cmt_start_stop_ch(ch, 1); |
3fb1b6ad | 266 | return 0; |
3f7e5e24 MD |
267 | err1: |
268 | /* stop clock */ | |
7269f933 | 269 | clk_disable(ch->cmt->clk); |
3f7e5e24 MD |
270 | |
271 | err0: | |
272 | return ret; | |
3fb1b6ad MD |
273 | } |
274 | ||
7269f933 | 275 | static void sh_cmt_disable(struct sh_cmt_channel *ch) |
3fb1b6ad MD |
276 | { |
277 | /* disable channel */ | |
7269f933 | 278 | sh_cmt_start_stop_ch(ch, 0); |
3fb1b6ad | 279 | |
be890a1a | 280 | /* disable interrupts in CMT block */ |
7269f933 | 281 | sh_cmt_write_cmcsr(ch, 0); |
be890a1a | 282 | |
9436b4ab | 283 | /* stop clock */ |
7269f933 | 284 | clk_disable(ch->cmt->clk); |
bad81383 | 285 | |
7269f933 LP |
286 | dev_pm_syscore_device(&ch->cmt->pdev->dev, false); |
287 | pm_runtime_put(&ch->cmt->pdev->dev); | |
3fb1b6ad MD |
288 | } |
289 | ||
290 | /* private flags */ | |
291 | #define FLAG_CLOCKEVENT (1 << 0) | |
292 | #define FLAG_CLOCKSOURCE (1 << 1) | |
293 | #define FLAG_REPROGRAM (1 << 2) | |
294 | #define FLAG_SKIPEVENT (1 << 3) | |
295 | #define FLAG_IRQCONTEXT (1 << 4) | |
296 | ||
7269f933 | 297 | static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch, |
3fb1b6ad MD |
298 | int absolute) |
299 | { | |
300 | unsigned long new_match; | |
7269f933 | 301 | unsigned long value = ch->next_match_value; |
3fb1b6ad MD |
302 | unsigned long delay = 0; |
303 | unsigned long now = 0; | |
304 | int has_wrapped; | |
305 | ||
7269f933 LP |
306 | now = sh_cmt_get_counter(ch, &has_wrapped); |
307 | ch->flags |= FLAG_REPROGRAM; /* force reprogram */ | |
3fb1b6ad MD |
308 | |
309 | if (has_wrapped) { | |
310 | /* we're competing with the interrupt handler. | |
311 | * -> let the interrupt handler reprogram the timer. | |
312 | * -> interrupt number two handles the event. | |
313 | */ | |
7269f933 | 314 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
315 | return; |
316 | } | |
317 | ||
318 | if (absolute) | |
319 | now = 0; | |
320 | ||
321 | do { | |
322 | /* reprogram the timer hardware, | |
323 | * but don't save the new match value yet. | |
324 | */ | |
325 | new_match = now + value + delay; | |
7269f933 LP |
326 | if (new_match > ch->max_match_value) |
327 | new_match = ch->max_match_value; | |
3fb1b6ad | 328 | |
7269f933 | 329 | sh_cmt_write_cmcor(ch, new_match); |
3fb1b6ad | 330 | |
7269f933 LP |
331 | now = sh_cmt_get_counter(ch, &has_wrapped); |
332 | if (has_wrapped && (new_match > ch->match_value)) { | |
3fb1b6ad MD |
333 | /* we are changing to a greater match value, |
334 | * so this wrap must be caused by the counter | |
335 | * matching the old value. | |
336 | * -> first interrupt reprograms the timer. | |
337 | * -> interrupt number two handles the event. | |
338 | */ | |
7269f933 | 339 | ch->flags |= FLAG_SKIPEVENT; |
3fb1b6ad MD |
340 | break; |
341 | } | |
342 | ||
343 | if (has_wrapped) { | |
344 | /* we are changing to a smaller match value, | |
345 | * so the wrap must be caused by the counter | |
346 | * matching the new value. | |
347 | * -> save programmed match value. | |
348 | * -> let isr handle the event. | |
349 | */ | |
7269f933 | 350 | ch->match_value = new_match; |
3fb1b6ad MD |
351 | break; |
352 | } | |
353 | ||
354 | /* be safe: verify hardware settings */ | |
355 | if (now < new_match) { | |
356 | /* timer value is below match value, all good. | |
357 | * this makes sure we won't miss any match events. | |
358 | * -> save programmed match value. | |
359 | * -> let isr handle the event. | |
360 | */ | |
7269f933 | 361 | ch->match_value = new_match; |
3fb1b6ad MD |
362 | break; |
363 | } | |
364 | ||
365 | /* the counter has reached a value greater | |
366 | * than our new match value. and since the | |
367 | * has_wrapped flag isn't set we must have | |
368 | * programmed a too close event. | |
369 | * -> increase delay and retry. | |
370 | */ | |
371 | if (delay) | |
372 | delay <<= 1; | |
373 | else | |
374 | delay = 1; | |
375 | ||
376 | if (!delay) | |
740a9518 LP |
377 | dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", |
378 | ch->index); | |
3fb1b6ad MD |
379 | |
380 | } while (delay); | |
381 | } | |
382 | ||
7269f933 | 383 | static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
3fb1b6ad | 384 | { |
7269f933 | 385 | if (delta > ch->max_match_value) |
740a9518 LP |
386 | dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", |
387 | ch->index); | |
3fb1b6ad | 388 | |
7269f933 LP |
389 | ch->next_match_value = delta; |
390 | sh_cmt_clock_event_program_verify(ch, 0); | |
65ada547 TY |
391 | } |
392 | ||
7269f933 | 393 | static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta) |
65ada547 TY |
394 | { |
395 | unsigned long flags; | |
396 | ||
7269f933 LP |
397 | raw_spin_lock_irqsave(&ch->lock, flags); |
398 | __sh_cmt_set_next(ch, delta); | |
399 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
3fb1b6ad MD |
400 | } |
401 | ||
402 | static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id) | |
403 | { | |
7269f933 | 404 | struct sh_cmt_channel *ch = dev_id; |
3fb1b6ad MD |
405 | |
406 | /* clear flags */ | |
7269f933 | 407 | sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) & ch->cmt->clear_bits); |
3fb1b6ad MD |
408 | |
409 | /* update clock source counter to begin with if enabled | |
410 | * the wrap flag should be cleared by the timer specific | |
411 | * isr before we end up here. | |
412 | */ | |
7269f933 LP |
413 | if (ch->flags & FLAG_CLOCKSOURCE) |
414 | ch->total_cycles += ch->match_value + 1; | |
3fb1b6ad | 415 | |
7269f933 LP |
416 | if (!(ch->flags & FLAG_REPROGRAM)) |
417 | ch->next_match_value = ch->max_match_value; | |
3fb1b6ad | 418 | |
7269f933 | 419 | ch->flags |= FLAG_IRQCONTEXT; |
3fb1b6ad | 420 | |
7269f933 LP |
421 | if (ch->flags & FLAG_CLOCKEVENT) { |
422 | if (!(ch->flags & FLAG_SKIPEVENT)) { | |
423 | if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT) { | |
424 | ch->next_match_value = ch->max_match_value; | |
425 | ch->flags |= FLAG_REPROGRAM; | |
3fb1b6ad MD |
426 | } |
427 | ||
7269f933 | 428 | ch->ced.event_handler(&ch->ced); |
3fb1b6ad MD |
429 | } |
430 | } | |
431 | ||
7269f933 | 432 | ch->flags &= ~FLAG_SKIPEVENT; |
3fb1b6ad | 433 | |
7269f933 LP |
434 | if (ch->flags & FLAG_REPROGRAM) { |
435 | ch->flags &= ~FLAG_REPROGRAM; | |
436 | sh_cmt_clock_event_program_verify(ch, 1); | |
3fb1b6ad | 437 | |
7269f933 LP |
438 | if (ch->flags & FLAG_CLOCKEVENT) |
439 | if ((ch->ced.mode == CLOCK_EVT_MODE_SHUTDOWN) | |
440 | || (ch->match_value == ch->next_match_value)) | |
441 | ch->flags &= ~FLAG_REPROGRAM; | |
3fb1b6ad MD |
442 | } |
443 | ||
7269f933 | 444 | ch->flags &= ~FLAG_IRQCONTEXT; |
3fb1b6ad MD |
445 | |
446 | return IRQ_HANDLED; | |
447 | } | |
448 | ||
7269f933 | 449 | static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
450 | { |
451 | int ret = 0; | |
452 | unsigned long flags; | |
453 | ||
7269f933 | 454 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 455 | |
7269f933 LP |
456 | if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
457 | ret = sh_cmt_enable(ch, &ch->rate); | |
3fb1b6ad MD |
458 | |
459 | if (ret) | |
460 | goto out; | |
7269f933 | 461 | ch->flags |= flag; |
3fb1b6ad MD |
462 | |
463 | /* setup timeout if no clockevent */ | |
7269f933 LP |
464 | if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) |
465 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 466 | out: |
7269f933 | 467 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
468 | |
469 | return ret; | |
470 | } | |
471 | ||
7269f933 | 472 | static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) |
3fb1b6ad MD |
473 | { |
474 | unsigned long flags; | |
475 | unsigned long f; | |
476 | ||
7269f933 | 477 | raw_spin_lock_irqsave(&ch->lock, flags); |
3fb1b6ad | 478 | |
7269f933 LP |
479 | f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); |
480 | ch->flags &= ~flag; | |
3fb1b6ad | 481 | |
7269f933 LP |
482 | if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) |
483 | sh_cmt_disable(ch); | |
3fb1b6ad MD |
484 | |
485 | /* adjust the timeout to maximum if only clocksource left */ | |
7269f933 LP |
486 | if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) |
487 | __sh_cmt_set_next(ch, ch->max_match_value); | |
3fb1b6ad | 488 | |
7269f933 | 489 | raw_spin_unlock_irqrestore(&ch->lock, flags); |
3fb1b6ad MD |
490 | } |
491 | ||
7269f933 | 492 | static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) |
19bdc9d0 | 493 | { |
7269f933 | 494 | return container_of(cs, struct sh_cmt_channel, cs); |
19bdc9d0 MD |
495 | } |
496 | ||
497 | static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) | |
498 | { | |
7269f933 | 499 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 MD |
500 | unsigned long flags, raw; |
501 | unsigned long value; | |
502 | int has_wrapped; | |
503 | ||
7269f933 LP |
504 | raw_spin_lock_irqsave(&ch->lock, flags); |
505 | value = ch->total_cycles; | |
506 | raw = sh_cmt_get_counter(ch, &has_wrapped); | |
19bdc9d0 MD |
507 | |
508 | if (unlikely(has_wrapped)) | |
7269f933 LP |
509 | raw += ch->match_value + 1; |
510 | raw_spin_unlock_irqrestore(&ch->lock, flags); | |
19bdc9d0 MD |
511 | |
512 | return value + raw; | |
513 | } | |
514 | ||
515 | static int sh_cmt_clocksource_enable(struct clocksource *cs) | |
516 | { | |
3593f5fe | 517 | int ret; |
7269f933 | 518 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
19bdc9d0 | 519 | |
7269f933 | 520 | WARN_ON(ch->cs_enabled); |
bad81383 | 521 | |
7269f933 | 522 | ch->total_cycles = 0; |
19bdc9d0 | 523 | |
7269f933 | 524 | ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); |
bad81383 | 525 | if (!ret) { |
7269f933 LP |
526 | __clocksource_updatefreq_hz(cs, ch->rate); |
527 | ch->cs_enabled = true; | |
bad81383 | 528 | } |
3593f5fe | 529 | return ret; |
19bdc9d0 MD |
530 | } |
531 | ||
532 | static void sh_cmt_clocksource_disable(struct clocksource *cs) | |
533 | { | |
7269f933 | 534 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
bad81383 | 535 | |
7269f933 | 536 | WARN_ON(!ch->cs_enabled); |
bad81383 | 537 | |
7269f933 LP |
538 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
539 | ch->cs_enabled = false; | |
19bdc9d0 MD |
540 | } |
541 | ||
9bb5ec88 RW |
542 | static void sh_cmt_clocksource_suspend(struct clocksource *cs) |
543 | { | |
7269f933 | 544 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 545 | |
7269f933 LP |
546 | sh_cmt_stop(ch, FLAG_CLOCKSOURCE); |
547 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
548 | } |
549 | ||
c8162884 MD |
550 | static void sh_cmt_clocksource_resume(struct clocksource *cs) |
551 | { | |
7269f933 | 552 | struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); |
9bb5ec88 | 553 | |
7269f933 LP |
554 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); |
555 | sh_cmt_start(ch, FLAG_CLOCKSOURCE); | |
c8162884 MD |
556 | } |
557 | ||
7269f933 | 558 | static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, |
1d053e1d | 559 | const char *name, unsigned long rating) |
19bdc9d0 | 560 | { |
7269f933 | 561 | struct clocksource *cs = &ch->cs; |
19bdc9d0 MD |
562 | |
563 | cs->name = name; | |
564 | cs->rating = rating; | |
565 | cs->read = sh_cmt_clocksource_read; | |
566 | cs->enable = sh_cmt_clocksource_enable; | |
567 | cs->disable = sh_cmt_clocksource_disable; | |
9bb5ec88 | 568 | cs->suspend = sh_cmt_clocksource_suspend; |
c8162884 | 569 | cs->resume = sh_cmt_clocksource_resume; |
19bdc9d0 MD |
570 | cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); |
571 | cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
f4d7c356 | 572 | |
740a9518 LP |
573 | dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", |
574 | ch->index); | |
f4d7c356 | 575 | |
3593f5fe MD |
576 | /* Register with dummy 1 Hz value, gets updated in ->enable() */ |
577 | clocksource_register_hz(cs, 1); | |
19bdc9d0 MD |
578 | return 0; |
579 | } | |
580 | ||
7269f933 | 581 | static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced) |
3fb1b6ad | 582 | { |
7269f933 | 583 | return container_of(ced, struct sh_cmt_channel, ced); |
3fb1b6ad MD |
584 | } |
585 | ||
7269f933 | 586 | static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) |
3fb1b6ad | 587 | { |
7269f933 | 588 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad | 589 | |
7269f933 | 590 | sh_cmt_start(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
591 | |
592 | /* TODO: calculate good shift from rate and counter bit width */ | |
593 | ||
594 | ced->shift = 32; | |
7269f933 LP |
595 | ced->mult = div_sc(ch->rate, NSEC_PER_SEC, ced->shift); |
596 | ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); | |
3fb1b6ad MD |
597 | ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); |
598 | ||
599 | if (periodic) | |
7269f933 | 600 | sh_cmt_set_next(ch, ((ch->rate + HZ/2) / HZ) - 1); |
3fb1b6ad | 601 | else |
7269f933 | 602 | sh_cmt_set_next(ch, ch->max_match_value); |
3fb1b6ad MD |
603 | } |
604 | ||
605 | static void sh_cmt_clock_event_mode(enum clock_event_mode mode, | |
606 | struct clock_event_device *ced) | |
607 | { | |
7269f933 | 608 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
609 | |
610 | /* deal with old setting first */ | |
611 | switch (ced->mode) { | |
612 | case CLOCK_EVT_MODE_PERIODIC: | |
613 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 614 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
615 | break; |
616 | default: | |
617 | break; | |
618 | } | |
619 | ||
620 | switch (mode) { | |
621 | case CLOCK_EVT_MODE_PERIODIC: | |
7269f933 | 622 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 623 | "ch%u: used for periodic clock events\n", ch->index); |
7269f933 | 624 | sh_cmt_clock_event_start(ch, 1); |
3fb1b6ad MD |
625 | break; |
626 | case CLOCK_EVT_MODE_ONESHOT: | |
7269f933 | 627 | dev_info(&ch->cmt->pdev->dev, |
740a9518 | 628 | "ch%u: used for oneshot clock events\n", ch->index); |
7269f933 | 629 | sh_cmt_clock_event_start(ch, 0); |
3fb1b6ad MD |
630 | break; |
631 | case CLOCK_EVT_MODE_SHUTDOWN: | |
632 | case CLOCK_EVT_MODE_UNUSED: | |
7269f933 | 633 | sh_cmt_stop(ch, FLAG_CLOCKEVENT); |
3fb1b6ad MD |
634 | break; |
635 | default: | |
636 | break; | |
637 | } | |
638 | } | |
639 | ||
640 | static int sh_cmt_clock_event_next(unsigned long delta, | |
641 | struct clock_event_device *ced) | |
642 | { | |
7269f933 | 643 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
3fb1b6ad MD |
644 | |
645 | BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT); | |
7269f933 LP |
646 | if (likely(ch->flags & FLAG_IRQCONTEXT)) |
647 | ch->next_match_value = delta - 1; | |
3fb1b6ad | 648 | else |
7269f933 | 649 | sh_cmt_set_next(ch, delta - 1); |
3fb1b6ad MD |
650 | |
651 | return 0; | |
652 | } | |
653 | ||
9bb5ec88 RW |
654 | static void sh_cmt_clock_event_suspend(struct clock_event_device *ced) |
655 | { | |
7269f933 | 656 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 657 | |
7269f933 LP |
658 | pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); |
659 | clk_unprepare(ch->cmt->clk); | |
9bb5ec88 RW |
660 | } |
661 | ||
662 | static void sh_cmt_clock_event_resume(struct clock_event_device *ced) | |
663 | { | |
7269f933 | 664 | struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); |
57dee992 | 665 | |
7269f933 LP |
666 | clk_prepare(ch->cmt->clk); |
667 | pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); | |
9bb5ec88 RW |
668 | } |
669 | ||
7269f933 | 670 | static void sh_cmt_register_clockevent(struct sh_cmt_channel *ch, |
1d053e1d | 671 | const char *name, unsigned long rating) |
3fb1b6ad | 672 | { |
7269f933 | 673 | struct clock_event_device *ced = &ch->ced; |
3fb1b6ad MD |
674 | |
675 | memset(ced, 0, sizeof(*ced)); | |
676 | ||
677 | ced->name = name; | |
678 | ced->features = CLOCK_EVT_FEAT_PERIODIC; | |
679 | ced->features |= CLOCK_EVT_FEAT_ONESHOT; | |
680 | ced->rating = rating; | |
681 | ced->cpumask = cpumask_of(0); | |
682 | ced->set_next_event = sh_cmt_clock_event_next; | |
683 | ced->set_mode = sh_cmt_clock_event_mode; | |
9bb5ec88 RW |
684 | ced->suspend = sh_cmt_clock_event_suspend; |
685 | ced->resume = sh_cmt_clock_event_resume; | |
3fb1b6ad | 686 | |
740a9518 LP |
687 | dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", |
688 | ch->index); | |
3fb1b6ad MD |
689 | clockevents_register_device(ced); |
690 | } | |
691 | ||
1d053e1d | 692 | static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name, |
d1fcc0a8 PM |
693 | unsigned long clockevent_rating, |
694 | unsigned long clocksource_rating) | |
3fb1b6ad | 695 | { |
3fb1b6ad | 696 | if (clockevent_rating) |
7269f933 | 697 | sh_cmt_register_clockevent(ch, name, clockevent_rating); |
3fb1b6ad | 698 | |
19bdc9d0 | 699 | if (clocksource_rating) |
7269f933 | 700 | sh_cmt_register_clocksource(ch, name, clocksource_rating); |
19bdc9d0 | 701 | |
3fb1b6ad MD |
702 | return 0; |
703 | } | |
704 | ||
740a9518 | 705 | static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index, |
b882e7b1 LP |
706 | struct sh_cmt_device *cmt) |
707 | { | |
708 | struct sh_timer_config *cfg = cmt->pdev->dev.platform_data; | |
709 | int irq; | |
710 | int ret; | |
711 | ||
712 | memset(ch, 0, sizeof(*ch)); | |
713 | ch->cmt = cmt; | |
c924d2d2 | 714 | ch->base = cmt->mapbase_ch; |
740a9518 | 715 | ch->index = index; |
b882e7b1 LP |
716 | |
717 | irq = platform_get_irq(cmt->pdev, 0); | |
718 | if (irq < 0) { | |
740a9518 LP |
719 | dev_err(&cmt->pdev->dev, "ch%u: failed to get irq\n", |
720 | ch->index); | |
b882e7b1 LP |
721 | return irq; |
722 | } | |
723 | ||
724 | if (cmt->width == (sizeof(ch->max_match_value) * 8)) | |
725 | ch->max_match_value = ~0; | |
726 | else | |
727 | ch->max_match_value = (1 << cmt->width) - 1; | |
728 | ||
729 | ch->match_value = ch->max_match_value; | |
730 | raw_spin_lock_init(&ch->lock); | |
731 | ||
1d053e1d | 732 | ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), |
b882e7b1 LP |
733 | cfg->clockevent_rating, |
734 | cfg->clocksource_rating); | |
735 | if (ret) { | |
740a9518 LP |
736 | dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", |
737 | ch->index); | |
b882e7b1 LP |
738 | return ret; |
739 | } | |
740 | ch->cs_enabled = false; | |
741 | ||
742 | ret = request_irq(irq, sh_cmt_interrupt, | |
743 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, | |
744 | dev_name(&cmt->pdev->dev), ch); | |
745 | if (ret) { | |
740a9518 LP |
746 | dev_err(&cmt->pdev->dev, "ch%u: failed to request irq %d\n", |
747 | ch->index, irq); | |
b882e7b1 LP |
748 | return ret; |
749 | } | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
2653caf4 | 754 | static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) |
3fb1b6ad | 755 | { |
46a12f74 | 756 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
8874c5e3 | 757 | struct resource *res, *res2; |
b882e7b1 | 758 | int ret; |
3fb1b6ad MD |
759 | ret = -ENXIO; |
760 | ||
2653caf4 LP |
761 | memset(cmt, 0, sizeof(*cmt)); |
762 | cmt->pdev = pdev; | |
3fb1b6ad MD |
763 | |
764 | if (!cfg) { | |
2653caf4 | 765 | dev_err(&cmt->pdev->dev, "missing platform data\n"); |
3fb1b6ad MD |
766 | goto err0; |
767 | } | |
768 | ||
2653caf4 | 769 | res = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); |
3fb1b6ad | 770 | if (!res) { |
2653caf4 | 771 | dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); |
3fb1b6ad MD |
772 | goto err0; |
773 | } | |
774 | ||
8874c5e3 | 775 | /* optional resource for the shared timer start/stop register */ |
2653caf4 | 776 | res2 = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 1); |
8874c5e3 | 777 | |
36f1ac98 LP |
778 | /* map memory, let mapbase_ch point to our channel */ |
779 | cmt->mapbase_ch = ioremap_nocache(res->start, resource_size(res)); | |
780 | if (cmt->mapbase_ch == NULL) { | |
2653caf4 | 781 | dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); |
3fb1b6ad MD |
782 | goto err0; |
783 | } | |
784 | ||
8874c5e3 | 785 | /* map second resource for CMSTR */ |
36f1ac98 LP |
786 | cmt->mapbase = ioremap_nocache(res2 ? res2->start : |
787 | res->start - cfg->channel_offset, | |
788 | res2 ? resource_size(res2) : 2); | |
789 | if (cmt->mapbase == NULL) { | |
2653caf4 | 790 | dev_err(&cmt->pdev->dev, "failed to remap I/O second memory\n"); |
8874c5e3 MD |
791 | goto err1; |
792 | } | |
793 | ||
3fb1b6ad | 794 | /* get hold of clock */ |
2653caf4 LP |
795 | cmt->clk = clk_get(&cmt->pdev->dev, "cmt_fck"); |
796 | if (IS_ERR(cmt->clk)) { | |
797 | dev_err(&cmt->pdev->dev, "cannot get clock\n"); | |
798 | ret = PTR_ERR(cmt->clk); | |
8874c5e3 | 799 | goto err2; |
3fb1b6ad MD |
800 | } |
801 | ||
2653caf4 | 802 | ret = clk_prepare(cmt->clk); |
57dee992 LP |
803 | if (ret < 0) |
804 | goto err3; | |
805 | ||
8874c5e3 MD |
806 | if (res2 && (resource_size(res2) == 4)) { |
807 | /* assume both CMSTR and CMCSR to be 32-bit */ | |
2653caf4 LP |
808 | cmt->read_control = sh_cmt_read32; |
809 | cmt->write_control = sh_cmt_write32; | |
8874c5e3 | 810 | } else { |
2653caf4 LP |
811 | cmt->read_control = sh_cmt_read16; |
812 | cmt->write_control = sh_cmt_write16; | |
8874c5e3 | 813 | } |
cccd7045 | 814 | |
3fb1b6ad | 815 | if (resource_size(res) == 6) { |
2653caf4 LP |
816 | cmt->width = 16; |
817 | cmt->read_count = sh_cmt_read16; | |
818 | cmt->write_count = sh_cmt_write16; | |
819 | cmt->overflow_bit = 0x80; | |
820 | cmt->clear_bits = ~0x80; | |
3fb1b6ad | 821 | } else { |
2653caf4 LP |
822 | cmt->width = 32; |
823 | cmt->read_count = sh_cmt_read32; | |
824 | cmt->write_count = sh_cmt_write32; | |
825 | cmt->overflow_bit = 0x8000; | |
826 | cmt->clear_bits = ~0xc000; | |
3fb1b6ad MD |
827 | } |
828 | ||
740a9518 | 829 | ret = sh_cmt_setup_channel(&cmt->channel, cfg->timer_bit, cmt); |
b882e7b1 | 830 | if (ret < 0) |
57dee992 | 831 | goto err4; |
da64c2a8 | 832 | |
2653caf4 | 833 | platform_set_drvdata(pdev, cmt); |
adccc69e | 834 | |
da64c2a8 | 835 | return 0; |
57dee992 | 836 | err4: |
2653caf4 | 837 | clk_unprepare(cmt->clk); |
8874c5e3 | 838 | err3: |
2653caf4 | 839 | clk_put(cmt->clk); |
8874c5e3 | 840 | err2: |
2653caf4 | 841 | iounmap(cmt->mapbase); |
36f1ac98 LP |
842 | err1: |
843 | iounmap(cmt->mapbase_ch); | |
da64c2a8 | 844 | err0: |
3fb1b6ad MD |
845 | return ret; |
846 | } | |
847 | ||
1850514b | 848 | static int sh_cmt_probe(struct platform_device *pdev) |
3fb1b6ad | 849 | { |
2653caf4 | 850 | struct sh_cmt_device *cmt = platform_get_drvdata(pdev); |
bad81383 | 851 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
3fb1b6ad MD |
852 | int ret; |
853 | ||
9bb5ec88 | 854 | if (!is_early_platform_device(pdev)) { |
bad81383 RW |
855 | pm_runtime_set_active(&pdev->dev); |
856 | pm_runtime_enable(&pdev->dev); | |
9bb5ec88 | 857 | } |
615a445f | 858 | |
2653caf4 | 859 | if (cmt) { |
214a607a | 860 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
bad81383 | 861 | goto out; |
e475eedb MD |
862 | } |
863 | ||
2653caf4 LP |
864 | cmt = kmalloc(sizeof(*cmt), GFP_KERNEL); |
865 | if (cmt == NULL) { | |
3fb1b6ad MD |
866 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
867 | return -ENOMEM; | |
868 | } | |
869 | ||
2653caf4 | 870 | ret = sh_cmt_setup(cmt, pdev); |
3fb1b6ad | 871 | if (ret) { |
2653caf4 | 872 | kfree(cmt); |
bad81383 RW |
873 | pm_runtime_idle(&pdev->dev); |
874 | return ret; | |
3fb1b6ad | 875 | } |
bad81383 RW |
876 | if (is_early_platform_device(pdev)) |
877 | return 0; | |
878 | ||
879 | out: | |
880 | if (cfg->clockevent_rating || cfg->clocksource_rating) | |
881 | pm_runtime_irq_safe(&pdev->dev); | |
882 | else | |
883 | pm_runtime_idle(&pdev->dev); | |
884 | ||
885 | return 0; | |
3fb1b6ad MD |
886 | } |
887 | ||
1850514b | 888 | static int sh_cmt_remove(struct platform_device *pdev) |
3fb1b6ad MD |
889 | { |
890 | return -EBUSY; /* cannot unregister clockevent and clocksource */ | |
891 | } | |
892 | ||
893 | static struct platform_driver sh_cmt_device_driver = { | |
894 | .probe = sh_cmt_probe, | |
1850514b | 895 | .remove = sh_cmt_remove, |
3fb1b6ad MD |
896 | .driver = { |
897 | .name = "sh_cmt", | |
898 | } | |
899 | }; | |
900 | ||
901 | static int __init sh_cmt_init(void) | |
902 | { | |
903 | return platform_driver_register(&sh_cmt_device_driver); | |
904 | } | |
905 | ||
906 | static void __exit sh_cmt_exit(void) | |
907 | { | |
908 | platform_driver_unregister(&sh_cmt_device_driver); | |
909 | } | |
910 | ||
e475eedb | 911 | early_platform_init("earlytimer", &sh_cmt_device_driver); |
e903a031 | 912 | subsys_initcall(sh_cmt_init); |
3fb1b6ad MD |
913 | module_exit(sh_cmt_exit); |
914 | ||
915 | MODULE_AUTHOR("Magnus Damm"); | |
916 | MODULE_DESCRIPTION("SuperH CMT Timer Driver"); | |
917 | MODULE_LICENSE("GPL v2"); |